JP3468261B2 - Bridge type inverter device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bridge type, half bridge type or multi-phase inverter device.

[0002]

2. Description of the Related Art When a switch of a bridge type inverter for converting direct current into alternating current is turned on and off, switching loss occurs. To solve this kind of problem, the partial resonance is used to switch the switch to ZCS (Zero Current Switching) or ZVS.
It has been proposed to reduce switching loss, surge voltage, and noise by (zero voltage switching). However, there is a demand for an inverter device that can surely and easily achieve reduction of the loss of not only the main switch but also the partial resonance switch. Further, it is required to simplify the structure of the partial resonance circuit.

Therefore, an object of the present invention is to provide a bridge type inverter device which can meet the above demands.

[0004]

The invention according to claim 1 for achieving the above object will be described with reference to the reference numerals of the drawings showing an embodiment. One of the invention is provided between one end and the other end of a DC power supply. Alternatively, a plurality of switch circuits are connected, and the switch circuit connects the load with a current in a first direction and an opposite second current.
In a bridge type, half bridge type, or multi-phase bridge type inverter device configured to flow a current in the direction of, at least one of the switch circuits is connected between one end and the other end of the DC power supply 1. A main conversion circuit comprising a series circuit of first and second main switches TR1 and TR2, the interconnection point of the first and second main switches TR1 and TR2 being connected to one end of a load; A series circuit of first and second diodes D1 and D2 connected in antiparallel to the first and second main switches TR1 and TR2, and a series circuit of the first reactor L1 and the first auxiliary switch S1. One reactor L1 is arranged closer to one end side of the power source 1 than the first auxiliary switch S1 is, and
Of the reactor L1 and the first auxiliary switch S1 are connected to one end of the power source 1 and the first and second main switches TR1.
, TR2, a series circuit of a first auxiliary circuit connected between the second auxiliary switch S2 and a second auxiliary switch S2, the first auxiliary circuit being connected between the first auxiliary circuit and the second auxiliary switch S2.
2 is arranged on the other end side of the power source 1 with respect to the second auxiliary switch S2, and the second reactor L2 and the second reactor L2 are connected to each other.
Auxiliary switch S2 is connected between the interconnection point of the first and second main switches TR1 and TR2 and the other end of the power supply 1, and one end of the second auxiliary circuit is connected to the first auxiliary circuit S1. A first capacitor C1 connected to the interconnection point between the reactor L1 and the first auxiliary switch S1 and one end thereof connected to the interconnection point between the second reactor L2 and the second auxiliary switch S2. Second capacitor C
2, a third diode D3 connected between the other end of the first capacitor C1 and the interconnection point of the first and second auxiliary switches S1, S2, and the first and second A fourth diode connected between the interconnection point of the auxiliary switches S1 and S2 and the other end of the second capacitor C2, the first capacitor C1 and the first reactor L1 are connected in series. A fifth diode D5 connected in parallel to the connected circuit, and a fifth diode D5 connected in parallel to the connected circuit in which the second reactor L2 and the second capacitor C2 are connected in series. 6 diode D
6 and one end thereof has the first and second auxiliary switches S1
, S2, a third capacitor C3 connected to the interconnection point
And one end thereof has the first and second auxiliary switches S1.
, S2, a fourth capacitor C4 connected to the interconnection point
A third reactor L3 having one end connected to the other end of the third capacitor C3; a fourth reactor L4 having one end connected to the other end of the fourth capacitor C4; The third diode D7 connected between the other end of the third reactor L3 and the other end of the first capacitor C1, the other end of the second capacitor C2 and the fourth reactor L4. An eighth diode D8 connected between the other end, the third capacitor C3 and the second diode D8.
Ninth diode D9 connected in parallel to the series circuit of the auxiliary switch S2 and the second reactor L2.
A tenth diode D10 connected in parallel to a series circuit of the fourth capacitor C4, the first auxiliary switch S1 and the first reactor L1, and the first and second diodes. For turning on the main switches TR1 and TR2 of each of them alternately with a dead time at a predetermined cycle.
And a second main control pulse to generate a second main control pulse, and at least the first auxiliary control pulse for controlling to turn on the first auxiliary switch S1 from the trailing edge of the second main control pulse to the first main control pulse. A second auxiliary control pulse, which is generated so as to include a part of the period up to the leading edge of the pulse, is used to turn on the second auxiliary switch S2 at least from the trailing edge of the first main control pulse. A switch control circuit which includes a part of the period up to the leading edge of the second main control pulse and which is generated so as to have a predetermined time gap with the first auxiliary control pulse. The present invention relates to a characteristic inverter device. As described in claim 2, the first
The first and second auxiliary resonance capacitors Ca and Cb can be connected in parallel to the first and second main switches TR1 and TR2. Further, as shown in claim 3, the first and second main switches TR1 and TR2 of claim 1 can be omitted and the first and second auxiliary switches S1 and S2 can be used as conversion switches.

[0005]

According to the inventions of claims 1 and 2,
During turn-off and turn-on of the first and second main switches TR1 and TR2, and the first and second auxiliary switches S
ZVS occurs when turning off 1 and S2, and ZC when turning off the first and second auxiliary switches S1 and S2.
Since it becomes S, the switching loss, the surge voltage, and the noise can be reduced. Further, the partial resonance operation can be obtained with a single power source having no midpoint potential, and the power source configuration is simplified. According to the second aspect of the present invention, energy can be supplied to the resonance circuit by the first and second auxiliary resonance capacitors Ca and Cb, and stable resonance operation can be obtained. According to the invention of claim 3, the first
Also, ZVS is turned off when the second switches S1 and S2 are turned off, and ZCS is turned off when the switches are turned off, so that switching loss, surge voltage, and noise can be reduced. Further, the partial resonance operation can be obtained with a single power source having no midpoint potential, and the power source configuration is simplified.

[0006]

[First Embodiment] Next, a bridge type inverter device according to a first embodiment of the present invention will be described with reference to FIGS.
As shown in FIG. 1, this inverter device is configured to convert a DC voltage of a DC power supply 1 into an AC by a bridge type inverter circuit and supply the AC to a load 2. The DC power supply 1 is composed of a rectifier circuit or a battery, and the load 2 is composed of, for example, an output transformer 3 connected to the load connection terminals 2a and 2b and a load circuit 4 connected to the output transformer 3.

The inverter circuit is composed of a combination of first and second switch circuits 5a and 5b having a half bridge structure. The first switch circuit 5a is a first and second main switch TR1 for forming a first arm of the bridge circuit.
, TR2 and the first and second diodes D1, D2, in addition to the first and second auxiliary switches S1, S2 and the first, second, third to achieve ZVS or ZCS.
And the fourth capacitors C1, C2, C3, C4 and the first, second, third and fourth reactors L1, L2, L3.
, L4 and the third, fourth, fifth, sixth, seventh, eighth, ninth and tenth diodes D3, D4, D5, D6, D.
7, D8, D9, D10 and first and second resistors R1, R2 as capacitor charging means. The second switch circuit 5b has third and fourth main switches TR3, TR4 and eleventh and twelfth diodes D11, D12 to form a second arm of the bridge circuit, and
To achieve ZVS, ZCS, third and fourth auxiliary switches S3, S4 and fifth, sixth, seventh and eighth capacitors C5, C6, C7, C8 and fifth, sixth, 7th
And the eighth reactor L5, L6, L7, L8, and the first reactor
3 to 20th diodes D13 to D20. In addition,
Each of the switches TR1 to TR4 and S1 to S4 is composed of a bipolar transistor.

First and second for forming a main conversion circuit
The series circuit of the main switches TR1 and TR2 is connected between one end and the other end of the power source 1, and the first and second main switches T1 and TR2 are connected.
The interconnection point of R1 and TR2 is connected to the first load connection terminal 2a as an output terminal. The first and second diodes D1 and D2 are connected to the first and second main switches TR1 and TR1,
It is connected in anti-parallel to TR2. The series circuit of the third and fourth main switches TR3 and TR4 is also connected between one end and the other end of the power source 1, and the third and fourth main switches TR3 and T4 are connected.
The interconnection point of R4 is connected to the second load connection terminal 2b. The eleventh and twelfth diodes D11, D12 are anti-parallel connected to the third and fourth main switches TR3, TR4. The first to fourth main switches TR1 to TR
4 is an insulated gate type (MOS type) field effect transistor having a structure in which the source is connected to the substrate, and the diodes incorporated therein are the first, second, eleventh and twelfth diodes D1, D2, D11. , D12.

A first auxiliary consisting of a series circuit of a first auxiliary switch S1 and a first reactor L1 between one end of the power supply 1 and the interconnection point of the first and second main switches TR1 and TR2. The circuit is connected. A second reactor L2 and a second auxiliary switch S are provided between the interconnection point of the first and second main switches TR1 and TR2 and the other end of the power source 1.
A second auxiliary circuit consisting of a series circuit with 2 is connected. The first reactor L1 is arranged closer to the positive terminal side of the power source 1 than the first auxiliary switch S1 is, and the second reactor L1 is
2 is arranged closer to the negative terminal side of the power source 1 than the second auxiliary switch S2.

One end of the first capacitor C1 is connected to the interconnection point of the first reactor L1 and the first auxiliary switch S1, and one end of the second capacitor C2 is connected to the second reactor L2 and the second auxiliary switch S1. It is connected to the interconnection point with the switch S2. The third diode D3 is connected to the other end of the first capacitor C1 and the first and second auxiliary switches S1 and S2.
And the fourth diode D4 is connected between the connection point P1 and the other end of the second capacitor C2. That is, the third and fourth diodes D
3 and D4 are connected in parallel to the first and second switches S1 and S2 via the first and second capacitors C1 and C2.

The fifth and sixth diodes D5 and D6 are connected in parallel to the first and second reactors L1 and L2 via the first and second capacitors C1 and C2. Third and fourth capacitors C3 having the same capacitance,
One end of C4 is connected to the interconnection point P1 of the first and second auxiliary switches S1 and S2, respectively. The other end of the third capacitor C3 is connected to the other end of the first capacitor C1 via the third reactor L3 and the seventh diode D7, and the other end of the fourth capacitor C4 is connected to the fourth reactor L4. It is connected to the other end of the second capacitor C2 via the eighth diode D8. The ninth diode D9 is connected between the lower terminal of the second reactor L2 and the other end (upper end) of the third capacitor C3. That is, the ninth diode D9 is connected in parallel to the series connection circuit of the third capacitor C3, the second auxiliary switch S2 and the second reactor L2. The tenth diode D10 is connected between the other end (lower end) of the fourth capacitor C4 and the upper terminal of the first reactor L1. That is, the tenth diode D10 is connected in parallel to the series connection circuit of the first reactor L1, the first auxiliary switch S1 and the fourth capacitor C4. The charging resistors R1 and R2 are connected in parallel to the ninth and tenth diodes D9 and D10. The capacitances of the third and fourth capacitors C3, C4 are the same as those of the first and second capacitors C1,
It may be the same as or different from the capacity of C2. In this embodiment, C3 and C4 have a larger capacity than C1 and C2. The inductance values of the reactors L3 and L4 may be the same as or different from those of L1 and L2. In this embodiment, L3, L4 are L1,
Less than L2.

The second switch circuit 5b is substantially the same circuit as the first switch circuit 5a. Therefore, the correspondence between the first and second switch circuits 5a and 5b is shown below, and the detailed description of the second switch circuit 5b is omitted.
Main switches TR3, TR4 are TR1, TR2, auxiliary switches S3, S4 are S1, S2, diodes D11-D20 are D1-D10, capacitors C5-C8 are C1-C4, reactors L5-L8 are L1-L4, resistors. R3 and R4 are R1
, R2, respectively, and the mutual connection of the circuit elements of the second switch circuit 5b is the same as that of the first switch circuit 5a.

In FIG. 1, some of the connecting lines between them are omitted for convenience of illustration, but the switches TR1 to TR4 are not shown.
, S1 to S4 control terminals (bases) are connected to the control circuit 6. As shown in principle in FIG. 2, the control circuit 6 includes first, second, third and fourth main control pulse generation circuits 7, 8, 9, 10 and first to fourth auxiliary control pulse generation circuits. It has circuits 11, 12, 13, and 14, an oscillator 15, and a phase control circuit 16. The first and second main control pulse generation circuits 7 and 8 are controlled by the oscillator 15 to generate a signal shown in FIG.
The first and second main control pulses shown in (B) are generated at a constant cycle, and the first and second main switches TR1 and T1 are generated.
Supply to the base of R2. The third and fourth main control pulse generation circuits 9 and 10 are controlled by the oscillator 15 and the phase control circuit 16 to generate the third and fourth main control pulses shown in FIGS. 3C and 3D, This is the third and fourth main switch T
Supply to the base of R3 and TR4. The first and second main control pulses and the third and fourth main control pulses are the same except that they have a phase difference between them. 3 (A), (B)
The first and second main control pulses of are alternately generated with a time gap (dead time) Ta between them, as shown in FIG.
The third and fourth main control pulses in (D) also occur alternately with a time gap Ta. In this time gap Ta, the auxiliary switches S1, S2, S3 and S4 are turned on while the capacitors C3, C4, C7 and C6 are charged, and almost all the charges of C3, C4, C7 and C8 are generated by the resonance operation. The time required for release is set. That is, Ta
Is 0 to 90 degrees of the waveform of the resonance current of C3 L2 or C4 L1.
It is set to a degree or more.

The first auxiliary control pulse generation circuit 11 has a second
Is connected to the main control pulse generating circuit 8 of FIG. 3 and generates a pulse after the trailing edge of the second main control pulse of FIG. The width of the first auxiliary control pulse supplied to the first auxiliary switch S1 is the second
Of the auxiliary control pulse of the second control pulse, and at least a part of the trailing edge time of the second main control pulse to the leading edge time of the first control pulse. The second auxiliary control pulse generation circuit 12 is connected to the first main control pulse generation circuit 7, and as shown in FIG.
The pulse is generated at the trailing edge of the first main control pulse in (A) or a certain time after this. Second auxiliary switch S2
The width of the second auxiliary control pulse supplied to the first auxiliary control pulse has a dead time between the second auxiliary control pulse and
Of the trailing edge of the main control pulse to the leading edge of the second main control pulse. The third and fourth auxiliary control pulse generation circuits 13 and 14 are connected to the fourth and third main control pulse generation circuits 10 and 9 as shown in FIG. 1st and 2nd
The third and fourth auxiliary control pulses are formed such that a relationship similar to the relationship with the main control pulse of the above is obtained between the fourth and third main control pulses.

[0015]

[Operation] The basic operation of the inverter circuit of FIG. 1 is the same as that of a known inverter. That is, while the main switches TR1 and TR4 shown in FIGS. 1 and 4 are turned on at the same time, the current in the first direction is generated in the circuit composed of the power source 1, the first main switch TR1, the load 2 and the fourth main switch TR4. Flow to load 2, second
Also, while the third main switches TR2 and TR3 are simultaneously turned on, a current in the second direction flows through the load 2 in the circuit composed of the power source 1, the third main switch TR3, the load 2 and the second main switch TR2. .

Next, the first to fourth main switches TR1 to T
The operation of R4 during the turn-on and turn-off periods will be described. However, the operation during the turn-off period of the first main switch TR1 and the turn-on of the second main switch TR2 shown at t1 to t4 in FIG. 3, the turn-off of the second main switch TR2 and the turn-on of the first main switch TR1. And the operation during the turn-off period of the third main switch TR3 and the fourth main switch TR4.
The operation during the turn-off period of the fourth main switch TR4 and the turn-off period of the third main switch TR3 is substantially the same, so the operation during the t1 to t4 period of FIG. 3 will be described in detail with reference to FIG. The description of the operation in other periods is omitted.

[0017]

[Capacitor charging operation] First and second capacitors C1
, C2 are charged in the L1-C1-D3-D4-C2-L2 circuit during the off period of the first and second main switches TR1, TR2. Further, in this embodiment, for example, it is necessary to precharge the third and eighth capacitors C3 and C8 in the directions shown in FIG. In order to perform this charging, the first and fourth main switches TR1 and TR4 are turned on. As a result, a charging current flows in the circuit of the first main switch TR1, the third capacitor C3 and the first resistor R1, and the third capacitor C3 is charged to the power supply voltage V. The fourth resistor R4, the eighth capacitor C8 and the fourth main switch T
A current also flows through the circuit of R4, and the eighth capacitor C8 is charged. Of course, conversely to the above, the fourth and seventh capacitors C4 and C7 can be precharged. First
After the inverter operation by the fourth main switches TR1 to TR4 is started, the third and fourth capacitors C3,
The loss in the resonance of C4 is the main switches TR1 to TR4.
Is replenished via.

[0018]

[Turn-off and turn-on operation] FIG. 4 shows the state of each part of FIG. 1 in the t1 to t4 section of FIG. 3 and its vicinity when the load circuit 4 is unloaded and the load 2 is a delay load of only the transformer. First and second capacitors C1
, C2 are charged, and the third capacitor C3 is almost charged to the power supply voltage V, at time t1, the first main switch TR1 is turned off, and at the same time, the second auxiliary switch S2 is turned on.
When turned on, the energy of the third capacitor C3 is released in the resonant circuit consisting of the third capacitor C3, the second auxiliary switch S2, the second reactor L2 and the ninth diode D9, Voltage V of capacitor C3
As shown in FIG. 4E, c3 decreases in the waveform of the sine wave in the 90 to 180 degree section. At this time, since the ninth diode D9 is on, the third main switch TR2 has a third diode across both ends.
The voltage Vc3 of the capacitor C3 of will be applied,
As shown in FIG. 4 (H), the voltage Vtr2 of the second main switch TR2 decreases toward zero from t1 to t2. Further, the voltage Vtr1 of the first main switch TR1 becomes a value obtained by subtracting the voltage Vtr2 of the second main switch TR2 from the power supply voltage V, and rises slowly as shown in FIG. 4 (G). When the second auxiliary switch S2 is turned on at time t1, the second capacitor C2, the eighth diode D8, the fourth reactor L4, the fourth capacitor C4, and the second capacitor C2 serve as a discharge circuit for the second capacitor C2. A circuit composed of the auxiliary switch S2 is formed, and the voltage Vc2 of the second capacitor C2 is shown in FIG.
It becomes zero at t2 as shown in (K). Further, the fourth capacitor C4 is charged as shown in FIG. Current I _L2 of the second reactor L2 flows in 0-90 ° segment of the waveform of the sine wave from the time t1 as shown in FIG. 4 (I). When the current I _L2 of the second reactor L2 reaches almost the peak value of the sine wave at time t2, the second reactor L2
The voltage of 2 becomes 0V, the voltage Vc3 of the third capacitor C3 also becomes zero, the reverse bias of the second diode D2 is released, and the current I _L2 due to the release of the stored energy of the second reactor _L2 becomes the second Of the second reactor L2, the second diode D2, and the second auxiliary switch S2 as a circulating current. When the ON control signal is applied to the second main switch TR2 at or near the time t2 at which the second diode D2 is converted to the forward bias, the second main switch T2 is supplied.
R2 ZVS is achieved. The preferred range at the start of turning on the second main switch TR2 is t2 to t3. Second
If the second auxiliary switch S2 is kept on after the time t2 when the voltage Vc2 of the capacitor C2 of the same becomes zero, the second reactor L2 and the second diode D2 are turned on.
Circulating current continues to flow in the closed circuit with the second auxiliary switch S2, resulting in power loss. Therefore, the second auxiliary switch S
Turn off 2 at t3. At this time t3, the voltage Vc2 of the second capacitor C2 and the voltage Vs2 of the second auxiliary switch S2 shown in FIG. 4 (M) are zero, so the second auxiliary switch S2 becomes ZVS. When the second auxiliary switch S2 is turned off at t3, the current flowing in the second reactor L2 is changed to the second reactor L2 and the sixth diode D6.
And a second capacitor C2 are commutated to a closed circuit, the second capacitor C2 is charged, and this voltage Vc2 rises in the waveform of the sine wave in the 0 to 90 degree section, as shown in FIG.
The power supply voltage becomes V. With the above operation, the voltage Vc3 of the third capacitor C3 is zero at time t4, the voltages Vc2 and Vc4 of the second and fourth capacitors C2 and C4 are charged to the power supply voltage V, and the voltage of the first capacitor C1 is increased. Is maintained at the power supply voltage V, the conditions for turning off the second main switch TR2 and turning on the first main switch TR1 are satisfied. The second auxiliary switch S2 may be turned on slightly after the turn-off time t1 of the first main switch S1.

When the second main switch TR2 is turned off, the first auxiliary switch S1 is turned on at the same time, and the fourth capacitor C4, the tenth diode D10, the first reactor L1 and the first auxiliary switch S1 are turned on. A resonance circuit with S1 is formed, and a current corresponding to the section from t1 to t2 in FIG. 4 flows in this circuit. Further, the discharge of the first capacitor C1 is caused by the first capacitor C1 and the first auxiliary switch S1.
And the third capacitor C3, the third reactor L3 and the seventh
Occurs in the closed circuit of the diode D7 of the. When the current in the first reactor L1 reaches a peak, this voltage becomes zero, the first diode D1 becomes forward biased, and the first reactor L1, the first auxiliary switch S1, and the first diode D1 A circuit is formed. Therefore, the first and second main switches TR1 and TR2 and the first auxiliary switch S
A ZVS of 1 is achieved. The second switch circuit 5
The same operation also occurs in b, and the same effect can be obtained.

In FIG. 4, the load 2 is explained as no load.
Is regarded as a resistance, a current corresponding to the voltage applied to the load 2 is applied to the first to fourth main switches TR1 to TR4.
Flowing through. At this time, even if the storage currents of the main switches TR1 to TR4 flow, the voltages of the first to fourth main switches TR1 to TR4 do not rise suddenly at the turn-off time, so that the power loss is small.

This embodiment has the following effects. (1) ZVS (zero current switch) when the main switches TR1 to TR4 are turned on and off and the auxiliary switches S1 to S4 are turned off, and ZVS (zero current switch) when the auxiliary switches S1 to S4 are turned on. Therefore, switching loss, surge voltage, and noise can be reduced. (2) Since the snubber circuit has substantially no loss, efficiency improvement is achieved. (3) PWM control with a constant frequency is possible, and voltage control can be easily performed. (4) Partial resonance operation can be obtained with a single power source having no midpoint potential, and the configuration is simplified. (5) Reactor L through diode D1 or D2
Since there is a period in which the circulating current of 1 or L2 flows, the degree of freedom at the time of turn-on becomes high.

[0022]

Second Embodiment Next, a bridge type inverter device according to a second embodiment of the present invention will be described with reference to FIG.
However, in FIG. 5 and FIG. 6 to be described later, the same parts as those in FIG. The inverter circuit of FIG. 5 is obtained by adding four auxiliary resonance capacitors Ca, Cb, Cc and Cd to the inverter circuit of FIG. First and second auxiliary resonance capacitors Ca and C
b is connected in parallel to the first and second main switches TR1 and TR2. The capacitors Cc and Cd are connected in parallel to the third and fourth main switches TR3 and TR4. The configuration of the circuit of FIG. 5 is the same as that of FIG. 1 except for the above.

The main switches TR1 to TR4 and the auxiliary switches S1 to S4 of FIG. 5 are driven as shown in FIG. 3 similarly to those of FIG. Therefore, the basic operation of the inverter of the circuit of FIG. 5 is the same as that of FIG. By the way, in the circuit of FIG. 1, if the voltage of the third, fourth, seventh and eighth capacitors C3, C4, C7 and C8 is insufficient to reach the power supply voltage V, ZVS cannot be achieved well. Also, the third, fourth, seventh and eighth capacitors C3, C4, C7
, C8 is fully charged to the power supply voltage V,
Ldi / dt depends on the wiring inductance of the switch circuit
Voltage is generated between the switches and does not become ZVS.
The first and second auxiliary resonance capacitors Ca to Cd of FIG.
Is provided to solve the above problems.

The third capacitor C3, the second capacitor C2, and the second auxiliary resonance capacitor Cb are charged to the power supply voltage V, the capacitor Ca is at zero volt, and the first main switch TR1 is turned off. When the second auxiliary switch S2 is turned on, the resonance current due to the discharge of the third capacitor C3 and the resonance current due to the discharge of the second capacitor C2 flow as in the circuit of FIG. At the same time, resonance also occurs in the circuit composed of the second auxiliary resonance capacitor Cb, the second auxiliary switch S2, and the second reactor L2. As a result, the voltage of the second auxiliary resonance capacitor Cb or the same voltage Vc3 of the third capacitor C3 as the same is applied across the second main switch TR2, and the second main switch TR2 is applied. The voltage Vtr2 of the device decreases toward zero. Further, the voltage Vtr1 of the first main switch TR1 becomes a value obtained by subtracting the voltage Vtr2 of the second main switch TR2 from the power supply voltage V, and rises slowly. Figure 5
In this circuit, since energy is supplied from the second auxiliary resonance capacitor Cb to the second reactor L2, the energy shortage of the resonance circuit is compensated. This function and effect can be obtained based on the first auxiliary resonance capacitor Ca when the second main switch TR2 is turned off and the first main switch TR1 is turned on. Since the first and second auxiliary resonance capacitors Ca and Cb are directly connected between the terminals of the power source 1, they are reliably charged to the power source voltage V. Therefore,
After starting the inverter, the resistors R1 to R4 can be disconnected from the circuit. In the circuit of FIG. 5, the capacitor Ca
Since the operations other than the auxiliary resonance of .about.Cd are the same as those of the circuit of FIG. 1, they have the same effects as those of the first embodiment.

[0025]

[Third Embodiment] In the inverter device of the third embodiment shown in FIG. 6, the first to fourth main switches TR1 to T in the circuit shown in FIG.
The structure is the same as that of FIG. 1 except that R4 is removed.
Although the switches from the transistors indicated by S1, S2, S3 and S4 in FIG. 6 are arranged at the same positions as the auxiliary switches S1 to S4 indicated by the same reference numerals in FIG. 1, they function as conversion switches. Therefore, in FIG. 6, they will be referred to as first to fourth switches. First to first in FIG.
The bases of the fourth switches S1 to S4 are shown in FIG.
The control signal shown in (D) is supplied. The operation of supplying AC power to the load 2 by turning on / off the first to fourth switches S1 to S4 is the first to fourth main switch TR1 of FIG.
The operation is the same as the operation of supplying AC power to the load 2 when the TTR4 is turned on and off.

FIG. 7 shows the states of the respective parts when the first switch S1 of FIG. 6 is turned off and the second switch S2 is turned off. Now, as shown immediately before t1 in FIG. 7, the second and third capacitors C2, C3 are charged to the power supply voltage V as in FIG. 4, and the first reactor L1, the first switch S1, and the first switch S1 are connected. When the first switch S1 is turned off at t1 when the circulating current is flowing in the closed circuit of the diode D1, the current I _L1 of the first reactor L1 becomes equal to that of the first reactor L1 and the first reactor L1. Commutated into the closed circuit of the capacitor C1 and the fifth diode D5, the resonance current of L1 C1 flows, and the current I _L1 of the first reactor L1 as shown in FIG. 7 (E).
Decreases in the waveform of the section of the sine wave 90 to 180. As a result, the voltage Vc1 of the first capacitor C1 gradually increases in the waveform of the 0-90 degree section of the sine wave as shown in FIG. 7 (G). The voltage Vs1 of the first switch S1 is substantially the same as the capacitor voltage Vc1 of FIG. 7 (G) as shown in FIG. 7 (I), and ZVS is achieved because it rises as a sine wave from t1.

When the second switch S2 is turned on at the time t2 in FIG. 7 when the second and third capacitors C2 and C3 are charged, the energy of the third capacitor C3 is changed to the third capacitor C3. The resonance current I _{L2 of} C3 L2 flows as shown in FIG. 7 (F) by being discharged by the closed circuit of the second switch S2, the second reactor L2 and the ninth diode D9. A closed circuit of C2-D8-L4-C4-S2 is also formed. As a result, in the section from t2 to t3, the third
The voltage Vc3 of the capacitor C3 of the second capacitor L4 decreases as shown in FIG. 7C, the voltage Vc4 of the fourth capacitor C4 increases as shown in FIG. 7D, and the current IL2 of the second reactor _L2.
Rises as a sine wave as shown in FIG. 7 (F), the voltage Vc2 of the second capacitor C2 decreases as shown in FIG. 7 (H), and the current I _L4 of the fourth reactor L4 as shown in FIG. 7 ( As shown in K), it flows in a sine wave. Second switch S2
Since the current flowing through this gradually increases when turned off,
ZCS is achieved. The operation in the section t2 to t3 in FIG. 7 is substantially the same as the operation in the section t1 to t2 in FIG. Also, when the second switch S2 is turned off, the same operation as in FIG. 7 occurs.

As is apparent from the above, the inverter device of FIG. 6 can obtain the same operational effect as that of the inverter device of FIG. The inverter device shown in FIG.
The circuit configuration is simplified as much as the switches TR1 to TR4 are omitted.

[0029]

MODIFICATION The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible. (1) It is possible to configure a three-phase or multi-phase bridge type inverter device by preparing three or a large number of ones corresponding to the first switch circuit 5a in each embodiment and connecting three-phase or multi-phase. . (2) Main switches TR1 to TR4, auxiliary switch S1
~ S4 can be a semiconductor switch such as a field effect transistor. Moreover, these can be made into the anti-parallel diode built-in element. (3) In the first embodiment, for example, the time when the second auxiliary switch S2 is turned on is slightly after the time when the first main switch TR1 is turned off, as shown by the dotted line in FIG. Can be at a previous point in time. Even in this way, ZVS when the first and second main switches TR1 and TR2 are turned on and off, ZCS (zero current switch) when the first and second auxiliary switches S1 and S2 are turned on, and ZVS when turned off. Is possible. (4) In each embodiment, the charging resistors R1 to R4 can be omitted and the initial charging of each capacitor can be performed by an independent charging circuit. Further, the charging resistors R1 to R4 can be replaced with switches to selectively flow the charging current.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an inverter device of a first embodiment.

FIG. 2 is a block diagram showing a control circuit of FIG.

FIG. 3 is a waveform diagram of each part of FIG.

FIG. 4 is a waveform diagram of each part of FIG.

FIG. 5 is a circuit diagram of an inverter device according to a second embodiment.

FIG. 6 is a circuit diagram of an inverter device according to a third embodiment.

7 is a waveform diagram of each part of FIG.

[Explanation of symbols] TR1 to TR4 main switch S1 to S4 auxiliary switch

Claims (3)

(57) [Claims] 1. One or a plurality of switch circuits are connected between one end and the other end of a DC power supply, and the switch circuit connects a load with a current in a first direction and a second direction opposite thereto. In a bridge type, half bridge type, or multi-phase bridge type inverter device configured to flow current, at least one of the switch circuits is connected between one end and the other end of the DC power supply (1). It is composed of a series circuit of first and second main switches (TR1, TR2), and includes the first and second main switches (TR1, T2).
A main conversion circuit having an interconnection point of R2) connected to one end of a load, and first and second diodes (D1, D1 connected in antiparallel to the first and second main switches (TR1, TR2)). D2
), The first reactor (L1) and the first auxiliary switch (S1
) In a series circuit with the first reactor (L1
) Is disposed closer to one end of the power source (1) than the first auxiliary switch (S1), and the first reactor (L)
1) and the first auxiliary switch (S1) are connected to one end of the power source (1) and the first and second main switches (TR1).
, TR2) first connected to the interconnection point
Auxiliary circuit, the second reactor (L2) and the second auxiliary switch (S2
) In series circuit with the second reactor (L2
) Is arranged on the other end side of the power source (1) with respect to the second auxiliary switch (S2), and the second reactor (L)
2) and the second auxiliary switch (S2) are connected between the interconnection point of the first and second main switches (TR1, TR2) and the other end of the power source (1). Two auxiliary circuits, one end of which is connected to an interconnection point between the first reactor (L1) and the first auxiliary switch (S1)
Capacitor (C1), a second capacitor (C2) whose one end is connected to an interconnection point between the second reactor (L2) and the second auxiliary switch (S2), and the first capacitor A third diode (D3) connected between the other end of (C1) and the interconnection point of the first and second auxiliary switches (S1, S2); and the first and second auxiliary switches. A fourth diode (D4) connected between the interconnection point of (S1, S2) and the other end of the second capacitor (C2), the first capacitor (C1) and the first diode (D1). A fifth diode (D5) connected in parallel to a circuit in which a reactor (L1) is connected in series, the second reactor (L2) and the second capacitor (C2) are connected in series. A sixth connected in parallel to the circuit connected to A diode (D6), one end of said first and second auxiliary switches (S1, S
2) A third capacitor (C3
) And one end thereof is the first and second auxiliary switches (S1, S)
2) A fourth capacitor (C4
), A third reactor (L3) having one end connected to the other end of the third capacitor (C3), and a fourth reactor having one end connected to the other end of the fourth capacitor (C4). A reactor (L4), a seventh diode (D7) connected between the other end of the third reactor (L3) and the other end of the first capacitor (C1), and An eighth diode (D8) connected between the other end of the second capacitor (C2) and the other end of the fourth reactor (L4); the third capacitor (C3); A ninth diode (D9) connected in parallel to the series circuit of the second auxiliary switch (S2) and the second reactor (L2).
And a tenth diode (D1) connected in parallel to the series circuit of the fourth capacitor (C4), the first auxiliary switch (S1) and the first reactor (L1).
0), and generating first and second main control pulses for alternately turning on the first and second main switches (TR1, TR2) at a predetermined period with a dead time, The first
The first auxiliary control pulse for controlling the ON of the auxiliary switch (S1) is at least part of the period from the trailing edge of the second main control pulse to the leading edge of the first main control pulse. A second auxiliary control pulse for turning on the second auxiliary switch (S2) is generated at least from the trailing edge of the first main control pulse to the leading edge of the second main control pulse. And a switch control circuit for generating a predetermined time gap between the first auxiliary control pulse and the first auxiliary control pulse. 2. Further comprising first and second auxiliary resonance capacitors (Ca, Cb) connected in parallel to the first and second main switches (TR1, TR2). An inverter device according to claim 1. 3. One or a plurality of switch circuits are connected between one end and the other end of the DC power supply, and the switch circuits connect a current in a first direction and a current in a second direction opposite thereto. In a bridge type, half-bridge type or multi-phase bridge type inverter device configured to flow a current, at least one of the switch circuits comprises a first reactor (L1) and a first switch (S1) in series. A circuit, wherein the first reactor (L1) is arranged closer to one end of the power source (1) than the first switch (S1), and the first reactor (L1) and the first switch are arranged. (S1) is connected between one end of the power source (1) and one end of the load, and a series circuit of a second reactor (L2) and a second switch (S2). And the second reactor The torque (L2) is arranged on the other end side of the power source (1) with respect to the second switch (S2), and the second reactor (L2) and the second switch (S2) are connected to the load. A second circuit connected between one end and the other end of the power supply (1), and first and second diodes (D1, D2) connected in parallel to the first and second circuits. ), A first capacitor (C1) whose one end is connected to an interconnection point of the first reactor (L1) and the first switch (S1), and one end of which is the second reactor (C1). L2) and a second capacitor (C2) connected to an interconnection point between the second switch (S2), the other end of the first capacitor (C1) and the first and second switches (S1). , S2) and a third diode (D3) connected to the interconnection point of the A fourth diode (D4) connected between the interconnection point of the first and second switches (S1, S2) and the other end of the second capacitor (C2); and the first capacitor (C1). ) And the first reactor (L1) are connected in series to a fifth diode (D5) connected in parallel, the second reactor (L2) and the second capacitor. A sixth diode (D6) connected in parallel to a circuit in which (C2) is connected in series, and one end of which is the first and second switches (S1, S2).
A third capacitor (C3) connected to the interconnection point of
And one end thereof has the first and second switches (S1, S2)
Fourth capacitor (C4) connected to the interconnection point of
A third reactor (L3) having one end connected to the other end of the third capacitor (C3), and a fourth reactor having one end connected to the other end of the fourth capacitor (C4). A reactor (L4), a seventh diode (D7) connected between the other end of the third reactor and the other end of the first capacitor (C1), and the second capacitor (L7). An eighth diode (D8) connected between the other end of C2) and the other end of the fourth reactor (L4), the third capacitor (C3), and the second switch (D8). A ninth diode (D9) connected in parallel to the series circuit of S2) and the second reactor (L2).
And a tenth diode (D10) connected in parallel to the series circuit of the fourth capacitor (C4), the first switch (S1) and the first reactor (L1).
And dead the first and second switches (S1, S2)
An inverter device, comprising: a switch control circuit that alternately turns on in a predetermined cycle with time.