JP3468546B2 - Image signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high-efficiency coding of an image signal, and more particularly to improvement of coding efficiency when an image signal is used as a motion compensation inter-frame code. It relates to an enabling device. 2. Description of the Related Art Inter-frame encoding for encoding a difference signal between frames has become mainstream in high-efficiency encoding of image signals. In addition, recently, we have measured the amount of frame movement,
A motion-compensated inter-frame coding method for performing inter-frame coding after correcting a motion is often used. In order to improve the coding efficiency in the inter-frame coding and the motion compensation inter-frame coding, noise removal between frames may be performed as preprocessing. FIG. 1 shows a general conventional noise elimination circuit. The image signal is input from input 1 as a one-dimensional signal sequence. The input image signal is delayed by the delay circuit 2 by a predetermined time. The delayed signal 3 is subtracted by the difference circuit 4 from the input signal 1 and is input to the noise correction circuit 6. The noise correction circuit 6 converts the input difference image 5 into a noise correction signal 7. The noise correction signal 7 is added to the delayed signal 3 in the addition circuit 8 to obtain an image signal 9 from which noise has been removed. Normally, by setting the delay amount of the delay circuit 2 to one frame, an operation with the pixel at the same position one frame before is performed. The noise correction circuit 6 can remove noise by performing, for example, non-linear processing as shown in FIG. In FIG. 2, when the input is in the range of ± 10, the input is halved and output. In other cases, a value obtained by subtracting 5 from the input is used when the input is positive, and a value obtained by adding 5 is used when the input is negative. Output. That is, when the input is in the range of ± 10, it is determined that there is no change in the image, and noise between frames is removed. By halving the difference image 5, an average value of the signal 1 and the signal 3 is obtained in the output image signal 9. In the range other than the above, the input signal is output almost as it is.
However, to eliminate signal discontinuity at the boundary,
A level shift of 5 or -5 is performed. The noise of the input signal can be reduced by delaying the input image signal by one frame time and performing an operation with the pixel at the same position in the next frame. However, this method cannot remove noise from an image that moves such that the entire screen moves in parallel. In order to solve the above-mentioned problems, the present invention detects a portion most similar to an input image from a delayed image, and then calculates a pixel corresponding to the detected portion. I do. According to the above-mentioned means, noise can be removed even from a moving image. Furthermore, when performing high-efficiency encoding of an image from which noise has been removed, an improvement in encoding efficiency can be expected. An embodiment of the present invention will be described with reference to the embodiment shown in FIG.
The embodiment of FIG. 3 performs the same operation as that of FIG. FIG.
23 is the part of the present invention. The input image is input to a delay amount determining circuit 20. The delay amount determination circuit 20 detects the image most similar to the input image among the already input images, and determines and outputs the detected portion and the delay amount 22 of the currently input image. The output delay amount 22 is input to the variable delay circuit 21. The variable delay circuit 21 outputs the delay signal 3 obtained by delaying the input signal 1 by the amount indicated by the delay amount 22. Hereinafter, noise removal can be performed by performing the same processing as in FIG. FIG. 4 shows an embodiment of the delay amount determining circuit. In order to determine the optimum delay amount, the delay amount determination circuit 20 determines some candidates for the delay amount in advance, and selects the optimum one from them. The selection of the optimum delay amount is performed in units of a plurality of adjacent pixels. In the following embodiment, two horizontal pixels,
An example is shown in which the optimum delay amount is obtained in units of four pixels of two vertical pixels. An image signal 1 input in FIG.
1-2 is stored in the memory (detected image).
At this time, the image of the previous frame is stored in the other memory (reference image). Reference image is switch 10
4. The signal is input to the arithmetic unit 50a via the signal destination 105 and the switch 57. On the other hand, the reference image is the switch 10
2. The signal is input to the arithmetic unit 50a via the signal line 103. The arithmetic unit 50a, as shown in FIG. 5, uses a subtractor 51, an absolute value circuit 53, and an accumulation addition circuit 54 to accumulate the accumulation value 55 of the sum of the absolute values of the differences between the two signal values.
Is calculated. The accumulated addition value 55 becomes smaller as the two signals are more similar, and becomes the minimum value 0 when the two signals match. In FIG. 4, the detection signal 40 input to the arithmetic unit 50a is delayed by one or two clocks by the variable delay circuit 31, and then compared with the previous reference image signal 103 in the arithmetic unit 50b.
Hereinafter, similarly, in the arithmetic units 50c, 50d and 50e, the detection signals 42, 43 and 4
4 and the reference signal 103 are compared. Calculation result 55
The smallest one of a, 55b, 55c, 55d, and 55e is selected by the comparison circuit 56, and the corresponding delay amount is output to the signal 22. FIG. 6 shows details of the variable delay circuit 31. As the input signal 40, one of the signal 203 delayed by the one-clock delay circuit 200 and the signal 204 further delayed by the one-clock delay circuit 201 is output as a selection indicator 41 by the switch 202. FIG. 7 shows a timing chart of the operation of FIG. FIG. 7 shows four detection pixels a, b, and
The part similar to c and d is 16 pixels of 4 horizontal pixels and 4 vertical pixels.
This is an example in which detection is performed from the range of pixels (1, 2,..., 16). The input of the detection pixel is performed only once in the order of a, b, c, and d, and thereafter the data is used cyclically by setting the switch 57 in FIG. on the other hand,
Reference pixels are 1, 2, 3,..., 15, 1 shown in the upper part of FIG.
Read once in the order of 6. The read reference pixel performs an operation with any of the detected images a, b, c, and d in each operation unit. The difference between the reference image 1 and the detection signal a is calculated in the arithmetic unit 50a. The difference between the reference image 2 and the detection signal b is calculated in the arithmetic unit 50a, and the difference between the reference image 2 and the detection signal a is calculated in the arithmetic unit 50b. Hereinafter, calculations are performed in the order shown in FIG. When the reference signal 6 is read, the unit 50a detects the detected pixels a, b, c, d and the reference pixels 1, 2, 2,.
The calculation with 5, 6 is completed. At this point, the calculation result 55a
Is taken into the comparison circuit 56. Immediately after being taken in, the accumulation addition result of the arithmetic unit 50a is cleared to zero,
The calculation is performed with the pixels 7, 8, 11, and 12 at the next position. Each of the other units also transfers the result to the comparison circuit 56 when the calculation for four pixels is completed, and clears the accumulation and addition result. These timings are shown by thick lines in FIG. When all the reference images have been input, each operation is completed, and the comparison circuit 56 can determine the minimum value. The detection pixel is used cyclically after being once taken into the variable delay circuit 31. Normally, a delay of one clock is selected to transfer data to an adjacent arithmetic unit during one processing clock. However, the rightmost reference pixels 4, 8,.
At the time when the processing of step 12 is completed, the detection pixel and the reference pixel are matched by delaying two clocks. FIG. 8 shows a detailed view of the variable delay circuit 21.
The input image signal 1 is output after being delayed by the delay amount indicated by the signal 22. Usually, there is a large delay of about one frame. The input signal 1 is stored in a memory 201-capable of storing one frame of data by a switch 200.
1 or the memory 201-2. The address to be stored is generated by the address generation circuit 203, and is stored in the switch 207-1 or the switch 207-2.
Is input to the corresponding memory via. At this point, the signal of the previous frame is stored in the other memory. The delay amount input from the outside is added to the address 204 by the adder 205 and input to the memory storing the image of the previous frame. For example, if -1 is input to the signal 22, the variable delay circuit 21 (delay for one frame)
It operates as a -1 clock delay circuit. In this way, a signal corresponding to the delay amount 22 can be obtained as the signal 3. The minimum value of the number of operation units in FIG. 3 can be uniquely obtained from the number of pixels of the detection unit of the delay amount and the detection range of the reference pixel. As shown in FIG. 9, a case where detection is performed from a detection range of reference pixels of horizontal M pixels and vertical N pixels using a horizontal n pixel and a vertical m pixel as a detection unit will be considered. It is assumed that pixels in the detection range are sequentially read out in the horizontal direction.
When the pixels in the calculation cycle range shown in FIG. 9 in the detection range have been read, the accumulation and addition result of the first delay amount candidate (the dotted line in the upper left of FIG. 9) is obtained, and the first arithmetic unit is operated for the new delay amount. Can be used. Thereafter, each time one pixel is read from the reference pixel, one arithmetic unit outputs the result, and the arithmetic operation for the new delay amount can be performed. As described above, if there is an operation unit corresponding to each delay amount in the operation cycle range of FIG. 9, the optimum delay amount can be detected. When the number of horizontal pixels in the detection range is N, the candidate for the delay amount is (N-n + 1). Therefore, there are (N-n + 1) * (m-1) + n delay candidates in the operation cycle range of FIG. . * Indicates integration. Therefore, if the number of operation units is (N−n + 1) * (m−1) + n, processing can be performed. In the examples of FIGS. 3 and 7, n = m = 2.
Since N = M = 4, at least five arithmetic units are required. FIG. 10 shows a modification of FIG. Figures 3 and 7
In the embodiment, the variable delay circuits 30, 31, 32, 33,
In 34 and 35, the amount of delay is changed in the period of (N-n + 1). This is because the ratio of the number of arithmetic units to the number of horizontal pixels in the detection range is not an integer ratio. The modification of FIG. 10 is an example in which the cycle of changing the delay amount and the number of arithmetic units have a relationship of an integer ratio. The minimum number of arithmetic units is (N-
n + 1) * (m-1) + n, (N-n + 1)
In this case, (N−n + 1) * m units may be used in order to obtain an integral multiple of. In the modification of FIG. 11, six arithmetic units are used. By making the number of units an integral multiple of the delay amount change cycle, a two-clock delay circuit is placed at a fixed position of 112 and 115 as shown in FIG.
The circuit scale can be reduced and the control circuit can be simplified. The operation of FIG. 10 is almost the same as that of FIG. As shown in FIG. 11, the processing is performed more regularly than in FIG. 7 and 1
In 1, the reading of the detection pixels a, b, c, and d may be performed prior to the reading of the reference pixel. In this case, the switches 102 and 104 or the signal lines 103 and 105 can be shared by time sharing. FIG. 12 shows a modification of FIG. In FIG. 12, two sets of delay amount determination circuits 20 and variable delay circuits 21 are provided, and noise removal is performed by calculating two images having different delay amounts and an input image. Two signals 3 with different amounts of delay
-1 and 3-2 are added in the adder 90 and are added to the division circuit 9
A new delay signal 3 is produced by converting the signal into two by one.
The new delayed signal 3 is calculated and the noise-removed image signal 9 is obtained as in the case of FIG. The present invention includes a case where the number of images to be added in the adder 90 is three or more, or a case where the addition ratio of the adder 90 is not 1: 1. FIG. 13 shows another modification of the delay amount determining circuit. This is a circuit configuration example when the delay detection unit is one pixel width, that is, m = 1 in FIG. Delay amount determination circuit 20
In order to find the optimum delay amount, some delay amount candidates are determined in advance, and arithmetic units corresponding to each candidate are arranged. For example, when calculating the optimum delay amount from the same position as the position pixel of the detection position and a total of five points in the vertical, horizontal, and
As shown in FIG. 13, it can be realized by five arithmetic units. Assuming that the number of horizontal pixels is h and the number of vertical pixels is v, the delay amount of the delay circuit 120 is d0 = h * (v−1), the delay amount of the delay circuit 121 is d1 = h−1, and so on.
= 1, d4 = h−1, the delay signal 40
Is the position on one line of the previous frame, the delay signal 41 is a position one pixel left, the delay signal 42 is the same position, the delay signal 43 is one pixel right, and the delay signal 44 is one line below. As a result of the comparison, for example, if the accumulation value 55a is the minimum value, h * (v-1) is output as the delay amount 22. Hereinafter, h * v-1 and the accumulation value 55c for the accumulation value 55b. H * v, and h * v + for the accumulated addition value 55d.
1, h * (v + 1) is output for the accumulated addition value 55d. When detecting the amount of delay in units of 4 pixels, clearing is performed before the 4 * p + 1 pixel, where p is an integer, and 4 *
The comparison is performed after the addition of the (p + 4) th pixel. FIG. 14 is a modification of FIG. 9 and is a variable delay circuit corresponding to FIG. Delay amount d5 of delay circuit 60
= D0, delay amount d6 of delay circuit 61 = d1, hereinafter d7 =
By setting d2, d8 = d3, d8 = d4, FIG.
The pixel corresponding to each delay amount of No. 3 can be selected by the selector 80. The delay circuits 60 to 64 can be shared with the delay circuits 120 to 124 of FIG. FIG. 15 is a modification of FIG. The noise correction circuit 6 in FIG. 3 replaces the coefficient circuit 131 and the multiplier 133. The coefficient circuit 131 inputs the minimum signal 55 among the accumulated signals 55a to 55e used in the delay amount determining circuit 20, and outputs a coefficient value 132 according to a predetermined rule. The coefficient value 132 is a multiplier 133
Is multiplied by the difference signal 5, and the same processing is performed as in the case of FIG. When the coefficient value 132 is α, for example, when α = 1, the output value 9 becomes the same as the input value 1, and α =
At 0, the output value 9 is the same value as the delay value 3, and at α = 0.5, the output value 9 is the average of the input value 1 and the delay value 3. FIG. 16 shows an output example of the coefficient circuit 131.
When the difference between the input value 1 and the delay value 3 is small and less than 40, α is 0.5, and when there is a slight difference (40 or more and less than 80), α is
When the difference is 0.75 and the difference is large (80 or more), it is possible to remove noise by setting α to 1. FIG. 17 is a modification of FIG. In the coefficient circuit 131, coefficient values of adjacent detection units (in the example of FIG. 13, 4 pixels × 1 pixel unit) are stored, and these values are reflected in determination of a new coefficient value.
It is possible to prevent the coefficient value from greatly changing in the adjacent region and causing discontinuity near the boundary. In the example of FIG. 16, the value of α is determined from the minimum value 55 of the difference signal of the adjacent area and the value of the current signal 55. For example, the current signal 5
When the value of 5 is 85 and the minimum value of the signal 55 in the adjacent area is 30, α is 1 in the method of FIG. 16, but α is 0.75 in the method of FIG. According to the present invention, after detecting a portion most similar to an input image from a delayed image, an operation with a pixel of the detected portion is performed, thereby obtaining a moving image. Can also be subjected to noise removal.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a conventional noise removal circuit diagram. FIG. 2 is an output characteristic diagram of the noise correction circuit in FIG. FIG. 3 is a noise removal circuit diagram according to the present invention. FIG. 4 is a circuit diagram for determining a delay amount in FIG. 3; FIG. 5 is a block diagram of an arithmetic unit in FIG. 4; FIG. 6 is a detailed diagram of a variable delay circuit in FIG. 4; FIG. 7 is an operation timing chart of FIG. FIG. 8 is a diagram showing a variable delay circuit in FIG. 3; FIG. 9 is an explanatory diagram of a search range and the number of operation units. FIG. 10 is a circuit diagram of a modification of FIG. 4; FIG. 11 is a timing chart of FIG. FIG. 12 is a circuit diagram of a modification of FIG. 3; FIG. 13 is a circuit diagram of a modification of FIG. 4; FIG. 14 is a variable delay circuit diagram in FIG. 3; FIG. 15 is a circuit diagram of a second modification of FIG. 3; 16 is an explanatory diagram of an output example of the coefficient circuit in FIG. FIG. 17 is an explanatory diagram of a modified example of the coefficient circuit of FIG. 16; [Description of Signs] 1 ... input image data, 3 ... delay data, 5 ... difference data, 6 ... noise correction circuit, 7 ... correction signal, 9 ... output image data, 20 ... delay amount determination circuit, 21 ... variable delay circuit ,
22: delay amount, 50: arithmetic unit, 131: coefficient output circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 5/14-5/217 H04N 5/93 H04N 11/04

Claims (1)

(57) Claims: 1. A delay circuit for delaying an input image signal to generate a plurality of delayed image signals having different delay amounts, and a detection unit having a plurality of pixels from the input image signal. An arithmetic unit configured to configure a reference unit having the same pixel arrangement as the detection unit from each of the plurality of delayed image signals, and to select a reference unit similar to the detection unit from the reference unit; Calculation between the unit and the pixel of the above detection unit
And a noise correction circuit for removing noise in the detection unit .