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JP3469593B2 - BiCMOSIC - Google Patents
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JP3469593B2 - BiCMOSIC - Google Patents

BiCMOSIC

Info

Publication number
JP3469593B2
JP3469593B2 JP10037092A JP10037092A JP3469593B2 JP 3469593 B2 JP3469593 B2 JP 3469593B2 JP 10037092 A JP10037092 A JP 10037092A JP 10037092 A JP10037092 A JP 10037092A JP 3469593 B2 JP3469593 B2 JP 3469593B2
Authority
JP
Japan
Prior art keywords
conductivity type
pad
epitaxial growth
growth layer
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP10037092A
Other languages
Japanese (ja)
Other versions
JPH05275628A (en
Inventor
郁夫 吉原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10037092A priority Critical patent/JP3469593B2/en
Publication of JPH05275628A publication Critical patent/JPH05275628A/en
Application granted granted Critical
Publication of JP3469593B2 publication Critical patent/JP3469593B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/981Auxiliary members, e.g. spacers
    • H10W72/983Reinforcing structures, e.g. collars

Landscapes

  • Wire Bonding (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 【0001】 【産業上の利用分野】本発明は、BiCMOSIC、特
に第1導電型半導体基板に形成された第2導電型のエピ
タキシャル成長層に半導体素子が形成されたBiCMO
SICに関する。 【0002】 【背景技術】図2はCMOSICのパッド部分を示す断
面図である。図面において、1はn型半導体基板、2は
p型ウェル、3はフィールド絶縁膜、4はアルミニウム
からなる電極パッド、5はオーバーコート膜、6は該オ
ーバーコート膜5の窓開部、7はコネクトワイヤであ
る。上記p型ウェルはパッド4の下側に位置するように
形成されてクラック10によるショートを防止する機能
を果す。 【0003】即ち、ワイヤボンディング時にワイヤボン
ディングによりパッド4に力が加わるので、フィールド
絶縁膜3にクラック10が入ることがある。そのため、
パッド4と基板1とがそのクラック10を通して短絡さ
れる不良が生じる虞れがある。そこで、パッド4下にp
型ウェル2を設けて、クラック10によりパッド4と短
絡された部分をn型半導体基板1と接合分離するように
したのである。 【0004】 【発明が解決しようとする課題】ところで、BiCMO
SICにおいては、一般にp型半導体基板上にn型エピ
タキシャル成長層を形成するので、このようなBiCM
OSICには、図2に示すパッド下にp型ウェルを設け
るという技術を用いてもクラックによるショートは防止
できなかった。なぜならば、そのp型ウェルとp型半導
体基板とは直接接しているからである。従って、クラッ
クが入ってp型ウェルとパッドとの間のショートした
ら、そのまま不良品となってしまい歩留り低下の原因と
なった。 【0005】尤も、BiCMOSICにおいて、n型エ
ピタキシャル成長層のパッドの下側にある部分のまわり
をリング状のp型ウェルで囲繞してしまうというショー
ト防止法もあり、これによれば、n型エピタキシャル成
長層のパッドの下側にあたる部分を、基板からも、n型
エピタキシャル成長層の他の部分からも接合分離でき
る。しかしながら、このような技術によれば、n型エピ
タキシャル成長層のパッドの下側にある部分のまわりを
リング状のp型ウェルで囲繞しなければならないので、
パッドの近傍に保護ダイオード等の素子を形成できなく
なる。 従って、ICの高集積化が阻まれるという問題があっ
た。 【0006】本発明はこのような問題点を解決すべく為
されたものであり、第1導電型半導体基板に形成された
導電型のエピタキシャル成長層に半導体素子が形成され
たBiCMOSICにおいてICの高集積化を阻むこと
なくパッド下のクラックによるパッド・基板間のショー
ト不良を防止することを目的とする。 【0007】 【課題を解決するための手段】本発明BiCMOSIC
は、第1導電型半導体基板上に、少なくとも一部がコレ
クタを成すバイポーラトランジスタを含む半導体素子を
有する第2導電型エピタキシャル成長層が設けられ、該
第2導電型エピタキシャル成長層を覆うフィールド絶縁
膜上の上記半導体素子が形成されていない部分の上方に
当たるところにパッドを有するBiCMOSICにおい
て、上記第2導電型エピタキシャル成長層のパッド下に
あたる部分に、内部に第1導電型チャンネルMOSトラ
ンジスタを有する第1導電型ウェルと同時に形成された
第1導電型ウェルが設けられ、上記第2導電型エピタキ
シャル成長層のパッド下にあたる部分に形成された上記
第1導電型ウェルと、上記第1導電型半導体基板との間
に、該第1導電型ウェルを上記第2導電型エピタキシャ
ル成長層とで上記第1導電型半導体基板から電気的に分
離する第2導電型埋込層が形成されたことを特徴とす
る。 【0008】 【作用】本発明BiCMOSICによれば、フィールド
絶縁膜のパッド下にあたる部分にクラックが生じたとき
パッドとショートする部分には第1導電型ウェルが形成
されているので、パッドと第2導電型エピタキシャル成
長層との間を接合分離できる。また、第1導電型ウェル
と第1導電型半導体基板との間に第2導電型埋込層が形
成されているので、パッドと第1導電型半導体基板との
間を第2導電型埋込層によって接合分離できる。 しかして、パッド下に生じたクラックによってショート
不良が生じるのを防止することができ、延いては歩留り
の向上を図ることができる。 【0009】 【実施例】以下、本発明BiCMOSICを図示実施例
に従って詳細に説明する。図1は本発明BiCMOSI
Cの一つの実施例を示す断面図である。図面において、
1pはp型半導体基板、8はn型エピタキシャル成長
層、2はn型エピタキシャル成長層8のパッド(4)下
にあたる部分に形成されたp型ウェルである。 【0010】9は該p型ウェル2とp型半導体基板1p
との間に設けられたn型埋込層であり、その間を接合に
よって電気的に分離する。3はフィールド絶縁膜、4は
アルミニウムからなる電極パッド、5はオーバーコート
膜、6はその窓開部、7はコネクトワイヤである。尚、
本BiCMOSICの図2の半導体集積回路(CMOS
IC)と共通する部分には共通する符号を用い、その説
明は省略し、相違する点についてのみ説明した。 【0011】このようなBiCMOSICによれば、n
型エピタキシャル成長層8のパッド4下にあたる部分に
p型ウェル2が形成されているので、ワイヤボンディン
グ時にフィールド絶縁膜3のパッド4下にあたる部分に
クラック10が生じても、p型ウェル2とパッド4との
間がショートするだけで、そのp型ウェル2とn型エピ
タキシャル成長層8との間は接合によって分離される。
従って、パッド4とn型エピタキシャル成長層8との間
のワイヤボンディングによって生じたクラック10によ
るショートを防止することができる。 【0012】そして、p型ウェル2とp型半導体基板1
pとの間にn型埋込層9を設けたので、p型ウェル2と
P型半導体基板1pとを接合分離することができる。従
って、パッド4とp型半導体基板1pとの間のワイヤボ
ンディング時に生じたクラック10によるショートを防
止することができる。 【0013】また、p型ウェルとp型半導体基板1pを
パッド4下に形成することによりワイヤボンディングに
よるパッド4下のクラックによるショート防止すること
ができ、ショート防止をICの高集積化を阻むことなく
行うことができる。また、BiCMOSICの場合、n
型エピタキシャル成長層9をnpnバイポーラトランジ
スタのn型コレクタと同時に形成することができ、ま
た、p型ウェル2はnチャンネルMOSトランジスタが
形成されるp型ウェルと同時に形成することができる。
従って、BiCOMSICの製造工数を増すことなく、
また、高集積化を阻むことなく、ワイヤボンディングに
よってパッド下に生じたクラックによるショートを防止
することができ、延いては歩留り向上を図ることができ
る。 【0014】 【発明の効果】本発明BiCMSICは、第1導電型半
導体基板上に、少なくとも一部がコレクタを成すバイポ
ーラトランジスタを含む半導体素子を有する第2導電型
エピタキシャル成長層が設けられ、該第2導電型エピタ
キシャル成長層を覆うフィールド絶縁膜上の上記半導体
素子が形成されていない部分の上方に当たるところにパ
ッドを有するBiCMOSICにおいて、上記第2導電
型エピタキシャル成長層のパッド下にあたる部分に、内
部に第1導電型チャンネルMOSトランジスタを有する
第1導電型ウェルと同時に形成された第1導電型ウェル
が設けられ、上記第2導電型エピタキシャル成長層のパ
ッド下にあたる部分に形成された上記第1導電型ウェル
と、上記第1導電型半導体基板との間に、該第1導電型
ウェルを上記第2導電型エピタキシャル成長層とで上記
第1導電型半導体基板から電気的に分離する第2導電型
埋込層が形成されたことを特徴とする。本発明BiCM
OSICによれば、フィールド絶縁膜のパッド下にあた
る部分にクラックが生じたときパッドとショートする部
分には第1導電型ウェルが形成されているので、パッド
と第2導電型エピタキシャル成長層との間を接合分離で
きる。また、第1導電型ウェルと第1導電型半導体基板
との間に第2導電型埋込層が形成されているので、パッ
ドと第1導電型半導体基板との間を第2導電型埋込層に
よって接合分離できる。しかして、パッド下に生じたク
ラックによってショート不良が生じるのを防止すること
ができ、延いては歩留りの向上を図ることができる。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BiCMOS IC, and more particularly to a BiCMO in which a semiconductor element is formed on a second conductivity type epitaxial growth layer formed on a first conductivity type semiconductor substrate.
Regarding SIC. 2. Description of the Related Art FIG. 2 is a sectional view showing a pad portion of a CMOS IC. In the drawing, 1 is an n-type semiconductor substrate, 2 is a p-type well, 3 is a field insulating film, 4 is an electrode pad made of aluminum, 5 is an overcoat film, 6 is a window opening of the overcoat film 5, 7 is Connect wire. The p-type well is formed so as to be located below the pad 4, and has a function of preventing a short circuit due to the crack 10. That is, since a force is applied to the pad 4 by wire bonding at the time of wire bonding, a crack 10 may enter the field insulating film 3. for that reason,
There is a possibility that a defect that the pad 4 and the substrate 1 are short-circuited through the crack 10 may occur. Therefore, p under pad 4
The mold well 2 is provided so that the portion short-circuited to the pad 4 by the crack 10 is bonded and separated from the n-type semiconductor substrate 1. [0004] By the way, BiCMO
In the SIC, an n-type epitaxial growth layer is generally formed on a p-type semiconductor substrate.
Even if a technique of providing a p-type well under the pad shown in FIG. 2 in the OSIC was used, a short circuit due to a crack could not be prevented. This is because the p-type well is in direct contact with the p-type semiconductor substrate. Accordingly, if a short circuit occurs between the p-type well and the pad due to a crack, the product becomes a defective product and causes a reduction in yield. However, in the BiCMOS IC, there is also a short-circuit prevention method in which a portion of the n-type epitaxial growth layer below the pad is surrounded by a ring-shaped p-type well. Can be junction-separated from the substrate and other parts of the n-type epitaxial growth layer. However, according to such a technique, a portion of the n-type epitaxial growth layer below the pad must be surrounded by a ring-shaped p-type well.
An element such as a protection diode cannot be formed near the pad. Therefore, there is a problem that high integration of the IC is hindered. SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and has a high integration of IC in a BiCMOS IC in which a semiconductor element is formed on a conductive type epitaxial growth layer formed on a first conductive type semiconductor substrate. It is an object of the present invention to prevent a short circuit between a pad and a substrate due to a crack under a pad without hindering the formation of a circuit. [0007] The present invention BiCMOSIC
Is provided on a first conductivity type semiconductor substrate, a second conductivity type epitaxial growth layer having a semiconductor element including a bipolar transistor at least partially forming a collector, and on a field insulating film covering the second conductivity type epitaxial growth layer. In a BiCMOS IC having a pad above a portion where the semiconductor element is not formed, a first conductivity type well having a first conductivity type channel MOS transistor inside a portion below the pad of the second conductivity type epitaxial growth layer At the same time, a first conductivity type well formed is provided, and between the first conductivity type well formed in a portion under the pad of the second conductivity type epitaxial growth layer and the first conductivity type semiconductor substrate, The first conductivity type well and the second conductivity type epitaxial growth layer are combined with the first conductivity type well. Wherein the second conductive type buried layer for electrically isolating is formed from first conductivity type semiconductor substrate. According to the BiCMOS IC of the present invention, the first conductivity type well is formed in a portion that is short-circuited with the pad when a crack occurs in a portion below the pad of the field insulating film. Junction can be separated from the conductive type epitaxial growth layer. Further, since the second conductivity type buried layer is formed between the first conductivity type well and the first conductivity type semiconductor substrate, the second conductivity type buried layer is provided between the pad and the first conductivity type semiconductor substrate. The layers can be joined and separated. Thus, it is possible to prevent the occurrence of a short circuit due to a crack formed under the pad, and to improve the yield. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a BiCMOS IC of the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 shows the BiCMOSI of the present invention.
It is sectional drawing which shows one Example of C. In the drawing,
1p is a p-type semiconductor substrate, 8 is an n-type epitaxial growth layer, and 2 is a p-type well formed in a portion of the n-type epitaxial growth layer 8 under the pad (4). Reference numeral 9 denotes the p-type well 2 and the p-type semiconductor substrate 1p
And an n-type buried layer provided therebetween, which is electrically separated by bonding. Reference numeral 3 denotes a field insulating film, 4 denotes an electrode pad made of aluminum, 5 denotes an overcoat film, 6 denotes a window opening thereof, and 7 denotes a connect wire. still,
The BiCMOS IC shown in FIG.
The same reference numerals are used for the same parts as in (IC), and the description thereof is omitted, and only different points are described. According to such a BiCMOS IC, n
Since the p-type well 2 is formed in a portion of the field type epitaxial growth layer 8 under the pad 4, even if a crack 10 occurs in the portion of the field insulating film 3 under the pad 4 during wire bonding, the p-type well 2 and the pad 4 Is merely short-circuited, and the p-type well 2 and the n-type epitaxial growth layer 8 are separated by a junction.
Therefore, it is possible to prevent a short circuit caused by a crack 10 caused by wire bonding between the pad 4 and the n-type epitaxial growth layer 8. Then, the p-type well 2 and the p-type semiconductor substrate 1
Since the n-type buried layer 9 is provided between the p-type well 2 and the p-type semiconductor layer 1p, the p-type well 2 and the P-type semiconductor substrate 1p can be separated. Therefore, it is possible to prevent a short circuit due to the crack 10 generated at the time of wire bonding between the pad 4 and the p-type semiconductor substrate 1p. Further, by forming the p-type well and the p-type semiconductor substrate 1p under the pad 4, short-circuiting due to cracks under the pad 4 due to wire bonding can be prevented, which prevents high integration of ICs. Can be done without. In the case of BiCMOS IC, n
The epitaxial growth layer 9 can be formed simultaneously with the n-type collector of the npn bipolar transistor, and the p-type well 2 can be formed simultaneously with the p-type well in which the n-channel MOS transistor is formed.
Therefore, without increasing the manufacturing man-hours of BiCOMSIC,
In addition, a short circuit due to a crack generated under a pad by wire bonding can be prevented without hindering high integration, and the yield can be improved. According to the BiCMSIC of the present invention, a second conductivity type epitaxial growth layer having a semiconductor element including a bipolar transistor at least partially forming a collector is provided on a first conductivity type semiconductor substrate. In a BiCMOS IC having a pad above a portion where the semiconductor element is not formed on the field insulating film covering the conductive type epitaxial growth layer, a portion of the second conductive type epitaxial growth layer below the pad has a first conductive inside. A first conductivity type well formed simultaneously with the first conductivity type well having the type channel MOS transistor, wherein the first conductivity type well is formed in a portion of the second conductivity type epitaxial growth layer under a pad; The first conductivity type wafer is provided between the first conductivity type semiconductor substrate and the first conductivity type semiconductor substrate. A buried layer of a second conductivity type, which electrically separates the semiconductor substrate from the first conductivity type semiconductor substrate with the second conductivity type epitaxial growth layer. BiCM of the present invention
According to the OSIC, the first conductivity type well is formed in a portion that is short-circuited with the pad when a crack occurs in a portion under the pad of the field insulating film, so that a gap between the pad and the second conductivity type epitaxial growth layer is formed. Can be joined and separated. Further, since the second conductivity type buried layer is formed between the first conductivity type well and the first conductivity type semiconductor substrate, the second conductivity type buried layer is provided between the pad and the first conductivity type semiconductor substrate. The layers can be joined and separated. Thus, it is possible to prevent a short circuit from occurring due to a crack generated under the pad, and to improve the yield.

【図面の簡単な説明】 【図1】本発明BiCMOSICの一つの実施例を示す
断面図である。 【図2】CMOSICのパッド部を示すところの背景技
術説明のための断面図である。 【符号の説明】 1p 第1導電型半導体基板 2 第1導電型ウェル 3 フィールド絶縁膜 4 パッド 8 第2導電型エピタキシャル成長層 9 第2導電型埋込層
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing one embodiment of a BiCMOS IC of the present invention. FIG. 2 is a cross-sectional view illustrating a pad portion of a CMOS IC for explaining background art. [Description of Signs] 1p First conductivity type semiconductor substrate 2 First conductivity type well 3 Field insulating film 4 Pad 8 Second conductivity type epitaxial growth layer 9 Second conductivity type buried layer

フロントページの続き (56)参考文献 特開 昭56−8852(JP,A) 特開 昭61−53756(JP,A) 特開 昭63−117466(JP,A) 特開 昭61−274343(JP,A) 特開 平3−273640(JP,A) 実開 昭51−77058(JP,U)Continuation of front page       (56) References JP-A-56-8852 (JP, A)                 JP-A-61-53756 (JP, A)                 JP-A-63-117466 (JP, A)                 JP-A-61-274343 (JP, A)                 JP-A-3-273640 (JP, A)                 Shokai Sho 51-77058 (JP, U)

Claims (1)

(57)【特許請求の範囲】 【請求項1】 第1導電型半導体基板上に、少なくとも
一部がコレクタを成すバイポーラトランジスタを含む半
導体素子を有する第2導電型エピタキシャル成長層が設
けられ、該第2導電型エピタキシャル成長層を覆うフィ
ールド絶縁膜上の上記半導体素子が形成されていない部
分の上方に当たるところにパッドを有するBiCMOS
ICにおいて、 上記第2導電型エピタキシャル成長層のパッド下にあた
る部分に、内部に第1導電型チャンネルMOSトランジ
スタを有する第1導電型ウェルと同時に形成された第1
導電型ウェルが設けられ、上記第2導電型エピタキシャル成長層のパッド下にあた
る部分に形成された上記 第1導電型ウェル上記第1
導電型半導体基板との間に、該第1導電型ウェルを上記
第2導電型エピタキシャル成長層とで上記第1導電型半
導体基板から電気的に分離する第2導電型埋込層が形成
された ことを特徴とするBiCMOSIC
(57) to the Claims 1 first conductivity type semiconductor substrate, at least
A half including a bipolar transistor partly forming a collector
BiCMOS having a second conductivity type epitaxial growth layer having a conductive element and having a pad above a portion of the field insulating film covering the second conductivity type epitaxial growth layer where the semiconductor element is not formed
In the IC , a first conductive type channel MOS transistor is provided inside a portion of the second conductive type epitaxial growth layer below the pad.
First well formed simultaneously with the first conductivity type well having
A conductivity type well is provided, and a well is provided under a pad of the second conductivity type epitaxial growth layer.
And the first conductive well formed on a portion that, the first
A second conductivity type buried layer for electrically separating the first conductivity type well from the first conductivity type semiconductor substrate with the second conductivity type epitaxial growth layer is formed between the first conductivity type well and the second conductivity type epitaxial growth layer; A BiCMOS IC characterized in that :
JP10037092A 1992-03-25 1992-03-25 BiCMOSIC Expired - Lifetime JP3469593B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10037092A JP3469593B2 (en) 1992-03-25 1992-03-25 BiCMOSIC

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10037092A JP3469593B2 (en) 1992-03-25 1992-03-25 BiCMOSIC

Publications (2)

Publication Number Publication Date
JPH05275628A JPH05275628A (en) 1993-10-22
JP3469593B2 true JP3469593B2 (en) 2003-11-25

Family

ID=14272165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10037092A Expired - Lifetime JP3469593B2 (en) 1992-03-25 1992-03-25 BiCMOSIC

Country Status (1)

Country Link
JP (1) JP3469593B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3602745B2 (en) 1999-06-30 2004-12-15 株式会社東芝 Semiconductor device
JP2016062967A (en) 2014-09-16 2016-04-25 株式会社東芝 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH05275628A (en) 1993-10-22

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