JP3469840B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3469840B2 JP3469840B2 JP2000044913A JP2000044913A JP3469840B2 JP 3469840 B2 JP3469840 B2 JP 3469840B2 JP 2000044913 A JP2000044913 A JP 2000044913A JP 2000044913 A JP2000044913 A JP 2000044913A JP 3469840 B2 JP3469840 B2 JP 3469840B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor chip
- semiconductor device
- resin case
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/38—Conductors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Led Device Packages (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は,半導体チップを搭
載した金属ベースを樹脂ケースに収容し,外部端子を導
出して形成される半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device formed by housing a metal base on which a semiconductor chip is mounted in a resin case and leading out external terminals.
【0002】[0002]
【従来の技術】従来の半導体装置の断面図を,図4及び
5に示す。1は金属ベースで,半導体チップ2がその上
面に半田付けによって固着されているが,絶縁層を介し
て固着される場合と,介せずに固着される場合とがあ
る。樹脂ケース枠4に埋め込まれて固着された端子金具
3は,樹脂ケース中央に向けて曲げ,伸延されて第1電
極として形成され,図4に示すように第1電極に半導体
チップ2と配線されるボンディングワイヤ7が固着され
る。図5のように端子金具3が半導体チップ2の上面に
半田8で固着される場合もあったが,この場合,半導体
チップ2の上面高さに半田8の厚みを加えた高さの水平
面と,端子金具3の下面高さが一致するように,端子金
具3が精度良く樹脂ケース枠4に埋め込まれて形成され
ることが重要であり,もしも,寸法精度が良くないもの
が無理に半導体チップ2上に押し付けられた状態で仕上
がったときは半田8の厚み不足が生じ接続不良を発生す
る。また半田不足で半導体チップ2と端子金具3との隙
間が出来ると隙間腐食が進行して損傷を促進することが
あった。また,図4のボンディングワイヤ7で接続する
場合では,大電流が集中するこの接続部分で異常発熱す
る原因となり,電力用半導体チップ2ではボンディング
ワイヤ7の直径を太くすることになるがこれにも限度が
あった。2. Description of the Related Art Cross-sectional views of a conventional semiconductor device are shown in FIGS. Reference numeral 1 denotes a metal base, and the semiconductor chip 2 is fixed to the upper surface of the semiconductor chip by soldering. There are cases where the semiconductor chip 2 is fixed via an insulating layer and cases where the semiconductor chip 2 is not interposed. The terminal fitting 3 embedded and fixed in the resin case frame 4 is bent and extended toward the center of the resin case to be formed as a first electrode, and is connected to the semiconductor chip 2 on the first electrode as shown in FIG. The bonding wire 7 is fixed. There is a case where the terminal fitting 3 is fixed to the upper surface of the semiconductor chip 2 with the solder 8 as shown in FIG. 5, but in this case, the height of the upper surface of the semiconductor chip 2 plus the thickness of the solder 8 is a horizontal plane. It is important that the terminal fittings 3 are accurately formed by being embedded in the resin case frame 4 so that the lower surface heights of the terminal fittings 3 are the same. When finished in a state in which the solder 8 is pressed onto the solder 2, insufficient thickness of the solder 8 occurs and a connection failure occurs. Further, if a gap is formed between the semiconductor chip 2 and the terminal fitting 3 due to lack of solder, crevice corrosion may proceed to promote damage. Further, in the case of connecting with the bonding wire 7 of FIG. 4, it causes abnormal heat generation in this connection portion where a large current is concentrated, and the diameter of the bonding wire 7 is increased in the power semiconductor chip 2, but There was a limit.
【0003】[0003]
【発明が解決しようとする課題】上記のように,半導体
チップの上面に対し寸法精度悪く埋め込まれて伸延され
た端子金具が,半導体チップとの半田付け不良を生じ,
接続不良や隙間腐食のため半導体チップ損傷へと進行す
る原因となっていた。又,電流値の最大限度がボンディ
ングワイヤによる接続可否を決めてしまい,限度を超え
た電流値の通電によってワイヤの発熱やワイヤ接続部で
の発熱のために接続部で断線が生じた。これらに対して
の解決が課題であった。SUMMARY OF THE INVENTION As described above, the terminal fitting extended and embedded in the upper surface of the semiconductor chip with poor dimensional accuracy causes defective soldering with the semiconductor chip.
This was a cause of damage to semiconductor chips due to poor connections and crevice corrosion. In addition, the maximum limit of the current value determines whether or not the bonding wire can be connected, and when the current value exceeds the limit, the wire is heated and the wire is heated at the wire connecting part, resulting in disconnection at the connecting part. The solution to these was an issue.
【0004】[0004]
【課題を解決するための手段】上記の課題を解決するた
めに,金属ベースに設けられた半導体チップと,該半導
体チップから配線され導出される端子金具と,該端子金
具を固着する樹脂ケース枠を備えて,金属ベースと樹脂
ケース枠が固着された半導体装置において,上記端子金
具の一端は外部端子として導出され,他端は樹脂ケース
枠の内側に突出して露出し,ボンディングワイヤ接続面
として平板状の第1電極を形成し,該第1電極の先端部
を伸延し半田付け用重ね継手としての,第2電極を形成
し,半導体チップと端子金具との接続に第1電極から配
線するか,第2電極から直接,半田付けするか,1つの
端子金具で2つの工法が選択できるようにした。In order to solve the above-mentioned problems, a semiconductor chip provided on a metal base, a terminal fitting wired and led from the semiconductor chip, and a resin case frame for fixing the terminal fitting. In a semiconductor device in which a metal base and a resin case frame are fixed to each other, one end of the terminal fitting is led out as an external terminal and the other end is projected and exposed inside the resin case frame and is a flat plate as a bonding wire connecting surface. Forming a first electrode in the form of a wire, extending the tip of the first electrode to form a second electrode as a lap joint for soldering, and connecting the semiconductor chip and the terminal fitting from the first electrode , It is possible to solder directly from the second electrode or select two construction methods with one terminal fitting.
【0005】半導体チップの上面に対し,同一の水平面
上に,端子金具の先端が合致して配設されるようにする
ため,請求項2では,埋め込み固着された端子金具が曲
げられた平板状の第1電極の水平面と,半導体チップの
上面の水平面との寸法差を補正するために第1電極に折
り曲げ部分を形成し,段差を設けたり傾斜を設けて第1
電極の先端を伸延し,第2電極を形成している。In order to ensure that the tips of the terminal fittings are arranged on the same horizontal surface with respect to the upper surface of the semiconductor chip, the terminal fittings embedded and fixed are bent in a flat plate shape. In order to correct the dimensional difference between the horizontal plane of the first electrode and the horizontal plane of the upper surface of the semiconductor chip, a bent portion is formed in the first electrode, and a step or an inclination is provided to form a first portion.
The tip of the electrode is extended to form the second electrode.
【0006】請求項3では,第2電極が半導体チップ上
面に精度良く配設されて,半田付けされた理想状態の場
合と,製造バラツキが発生し半田付け面の状態が悪い場
合とを見分ける必要から,第2電極を穴を有する平板と
して,半田付け完了時に余った半田が該穴から上に出て
いるか,不足しているかを見分けることによって製造バ
ラツキに対して品質が管理できるように考慮されてい
る。In the third aspect, it is necessary to distinguish between the ideal state in which the second electrode is accurately arranged on the upper surface of the semiconductor chip and is soldered, and the case in which the manufacturing surface is uneven and the soldering surface is in a bad state. Therefore, by considering the second electrode as a flat plate having a hole, it is possible to control the quality against manufacturing variations by distinguishing whether the surplus solder comes out from the hole or is insufficient at the time of completion of soldering. ing.
【0007】請求項4では,第2電極の形状を櫛形とし
て,上記の半田付けの仕上がり状態を明確に確認できる
ように考慮している。In the fourth aspect, the second electrode is formed in a comb shape so that the finished state of the soldering can be clearly confirmed.
【0008】[0008]
【発明の実施の形態】本発明による第1の実施の形態を
図1によって説明する。1は金属ベースであり半導体チ
ップ2が直接または絶縁層を介して固着されており,端
子金具3に配線されている。樹脂ケース枠4は端子金具
3を埋め込み又は抱き込んで固着し,同時に金属ケース
1に固着されている。該端子金具3の一方の先端部分は
外部端子として導出され,他の先端部分は埋め込まれた
樹脂ケース枠から略直角に折り曲げられ樹脂ケース内へ
突出して半導体チップ2との接続用ボンディングワイヤ
7が固着される平板状の第1電極5を形成し,該第1電
極は先端が伸延され第2電極6が形成されて,半導体チ
ップの上面に半田付け用の重ね継ぎ手として作用する。BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment according to the present invention will be described with reference to FIG. Reference numeral 1 denotes a metal base, to which a semiconductor chip 2 is fixed directly or via an insulating layer, and is wired to a terminal fitting 3. The resin case frame 4 is fixed by embedding or embracing the terminal fitting 3 and at the same time being fixed to the metal case 1. One end portion of the terminal fitting 3 is led out as an external terminal, and the other end portion is bent at a substantially right angle from the embedded resin case frame and protrudes into the resin case to form a bonding wire 7 for connection with the semiconductor chip 2. A fixed plate-shaped first electrode 5 is formed, the tip of the first electrode is extended and the second electrode 6 is formed, and it functions as a lap joint for soldering on the upper surface of the semiconductor chip.
【0009】第1電極5に必要な条件は,樹脂ケース枠
4の内部側面から最短の寸法でボンディングできる位置
以上の突出長さが必要で,ボンディングマシンの治具先
端部が,該樹脂ケース枠4の内壁に当たらずに第1電極
の上面に到達することを条件として,長さ寸法が決定さ
れる。また該治具先端部のボンディング押圧に耐えるよ
うに樹脂ケース枠4の底部水平部を台として,その上に
接して水平に第1電極が配置されることが必要条件であ
る。The condition required for the first electrode 5 is that the protruding length is equal to or larger than the position where bonding can be performed from the inner side surface of the resin case frame 4 with the shortest dimension, and the tip of the jig of the bonding machine is the resin case frame. The length dimension is determined on the condition that the upper surface of the first electrode is reached without hitting the inner wall of No. 4. Further, it is a necessary condition that the bottom horizontal portion of the resin case frame 4 is used as a base and the first electrode is arranged horizontally in contact therewith so as to withstand the bonding pressure of the jig tip portion.
【0010】第2電極6に必要な条件としては,半導体
チップの上面に重ねて,その重なり部分に充分な量の半
田が充満し,半導体チップに押し圧力や引っ張り力など
のストレスを加えない空間位置に保持され,半田付け作
業性を阻害しない寸法や位置範囲内に保持されることで
ある。A necessary condition for the second electrode 6 is a space where the semiconductor chip is overlaid on the upper surface and a sufficient amount of solder is filled in the overlapping portion so that stress such as pushing pressure or pulling force is not applied to the semiconductor chip. It is to be held in a position and within a size and position range that does not hinder soldering workability.
【0011】請求項2に関連して説明すると,第2電極
6は銅板でその代表的な寸法は厚さ1mm,幅18m
m,樹脂ケース枠4の内壁からケース内への突出長さ寸
法が30mmに形成され,該内壁から8mmの位置で段
差又は傾斜を設ける折り曲げ部を形成し,半導体チップ
2の上面の例えばエミッタ電極層より0.2mmだけ高
い水平位置に,該第2電極6の下面が来るように保持
し,半田付け工程に移行し0.2mmの隙間に充満する
ように半田付けされる。Explaining in connection with claim 2, the second electrode 6 is a copper plate, and its typical dimensions are 1 mm in thickness and 18 m in width.
m, a protruding length dimension from the inner wall of the resin case frame 4 to the inside of the case is formed to be 30 mm, and a bent portion for forming a step or an inclination is formed at a position of 8 mm from the inner wall to form, for example, an emitter electrode on the upper surface of the semiconductor chip 2. The lower surface of the second electrode 6 is held at a horizontal position higher by 0.2 mm than the layer so that the lower surface of the second electrode 6 comes to the soldering step, and soldering is performed so as to fill the gap of 0.2 mm.
【0012】第1電極5からアルミ細線で半導体チップ
2の上面の例えばカソード電極層にボンディングされ
る。このように電流値と作業性,品質バラツキを考慮に
入れてワイヤボンディングか重ね継手半田付けか,どち
らかを選択し工法を使い分け出来るように構成されてい
るので,品質が安定し信頼性を向上させることができ,
作業性の向上によって製品不良率が減ったので安価に提
供できるようになった。The first electrode 5 is bonded to the cathode electrode layer, for example, on the upper surface of the semiconductor chip 2 with an aluminum thin wire. In this way, the current value, workability, and quality variations are taken into consideration, and either wire bonding or lap joint soldering can be selected and the construction method can be used differently, so quality is stable and reliability is improved. Can be
The improved workability has reduced the product defect rate and made it possible to provide it at low cost.
【0013】第2の実施形態について図2を用いて説明
する。図2は第2電極6の平面図である。例えば銅板で
厚さ1mm,幅18mm内壁から突出長さ30mmの内
18mm長さ部分に直径1.2mm穴を設けているの
で,これの下面の半田付け後に,該穴から半導体チップ
上面の半田付着量の適否が確認でき,半田付け品質のバ
ラツキを管理することが容易になった。The second embodiment will be described with reference to FIG. FIG. 2 is a plan view of the second electrode 6. For example, a copper plate has a thickness of 1 mm, a width of 18 mm, and a protrusion of 30 mm from a length of 18 mm, and a hole of 1.2 mm in diameter is provided in a portion of the length of 18 mm. The properness of the quantity can be confirmed, and it became easier to manage the variation in soldering quality.
【0014】第3の実施形態について図3を用いて説明
する。図3は第2電極の平面図で,平板状の金属板に櫛
形の切り込み部を形成し,半導体チップ上面に半田付け
される。半田付けの仕上がり状態が一層明確に点検でき
るようになった。A third embodiment will be described with reference to FIG. FIG. 3 is a plan view of the second electrode, in which a comb-shaped cut portion is formed in a flat metal plate and soldered to the upper surface of the semiconductor chip. It is now possible to more clearly check the finished state of soldering.
【0015】[0015]
【発明の効果】本発明によれば,第1電極と第2電極を
同一の端子金具に形成し,第1電極にはワイヤボンディ
ング工法を,第2電極には半田付け工法を用いて,それ
ぞれの半導体チップ上面の形状,寸法にあわせて選択し
た工法を使い分けできる構成にしたので,作業性が,よ
り有利な工法を用いることによって,品質のバラツキ,
断線など信頼性の低下が改善された。例えば電流ランク
によって寸法別に5シリーズの端子金具を製作する場
合,従来の各2通りで10種類の寸法の金具を作るため
に必要とした金型が5種類に集約できたので,金型に要
する資材を半減できて,製品を安価に提供することが可
能となり工業的価値が大きい。According to the present invention, the first electrode and the second electrode are formed on the same terminal fitting, the wire bonding method is used for the first electrode, and the soldering method is used for the second electrode. Since the construction method selected according to the shape and dimensions of the upper surface of the semiconductor chip can be selectively used, the workability is more advantageous by using the construction method which is more advantageous.
Improved reliability such as disconnection. For example, when manufacturing 5 series terminal fittings by size according to the current rank, the molds required to make 10 kinds of fittings in each of the conventional 2 ways can be integrated into 5 kinds, so it is necessary for the molds. Materials can be halved and products can be provided at low cost, which has great industrial value.
【図1】 本発明による第1の実施形態を示す半導体装
置の構造説明図。FIG. 1 is a structural explanatory view of a semiconductor device showing a first embodiment according to the present invention.
【図2】 本発明による第2の実施形態を示す半導体装
置の要部拡大図。FIG. 2 is an enlarged view of a main part of a semiconductor device showing a second embodiment according to the present invention.
【図3】 本発明による第3の実施形態を示す半導体装
置の要部拡大図。FIG. 3 is an enlarged view of a main part of a semiconductor device showing a third embodiment according to the present invention.
【図4】 従来の半導体装置の構造説明図。FIG. 4 is a structural explanatory view of a conventional semiconductor device.
【図5】 従来の半導体装置の構造説明図。FIG. 5 is a structural explanatory view of a conventional semiconductor device.
1 金属ベース 2 半導体チップ 3 端子金具 4 樹脂ケース枠 5 第1電極 6 第2電極 7 ボンディングワイヤ 8 半田 9 穴 10 櫛状の電極切り込み部 1 metal base 2 semiconductor chips 3 terminal fittings 4 resin case frame 5 First electrode 6 Second electrode 7 Bonding wire 8 solder 9 holes 10 Comb-shaped electrode notch
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平1−255257(JP,A) 特開 平10−56096(JP,A) 特開 昭62−202548(JP,A) 特開2000−183249(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/60,23/48 - 23/50 H01L 25/07,25/18 ─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-1-255257 (JP, A) JP-A-10-56096 (JP, A) JP-A-62-202548 (JP, A) JP-A-2000-183249 (JP, A) (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21 / 60,23 / 48-23/50 H01L 25 / 07,25 / 18
Claims (4)
と,該半導体チップから配線され導出される端子金具
と,該端子金具を固着する樹脂ケース枠を備えて,金属
ベースと樹脂ケース枠が固着された半導体装置におい
て,上記端子金具の一端は外部端子として導出され,他
端は樹脂ケース枠の内側に突出して露出し,ボンディン
グワイヤ接続面として平板状の第1電極を形成し,該第
1電極の先端部を伸延し半田付け用重ね継手としての,
第2電極を形成し,第1電極から配線するか,第2電極
から直接,半田付けするか,半導体チップと端子金具と
の接続に,1つの端子金具で2つの工法が選択できる構
成を特徴とする半導体装置。1. A semiconductor chip provided on a metal base, a terminal fitting wired and led out from the semiconductor chip, and a resin case frame for fixing the terminal fitting, wherein the metal base and the resin case frame are fixed to each other. In the semiconductor device, one end of the terminal fitting is led out as an external terminal, and the other end projects and is exposed inside the resin case frame to form a flat plate-shaped first electrode as a bonding wire connection surface. As a lap joint for soldering by extending the tip of
Features a structure in which a second electrode is formed and wiring is performed from the first electrode, soldering is performed directly from the second electrode, or two construction methods can be selected with one terminal metal fitting for connecting the semiconductor chip and the terminal metal fitting. Semiconductor device.
て伸延し,第1電極と異なる平面上に第2電極を形成し
た,請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the tip of the first electrode is extended by providing a step or an inclination, and the second electrode is formed on a plane different from that of the first electrode.
た,請求項1,請求項2記載の半導体装置。3. The semiconductor device according to claim 1, wherein the shape of the second electrode is a flat plate having a hole.
1,請求項2記載の半導体装置。4. The semiconductor device according to claim 1, wherein the second electrode has a comb shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000044913A JP3469840B2 (en) | 2000-02-22 | 2000-02-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000044913A JP3469840B2 (en) | 2000-02-22 | 2000-02-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001237359A JP2001237359A (en) | 2001-08-31 |
| JP3469840B2 true JP3469840B2 (en) | 2003-11-25 |
Family
ID=18567599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000044913A Expired - Fee Related JP3469840B2 (en) | 2000-02-22 | 2000-02-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3469840B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4453498B2 (en) | 2004-09-22 | 2010-04-21 | 富士電機システムズ株式会社 | Power semiconductor module and manufacturing method thereof |
| JP5239291B2 (en) * | 2007-10-24 | 2013-07-17 | 富士電機株式会社 | Semiconductor device and manufacturing method thereof |
| WO2018180580A1 (en) * | 2017-03-30 | 2018-10-04 | 三菱電機株式会社 | Semiconductor device and power conversion device |
| DE112023006608T5 (en) | 2023-07-03 | 2026-04-23 | Mitsubishi Electric Corporation | Power module and method for manufacturing it, as well as power converter device |
-
2000
- 2000-02-22 JP JP2000044913A patent/JP3469840B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001237359A (en) | 2001-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6805277B1 (en) | Process for soldering electric connector onto circuit board | |
| JP6622491B2 (en) | Current detection device and manufacturing method thereof | |
| JP2705368B2 (en) | Electronic equipment | |
| EP2816599B1 (en) | Power semiconductor device | |
| EP2782431B1 (en) | Manufacturing method of semicondictor device and mounting jig | |
| JP5098440B2 (en) | Method for manufacturing power semiconductor device | |
| US20110162204A1 (en) | Integrated device | |
| JP2001077232A (en) | Semiconductor device and method of manufacturing the same | |
| CN101877339A (en) | Lead frame | |
| JPWO2020208741A1 (en) | Semiconductor devices and lead frame materials | |
| US6372998B1 (en) | Electrical component connecting structure of wiring board | |
| JPH1168035A (en) | Power semiconductor module | |
| JP2765278B2 (en) | Electronic device manufacturing method | |
| JP3469840B2 (en) | Semiconductor device | |
| US10586773B2 (en) | Semiconductor device | |
| JP4431756B2 (en) | Resin-sealed semiconductor device | |
| JP2002026195A (en) | Resin-sealed semiconductor device and manufacturing method thereof | |
| CN114944375B (en) | Power device packaging structure and preparation method thereof | |
| US7439625B2 (en) | Circuit board | |
| JP5176557B2 (en) | Electrode pattern and wire bonding method | |
| JP2768056B2 (en) | Electronic equipment | |
| JP3381447B2 (en) | Semiconductor device | |
| JP2765277B2 (en) | Electronic equipment | |
| JP2002359336A (en) | Semiconductor device | |
| JP4020479B2 (en) | Resin-sealed capacitor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| TRDD | Decision of grant or rejection written | ||
| R150 | Certificate of patent or registration of utility model |
Ref document number: 3469840 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080905 Year of fee payment: 5 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080905 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090905 Year of fee payment: 6 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090905 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100905 Year of fee payment: 7 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100905 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110905 Year of fee payment: 8 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120905 Year of fee payment: 9 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130905 Year of fee payment: 10 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |