JP3471978B2 - Electronic component, electronic component manufacturing substrate, and electronic component manufacturing method - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an electronic component having a form in which an element is mounted on a substrate on which external connection terminals are formed, a substrate for manufacturing the same, and a manufacturing method thereof.

[0002]

^2. Description of the Related Art For example, an E ² PROM chip may be mounted on a substrate as a simple information storage device. Generally, an E ² PROM chip includes a ground (GND) terminal pad, a logic power supply (V _DD ) terminal pad, a clock signal (CLK) terminal pad,
Data in / out (D _{IN, OUT} ) terminal pads, a plurality of address (A ₀ , A ₁ ) terminal pads, and a test (T
EST) terminal pads are provided. However,
For simplification as a device, the number of external connection terminals provided on the substrate may be reduced instead of guiding all the wirings that are electrically connected to all the terminal pads to the external connection terminals of the substrate.

For example, as shown in FIG. 10, address (A ₀ , A ₁ ) terminal pads and ground (GND) are provided.
In some cases, the wirings that are electrically connected to the respective terminal pads are connected to the same external connection terminal for use. In the example shown in FIG. 10, the wiring that conducts to the test (TEST) terminal pad is also commonly connected to the external connection terminal for ground. In this case, the storage address of the input data can be defined by the command inserted at the beginning or in the middle of the data string and the data following the command.

Conventionally, when the terminal pads of the element chips mounted on the substrate are commonly connected to the external connection terminals as described above, as shown in FIG. 10, the common connection portion is formed on the wiring pattern provided on the substrate. Was only provided.

[0005]

Then, in the process of manufacturing the above information storage device, the chips mounted on each substrate, that is, E ² PR in the example shown in FIG.
It has been difficult to easily check whether the OM chip functions normally. That is, in the example shown in FIG. 10, since two address terminals (A ₀ , A ₁ ) are commonly connected to the ground terminal (CND), it is difficult to easily perform a function check via the address terminals. there were.

The present invention has been devised under the circumstances as described above, and in the case where some of the terminal pads on the element are commonly connected on the substrate to form an electronic component. Even if there is, the task is to properly check the function of the element in the process of manufacturing the electronic component.

[0007]

DISCLOSURE OF THE INVENTION In order to solve the above problems, the present invention takes the following technical means.

That is, an electronic component provided by the first aspect of the present invention is a substrate, an element mounted on one side of the substrate and having a plurality of terminal pads, and a pattern formed on the one side of the substrate. And a plurality of wirings that are electrically connected to the respective terminal pads of the device, wherein a plurality of wirings to be commonly connected among wirings to be externally connected to an appropriate portion on the one surface side of the substrate. A plurality of auxiliary pads for common connection, which are electrically connected to each other, are arranged close to each other, and an inspection pad electrically connected to a selected one of the plurality of wiring lines to be commonly connected is the other surface of the substrate. Of the wiring to be externally connected, which is arranged on the side, and the external connection terminals that are respectively conductive to wirings other than the wiring to be commonly connected, and the wiring to be commonly connected. And external connection terminals which are conductive in at least one Chino is characterized in that provided on the other surface of the substrate.

In a preferred embodiment, the device is
Ground (GND) terminal pad and logic power supply (V
_DD ) terminal pad, clock signal (CLK) terminal pad, data in / out (D _{IN, OUT} ) terminal pad, a plurality of address (A ₀ , A ₁ ) terminal pads, and a test (TEST A plurality of wirings to be commonly connected among the wirings to be externally connected are wirings for ground (GND),
Also, among the wirings for a plurality of addresses (A ₀ , A ₁ ), wirings other than the wirings to be commonly connected among the wirings to be externally connected, the wiring for logic power supply (V _DD ) and the clock signal (CLK ) Wiring and data in / out (D _{IN, OUT} ) wiring.

With respect to the preferred embodiment described above, the logic
Power supply (V_DD) Wiring and for clock signal (CLK)
Wiring and data in / out (D_{IN, OUT}) Wiring is
Each reaches the corresponding external connection terminal independently. one
, Multiple addresses (A₀, A ₁) Wiring and ground
The wiring for the GND (GND) should be placed close to each other.
A common connection auxiliary pad is formed. The above
Address (A₀, A₁) Wiring for inspection.
The pad is formed. Then, the distribution for the ground (GND)
The wire leads to the external connection terminal. Test (TES
For the wiring for T), for example, an inspection pad is formed.
Be done.

Then, in the case of the preferred embodiment described above,
The external connection terminals provided on the board are ground (GN
D) terminal, logic power supply (V _DD ) terminal, clock signal (CLK) terminal, data in / out (D
There are only 4 terminals, terminals for _{IN, OUT} ). On the other hand, since a plurality of address (A ₀ , A ₁ ) wirings are provided with inspection pads respectively, and test (TEST) wirings are also provided with inspection pads, the above four external connection wirings are used. Using the terminals and each test pad, the above E ² PROM
The inspection through all of the terminal pads can be properly performed.

The plurality of addresses (A ₀ ,
The wiring for A ₁ ) is finally commonly connected to the wiring for ground (GND), but the operation is performed on the auxiliary pad for common connection provided close to each other for the address wiring and the ground wiring. It is only necessary to apply a conductive material such as solder to.

According to a second aspect of the present invention, there is provided a substrate for manufacturing an electronic component, which comprises a plurality of unit electronic components having the structure of the second aspect connected through a bridging portion. is there.

By doing so, it is possible to collectively manufacture a plurality of electronic components. In particular, the above-described functional inspection of the elements such as the E ² PROM mounted on each unit substrate and the common connection operation of the wiring on the substrate can be efficiently performed sequentially or collectively.

According to a third aspect of the present invention, there is provided the above-mentioned second aspect.
A method of manufacturing an electronic component using a substrate for manufacturing an electronic component provided by the side surface of the device, the method including: performing an inspection of the device using the external connection terminal and / or the inspection pad. , A step of electrically connecting the auxiliary pads for common connection by a conductive material.

As already mentioned, according to this method,
Even when selected terminal pads of elements are commonly connected to manufacture a simple device, the function check of each element mounted on the substrate can be appropriately and easily performed.

Other features and advantages of the present invention will be apparent from the detailed description given below with reference to the accompanying drawings.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a form on one side of an electronic component manufacturing substrate of the present invention, and FIG. 2 shows a form on the other side. This manufacturing substrate 1 is a unit substrate 1 having a predetermined shape.
0 has a form in which a plurality of 0s are connected through the bridging portion 2, and after forming predetermined wirings, terminals or various pads on one surface side and the other surface side of the substrate material such as glass epoxy, each unit It is obtained by punching a slit 3 for partitioning the substrate 10 while leaving the bridging portion 2. The wiring, terminals or pads can be formed by a method in which a metal conductor layer such as copper is formed on the surface of the substrate material by vapor deposition and then unnecessary portions are removed by etching.

The unit substrate 10 will be focused below. Each unit substrate 10 has a planar shape such that a thin extension 12 extends from a rectangular main body 11. The rectangular main body 11 may have a size necessary and sufficient for mounting an element 15 to be described later, for example, a size of several mm to ten and several mm square.

The external extension 12a of the unit substrate 10 has four external connection terminals 161, 162, 163, 1.
64 is formed. Each terminal 161, 162, 16
3, 164 are through holes 171, 172, 173,
By 174, it is connected to a predetermined wiring pattern-formed on the other surface side of the substrate. The thickness of the metal conductor layer forming the terminal is, for example, 20 to 30 μm. Furthermore, three inspection pads 181, 182, 183 are formed in the vicinity of the upper side of the rectangular main body 11 of the unit board, and the wiring 1 connected to each inspection pad 181, 182, 183 is formed.
81a, 182a, 183a are through holes 191,
192 and 193 connect to predetermined wirings 26e, 26f and 26g which are patterned on the other surface side of the substrate. In this embodiment, the rectangular main body 1 of the unit substrate 10 is used.
The external connection terminals 161 to 16 are provided at the central portion on the one surface side of 1.
4 and the test pads 181, 182, 183 are formed at the same time, and a rectangular discard pattern 20 of a metal conductor layer is formed. Then, the one surface side of the unit substrate 10 has the external connection terminals 161, 162, 163.
The insulating layer 21 such as a green resist is covered, leaving 164 and the inspection pads 181, 182 and 183.
As a result, as shown in FIG. 5, a bulging portion 22 corresponding to the thickness of the conductor layer is formed in the central portion of the rectangular main body portion 11 on the one surface side of the unit substrate 10.

On the other hand, as shown in FIG. 2, predetermined wirings 26a to 26g or pads 25a to 25g, 27a, 27e and 27f are patterned on the other surface of the unit substrate 10, that is, the substrate material. It is formed by a method of removing an unnecessary portion of the metal conductor layer formed on the substrate by etching. As shown in FIG. 2, the element mounting region 23 is formed in the central region of the rectangular main body of the unit substrate 10 on the other surface side.
Is set, and the E ² PROM 15a is bonded to this area. Surrounding the element mounting area 23,
Bonding pads 25a, 25b, 25c, 25 for wire bonding with terminal pads on the device
d, 25e, 25f and 25g are formed. E ² PRO
On the upper surface of M, as shown in detail in FIG.
D) terminal pad 24a, logic power supply (V _DD ) terminal pad 24b, clock signal (CLK) terminal pad 24c, data in / out (D _{IN, OUT} ) terminal pad 24d, and two addresses Terminal pads 24e and 24f for (A ₀ , A ₁ ) and terminal pads 24f for test (TEST) are arranged. The bonding pads 25a and 25a are arranged so as to correspond to these terminal pads.
25b, 25c, 25d, 25e, 25f and 25g are arranged on the substrate.

The ground wiring 26a connected to the ground (GND) terminal pad 24a on the device and the corresponding bonding pad 25a on the substrate is routed on the other surface of the substrate to the back surface side of the ground external connection terminal 161. The through-hole 171 is connected to the ground external connection terminal 161. The logic power supply wiring 26b connected to the bonding pad 25b corresponding to the logic power supply (V _DD ) terminal pad 24b is routed to the back surface side of the logic power supply external connection terminal 162 on the other surface of the substrate, and the through hole 172 causes the above. It is connected to the external connection terminal 162 for logic power supply. Clock signal (C
The clock signal wiring 26c connected to the bonding pad 25c corresponding to the LK) terminal pad 24c is also
The other side of the substrate is routed to the back side of the clock signal external connection terminal 163, and is connected to the clock signal external connection terminal 163 through the through hole 173. Furthermore, terminal pad 2 for data in / out (D _{IN, OUT} )
The data wiring 26d connected to the bonding pad 25d corresponding to 4d is also routed on the other surface of the substrate to the back surface side of the data connection terminal 164, and the through hole 174 is formed.
Is connected to the data external connection terminal 164.

On the other hand, a center angle of 120 ° is formed at the other end of the first address wiring 26e connected to the bonding pad 25e on the substrate corresponding to the first address (A ₀ ) terminal pad 24e on the device. The common connection auxiliary pad 27e is provided, and the first address wiring 26 is provided.
The intermediate portion of e is connected to the inspection pad 181 formed on the one surface side of the substrate via the through hole 191 and the wiring 181a.
Have been contacted via. The other end of the second address wiring 26f connected to the bonding pad 25f on the substrate corresponding to the second address (A ₁ ) terminal pad 24f on the element is the other end of the first address wiring 26e. A common connection auxiliary pad 27f having a center angle of 120 ° is provided near the common connection auxiliary pad 27 formed in the above portion, and an intermediate portion of the second address wiring 26f is provided with a through hole. The wiring 1 is connected to the above-described inspection pad 182 formed on the one surface side of the substrate via 192.
82a. Further, the tip end of the branch portion formed in the intermediate portion of the ground wiring 26a has a circular shape as a whole in cooperation with the common connection auxiliary pads 27e and 27f for the first and second address wirings. A common connection auxiliary pad 27a having a central angle of 120 ° is formed so as to form an auxiliary pad group. Furthermore, the test wiring 26g connected to the test (TEST) terminal pad 24g on the element and the bonding pad 25g on the substrate corresponding to the wiring 183a is connected to the inspection pad 183 formed on the one surface side of the substrate through the through hole 193. Have been contacted through.

As a result, on the other surface of the substrate, the ground wiring 26a, the logic power wiring 26b, the clock signal wiring 26c and the data wiring 26d are connected to the external connection terminals 161, 162, 163 on the one surface of the substrate. 164
While being connected to each of the two address wirings 26
e, 26f and the test wiring 26f are connected to the respective test pads 181, 182, 183 on the other surface side of the substrate, and the ground wiring 26a and the two address wirings 26e, 26f are arranged close to each other. Thus, the common connection auxiliary pads 27a, 27e, 27f are formed. On the other surface side of the substrate, the element mounting region 23 and the common connection auxiliary pads 27a, 27e, 2
Except for 7f, it is covered with an insulating layer 29 such as a green resist.

An E ² PROM 15 is used by using the collective substrate 1 in which the above wiring, terminals and pads are formed on each unit substrate.
A procedure for manufacturing a simple information storage device using a will be described.

First, the E ² PROM chip 15a is bonded to the substrate mounting area 23 of each unit substrate, and the terminal pads 24a, 24b, 24c, 24 on this chip are bonded.
Bonding pads 25a, 25b, 25c, 25d and 25 corresponding to d, 24e, 24f and 24g, respectively.
The wires e, 25f and 25g are connected by wire bonding. Then, the chip 15a and the wire bonding portion are covered with a protective layer 28 formed by applying and curing a thermosetting resin. In this state, the collective connection auxiliary pads 27a, 27e, 27f are separated from each other.
Seven terminal pads 24a, 24 formed on the chip
b, 24c, 24d, 24e, 24f, 24g are electrically connected to four external connection terminals 161, 162, 16
3,164 and three inspection pads 181,183,
The measurement can be performed from the one surface side of the substrate by bringing the measurement terminal into contact with 184. Therefore, inspection related to all the terminal pads on the chip can be performed without any problem, and the defective chip can be specified at this point.

Next, a conductive material such as solder is applied onto the common connection auxiliary pads 27a, 27e, and 27f that are collectively arranged, so that the two address wirings 26 are formed.
e, 26f, and by extension, the two address terminal pads 24e, 24f on the chip, can be commonly connected to the ground wiring 26a. In this way, after performing the above-mentioned steps for each unit substrate 10 in the manufacturing substrate 1,
By punching out the bridging portion 2, a unit device as shown in FIGS. 4 and 5 is obtained.

As already mentioned, the existing general E ²
By using the PROM 15a and commonly connecting the address terminal to the ground terminal, a simple information storage element with a reduced number of external connection terminals is realized. In this case, the address for storing the data to be input is determined by the address data specified by the command in the data string.

FIG. 6 shows a state in which the information storage device D having the above configuration is attached to an attachment target. As the object to be attached, for example, the video tape cassette case 30 is selected. In such a cassette case, an internal space is defined by combining the lower member 30a and the upper member 30b, and in addition to the tape reel, functional components are incorporated in the internal space. A slit 31 that is substantially parallel to the outer surface 32 of the cassette case 30 is formed at the edge portion.

As shown in FIGS. 7 and 8, the slit 31 has a first inner wall 311 close to the outer surface 32 of the casing case and parallel to the outer surface of the cassette case.
And a second inner wall 312 facing the first inner wall 311.

The first inner wall 311 of the slit 31 has a flat shape, and an opening window 33 penetrating the cassette case outer surface 32 is cut out in a part thereof.
As will be described later, the first inner wall 311 has the slit 31
When the information storage device D is inserted into the, the bulging portion 22 on the one surface side is supported. Further, the opening window 33 is
External connection terminals 161, 1 of the inserted device D
The 62, 163 and 164 are exposed to the outer surface of the cassette case.

The second inner wall 312 of the slit 31 has a second-side element portion (E ² PROM) of the inserted device D.
A concave portion 312a for accommodating the mounting portion) and the concave portion 312a
On both sides of the device, there are substrate receiving surfaces 312b and 312b for receiving the other ends of the device on the other surface side. The distance L ₁ between the substrate receiving and supporting surface 312b and the first inner wall 311 is set to be slightly smaller than the dimension L ₂ from the other surface of the substrate of the device to the top of the bulging portion 22 in the natural state. To be done.

FIG. 9 shows a state in which the thin plate information storage device D is inserted into the slit 31. As described above, the distance L ₁ between the substrate receiving surface 312b of the second inner wall 312 of the slit 31 and the first inner wall 311 is from the other surface of the substrate of the device D in the natural state to the top of the bulging portion 22. Since it is set to be slightly smaller than the size L _{2 of the} device, the device D inserted in the slit 31 is elastically bent and deformed, and the bulging portion 22 is formed on the first inner wall 311. Both ends of the other surface of the substrate are elastically brought into contact with the substrate receiving surfaces 312b and 312b of the second inner wall 312, respectively. Therefore, due to the frictional resistance generated by such elastic contact, the thin plate-shaped information storage device D inserted in the slit 31 is
It can be held stably without rattling and preventing accidental falling. Then, the work of attaching the thin plate-shaped information storage device D may be simply inserted into the slit 31 and is extremely simple. The end portion opening in the component insertion direction of the slit 31 after the thin plate information storage device is inserted and held in the slit 31 of the lower member 30a of the cassette case as described above is defined by the cassette case 3
It is closed by the upper member 30b of 0.

As a result, an information storage device such as an E ² PROM having a predetermined storage capacity is properly incorporated in an appropriate portion of the video tape cassette case, and a terminal portion used for writing or reading data. Will properly face the selected outer surface of the cassette case.

For example, in a video tape recorder,
As described above, a data writing or reading terminal is provided which can contact the terminals 161, 162, 163, 164 when the video tape cassette is inserted, and, for example, at the start of recording, the above The device element is configured so that index information such as date and title is written together with the tape running counter number. Further, the contents stored in the device element are read out appropriately and displayed on the video screen. In this way, for example, when the digital video tape recorder is used, it becomes extremely easy to search the contents recorded in the digital video tape cassette capable of recording for a long time.

[Brief description of drawings]

FIG. 1 is a partial plan view of one surface side of an aggregate substrate for manufacturing an information storage device which is an example of an electronic component of the present invention.

FIG. 2 is a partial plan view of the other surface side of the collective substrate for manufacturing the information storage device which is an example of the electronic component of the present invention.

FIG. 3 is a layout view of terminal pads on an E ² PROM used for manufacturing an information storage device which is an example of an electronic component of the present invention.

FIG. 4 is a plan view of one side of an information storage device which is an example of the electronic component of the present invention.

5 is a cross-sectional view taken along the line VV of FIG.

FIG. 6 is an external perspective view showing a state in which the information storage device is attached to a video tape cassette as an example of an attachment target.

7 is an explanatory diagram showing a state in which a mounting slit is formed in a lower member of the cassette shown in FIG.

FIG. 8 is a detailed view of the slit.

9 is an explanatory diagram of a state in which the information storage device is inserted and held in the slit shown in FIG.

FIG. 10 is an explanatory diagram of a conventional example.

[Explanation of symbols]

1 Manufacturing Assembly Board 2 Bridge Section 10 Unit Board 15 Element 15a E ² PROM 161 to 164 External Connection Terminals 171 to 174 Through Holes 181 to 183 Inspection Pads 24a to 24g (on Element) Terminal Pads 25a to 25g ( Bonding pads 26a-26g (on board) Wirings 27a, 27e, 27f (on board) Auxiliary pads for common connection

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 23/12 H05K 1/18

Claims (5)

(57) [Claims] 1. A substrate and a substrate mounted on one side of the substrate,
And an element having a plurality of terminal pads, and one surface of the substrate
Patterned on the side, and an electronic component having a plurality of wiring to be caused to conduct to each terminal pad of the device, to an appropriate portion of one side of the substrate, of the wiring to be externally connected, a common connection A plurality of auxiliary pads for common connection, which are respectively connected to a plurality of wirings to be connected, are arranged in close proximity to each other, and an inspection pad that is respectively connected to a selected one of the plurality of wirings to be commonly connected is Of the above substrate
At least one of an external connection terminal which is arranged on the other surface side and which is electrically connected to a wiring other than the wiring to be commonly connected among the wiring to be externally connected and the wiring to be commonly connected. An electronic component, characterized in that an external connection terminal that is electrically connected to one another is provided on the other surface side of the substrate. 2. The device comprises a ground (GND) terminal pad, a logic power supply (V _DD ) terminal pad, a clock signal (CLK) terminal pad, and a data in / out (D _{IN, OUT} ) terminal pad. A memory chip element including a terminal pad, a plurality of address (A ₀ , A ₁ ) terminal pads, and a test (TEST) terminal pad, and a plurality of wirings to be commonly connected among the wirings to be externally connected. Are wirings for ground (GND) and wirings for a plurality of addresses (A ₀ , A ₁ ). Of the wirings to be externally connected, the wirings other than the wirings to be commonly connected are the logic power supply (V _DD ) wiring, clock signal (CLK) wiring, data in / out (D
The electronic component according to claim 1, which is a wiring for ( _{IN, OUT} ). 3. A substrate for manufacturing an electronic component, wherein a plurality of unit electronic components having the structure according to claim 1 or 2 are connected via a bridging portion. 4. A method for manufacturing an electronic component by using the electronic component manufacturing substrate according to claim 3, wherein the element is inspected by using the external connection terminal and / or the inspection pad. After that, a method for manufacturing an electronic component, including a step of electrically connecting the auxiliary pads for common connection with a conductive material. 5. The electronic component according to claim 1, wherein the plurality of auxiliary pads for common connection are electrically connected by a conductive material.