JP3472067B2 - Design support equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CAD (Computer Aided Design) system for supporting hardware design.

[0002]

2. Description of the Related Art In recent years, with the increase in the scale of hardware to be designed such as LSI, CAD for supporting the design from the upper step of design such as functional design for the purpose of improving the design efficiency.
The system is being developed.

As input data of the simulator, a hardware description language (hereinafter referred to as HDL) for hardware design similar to the programming language of software is used in addition to the input by the drawing, and the designer Input drawings or HDL etc. into the simulator and verify the design by simulation.

Among HDL, VHDL and Verilo
g HDL and the like support mixed level simulation. In other words, since it is possible to perform model description with a plurality of description levels and description methods using a single HDL and combine them for verification, it is being used in many designs.

A unit operating in parallel described in the simulation model is called a process. VHDL, Ver
An example of the process described in ilog HDL is shown in FIGS.

The process in the VHDL description (see FIG. 2) is the signal shown in parentheses following the reserved word "process", ie in this case the signals "in1", "i".
It is executed when the value of "n2" changes. Similarly Veri
The process in log HDL (see FIG. 3) is executed when the value of the signal shown in parentheses following the reserved word “always @” changes.

The list of signals shown in parentheses above is called the process sensitivity list, and the signals are called sensitivity signals and drive signals.

In order to support the design from the upper process, the simulator is strongly required to have the ability to simulate a large-scale circuit at high speed.

For this reason, there has been proposed a method of simulating a large-scale circuit by a high-speed method called a cycle-based method instead of simulating it by an event-driven method simulator that has been used conventionally.

The event-driven method is a method in which, if there is a change in the input of an element at a certain time, the logical operation of that element is performed at the next time, and if there is no change, nothing is done.

The event driven method will be described below.

Event-Driven Simulation Step 0: (Initial Process Execution) All processes are operated, signal value update requests are processed, signal substitution reservations are registered, and step 1 is proceeded to.

Step 1: (Cycle update) The simulation cycle is advanced by one cycle. If the substitution reservation is registered in the time wheel in the current cycle, the process proceeds to step 3. If not registered, proceed to step 2.

Step 2: (Time update) The time is advanced by one time. If there is a signal value update request at the current time, the process proceeds to step 4. If it does not exist, the time is advanced to the place where it exists and the process proceeds to step 3.

Step 3: (Signal Substitution) The signal value update at the current time is executed. At this time, the process driven by the signal whose value is updated is registered in the time wheel (hereinafter referred to as process execution reservation). Then proceed to step 4.

Step 4: (Process execution) The process reserved for process execution in step 3 is operated, the signal value update request is processed, and the process returns to step 1.

As described above, in the event-driven simulation, the change in the value of the signal (event) is detected and the signal values are sequentially propagated. Is designed to be updated.

On the other hand, in the cycle-based simulation, the process dependence of the simulation model is statically analyzed in advance, and the execution order of the processes is adjusted so that the results match at the clock breaks when the simulation is performed by the event driven system. And evaluate the entire circuit for each clock a predetermined number of times.

The cycle-based method simulation is not used for verifying the timing, but is used for performing verification at high speed focusing on the confirmation of the function. Therefore, the delay described in the substitution reservation description of signals other than the clock signal is often not allowed or ignored.

A signal whose value has changed many times within one clock when simulated by the event driven system shows that the value changes once per clock (or several times in some cases) in the cycle-based simulation. However, it is a constant number of times) and the simulation can be sped up.

However, when the cycle-based method is used, it is difficult to observe the event propagation state in detail because the execution order of the processes and the like is fixed in advance based on the processing dependency of the simulation model. Is.

In addition to the cycle-based method, as a means for accelerating the simulation, in a large-scale circuit, the already-debugged module and the commercially available module part are not in the register transfer level model based on the hardware configuration. Another method is to improve the simulation speed of the entire circuit by using a behavior level model based on the behavior of the target hardware model.

In the case of this method, when it is necessary to debug the module using the behavior level model at the register transfer level while simulating a large scale circuit, the model is transferred from the behavior model to the register transfer level. You have to change to a transfer-level model and start the simulation over.

[0024]

In the cycle-based method, high-speed simulation can be performed, but there is a problem that it is difficult to observe the event propagation state in detail. Therefore, when it is determined that a detailed simulation is required by performing the verification by the cycle-based method, it is necessary to re-execute the detailed but slow simulation such as the event driven method from the beginning. In this case, although it is not necessary to observe the signal in detail until the time when the problem occurs, there is a problem that the verification period is increased because the slow simulation is performed.

Further, in the method of improving the simulation speed of the whole circuit by using a part of the large scale circuit at the behavior level model, the behavior level model is changed during the simulation of a certain large scale circuit. If the module used is required to be debugged at the register transfer level, the model has to be changed from the behavior model to the register transfer level model and the simulation has to be restarted from the beginning.

In view of this, the present invention is particularly directed to a design support method and a design support apparatus using the same, which can smoothly switch from a simple simulation to a detailed simulation and can easily perform simulation at a verification level at high speed. The purpose is to provide.

[0027]

The design support method of the present invention obtains the level of detail of each of at least two hardware models, and when the switching times of these models are designated, the designated switching is performed. By switching the model and verifying the operation of the hardware at the switching time determined based on the time and the level of detail, in particular, a simple simulation can be smoothly switched to a detailed simulation, and the level of verification can be improved. The simulation that suits you can be done easily and at high speed.

Further, the design support method of the present invention acquires the level of detail of each simulator for verifying the operation of at least two hardware, and when the switching time of these simulators is designated, the designated switching is performed. By switching the simulator and verifying the operation of the hardware at the switching time determined based on the time and the level of detail, in particular, switching from a simple simulation to a detailed simulation can be smoothly performed, and the level of verification can be improved. The simulation that suits you can be done easily and at high speed.

Further, the design support method of the present invention obtains the level of detail of each of at least two hardware models, and when the first switching time of these models is designated, this first switching time is set. To the second switching time advanced by the time determined based on the detail level, the operation of the hardware is verified by the model with the coarser level of detail, and the operation with the finer level of detail is performed at the second switch time. By switching to the model and verifying the operation of the hardware, in particular, the switching from the simple simulation to the detailed simulation can be smoothly performed, and the simulation suitable for the verification level can be performed easily and at high speed.

Further, the design support method of the present invention acquires the level of detail of each of the simulators for verifying the operation of at least two hardware, and the first of these simulators is used.
When the switching time of is specified, the operation of the hardware is performed by the simulator with the coarser level of detail from the first switching time to the second switching time advanced by the time determined based on the level of detail. By verifying and switching to a simulator with a finer level of detail at the second switching time to verify the operation of the hardware, in particular, a smooth simulation can be smoothly switched to a detailed simulation, and the verification can be performed smoothly. Simulation suitable for the level can be performed easily and at high speed.

The design support apparatus of the present invention includes a model designating unit for designating at least two hardware models, a detail level acquiring unit for acquiring the level of detail of the model specified by the model designating unit, and the model designating unit. A time designation means for designating a switching time of the model designated by the means, and a switching time designated by the time designating means and a switching time determined based on the detail level of the model acquired by the detail level acquiring means. By including the verification means for switching the model and verifying the operation of the hardware, particularly, it is possible to smoothly switch from the simple simulation to the detailed simulation and facilitate the simulation suitable for the verification level. Moreover, it can be done at high speed.

Further, the design support apparatus of the present invention acquires simulator detail means for designating at least two simulators for verifying the operation of the hardware and detail level for obtaining the detail level of the simulator designated by the simulator designating means. Means, a time designating means for designating a switching time of the simulator designated by the simulator designating means, a switching time designated by the time designating means, and the detail level of the simulator acquired by the detail level acquiring means. By providing the verification means for verifying the operation of the hardware by switching the simulator at the switching time determined based on the switching time, in particular, the switching from the simple simulation to the detailed simulation can be smoothly performed, and the verification level can be improved. The simulation that suits you can be done easily and at high speed.

The design support apparatus of the present invention further comprises a model designating means for designating at least two hardware models, and a detail level acquiring means for acquiring the level of detail of each model specified by the model designating means. A time designating means for designating a first switching time of the model designated by the model designating means, and a detail level acquired by the detail level acquiring means from the first switching time designated by the time designating means. Based on the model having a coarser degree of detail acquired by the detail degree acquiring means, the operation of the hardware is verified until the second switch time advanced by the time determined based on the detailed change at the second switch time. By providing a verification means for switching to a model with a finer degree and verifying the operation of the hardware, particularly from a simple simulation to a detailed simulation. Switching to be smoothly carried out, simulation for the level of verification can be performed to easily and fast.

Further, the design support apparatus of the present invention includes simulator designating means for designating two simulators for verifying the operation of the hardware, and detail level acquiring means for acquiring the level of detail of the simulators designated by the simulator designating means. And a time designating means for designating a first switching time of the simulator designated by the simulator designating means, and a detail level acquired by the detail level acquiring means from the first switching time designated by the time designating means. Until the second switch time advanced by a time determined based on the above, the operation of the hardware is verified by the simulator with the coarser detail acquired by the detail acquiring means, and at the second switch time, By providing a verification means for verifying the operation of the hardware by switching to a simulator with a finer degree of detail, it is particularly easy. Switching to a detailed simulation from the simulation is carried out smoothly such, simulation for the level of verification can be performed to easily and fast.

Further, the design support apparatus of the present invention uses the simple model of hardware to verify the operation of the hardware and the software that causes the hardware to function, and a detailed verification of the hardware. A second verification means for verifying the operation of the hardware and the software that causes the hardware to function using a simple model, and a switching means for switching to either one of the first and second verification means. With the provision, the simulation suitable for the verification target can be performed easily and at high speed.

The design support apparatus of the present invention further comprises first verification means for verifying the operation of the hardware and the software that causes the hardware to function by using a simulator for simply verifying the operation of the hardware. One of the first and second verifying means for verifying the operation of the hardware and the software for operating the hardware by using a simulator for verifying the operation of the hardware in detail. By including the switching means for switching to, the simulation suitable for the verification target can be performed easily and at high speed.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, as a first embodiment, when verifying the operation of hardware, a plurality of hardwares (for example, 2
The case where the verification model (hardware model) of (1) is switched to perform the simulation will be described.

(1.1) Configuration and Operation FIG. 1 is a diagram schematically showing an example of the configuration of the design support apparatus according to the first embodiment. The first hardware model designation unit 1 and the second hardware model designation unit 1 Hardware designation unit 2, model switching time designation unit 3, time accuracy acquisition unit 4, hardware model storage unit 5, switching time determination unit 6, hardware model switching unit 7,
It is composed of a simulation execution unit 8.

The hardware model storage unit 5 stores a hardware model described as shown in FIGS. 7 and 8, for example.

Description contents of the hardware model shown in FIG. 7 will be described along line numbers.

Line 0-Line 1: The module name is "mo
“Del0”, indicating that the module has neither an input port nor an output port.

Lines 2 to 31: Module "model"
The internal configuration of "0" is shown.

Row 3: Indicates that the signals in module "model0" are "CLK", "A", "B", "C", "D".

Row 5 to Row 8: Signal "CLK" is 10 ns
It indicates that it is inverted every time.

Lines 9-16: The process that is invoked when an event occurs on the signal "CLK". Signal "C
When LK is "1", the value of the signal "C" is assigned to the signal "A" and reserved, and when the signal "CLK" is "0", the value obtained by inverting the value of the signal "A" is signal "A". Reserve by assigning to.

Lines 17-24: Two processes "p2" which are activated when an event occurs in the signal "A",
It is a description of "p3", and the process "p2" is a signal "A".
Value is inverted and transferred to signal "B" after 2 ns, and process "p3" transfers the value of signal "A" to signal "D" after 1 ns.

Lines 25 to 30: A description of the process "p4" which is started when an event occurs in at least one of the signals "B" and "D", and includes the signals "B" and "D". Is transferred to the signal "C". Then, at the end of the signal “C”, a transaction (a case where the value changes is called an event, whereas a signal substitution is executed regardless of the change of the value,
This is called a transaction) and the elapsed time since the occurrence of the transaction is output to the file "outf".

Description contents of the hardware model shown in FIG. 8 will be described along line numbers.

Line 0 to Line 1: The module name is "mo
"del1", indicating that the model has neither input nor output ports.

Lines 2 to 29: Module "model
1 ”shows the internal configuration.

Line 3: Indicates that the signals in module "model1" are "CLK", "C".

Row 5 to Row 8: Signal "CLK" is 10 ns
It indicates that it is inverted every time.

Line 9 to Line 24: A description of the process started when an event occurs in the signal "CLK". Indicates that the variables in this process are "A", "B", "D". Also, "F" and "L" for file output
Is defined. The description after "-" is a comment, and 1
"-P1" on line 4 indicates that the parts of lines 13 to 17 correspond to the process p1 of FIG. Below, line 2
The same applies to 0, row 22, and row 24. That is, the signal "C
When LK is "1", the value of the signal "C" is assigned to the variable "A", and when the signal "CLK" is "0", the inverted value of the variable "A" is assigned. Next, the variable "A"
The inversion of the value of is assigned to the variable “B”, and the value of the variable “A” is assigned to the variable “D”. After that, variable “B” and variable “D”
The exclusive OR of is assigned to the signal "C" and reserved. Also, the elapsed time from the last transaction that occurred on the signal “C” is output to the file “outf”.

The description of FIGS. 7 and 8 respectively operates as described above, but at the clock edge, the signal "CL
Focusing on the values of “K” and the signal “C”, the model gives the same result.

These models are stored in the hardware model storage unit 4 of FIG. It should be noted that the description will be made here assuming that two hardware models are stored, but the same can be considered when three or more hardware models are stored.

First hardware model designation unit 1, second
The hardware model designation unit 2 of FIG. 8 designates any of the hardware stored in the hardware model storage unit 5, and here, for example, the first hardware model designation unit 1 uses the vhdl description of FIG. A case where a model is specified and the vhdl description model of FIG. 7 is specified by the second hardware model specification unit 2 will be described as an example. In the following description, the hardware model designated by the first hardware model designation unit 1 is the first model, and the hardware model designated by the second hardware model designation unit 2 is the second model. Sometimes called. That is, here, the vhdl description model of FIG. 8 is the first model,
The vhdl description model of FIG. 7 is the second model.

In the model switching time designation unit 3, the user designates the switching time at which the hardware models designated by the first and second hardware models 1 and 2 are switched from one to the other. . Here, it is assumed that the switching time designation unit 3 has designated a time of, for example, “50 ns”.

The time accuracy acquisition unit 4 analyzes the hardware model specified by the first and second hardware model specification units 1 and 2, or by the information added to the hardware model, or The accuracy of each model is acquired by the input by the designer.

The case of analyzing the hardware model to obtain the time accuracy of each model will be described as an example. For example, the signals "CLK" and "CLK" used as the sensitivity signal of each process in the description of FIG. A ",
The reserved reserved statements for "B" and "D" are lines 7, 12, and 1
4, line 19, line 23, line 27, and the time portion of these assignment statements is a delay of delta delay (also called 0 ns: 0 delay), 1 ns, 2 ns, and 10 ns. This delay corresponds to the delay time of the circuit element, for example. Assuming the delta delay is a divisor of all delays, the greatest common divisor of these delays is the delta delay, i.e. 0 ns. If the time precision is defined as the greatest common divisor of the delay in the description, the time precision of the hardware model according to the description of FIG. 7 is delta delay (0 ns).

On the other hand, the signal "CLK" is used as the sensitivity signal of the process in the description of FIG.
Only. Since the time portion of this assignment statement is 10 ns (see line 7), the time accuracy is 10 ns.

Here, the drive signal substitution reservation statement is analyzed for all the processes in the description, and the greatest common divisor of the delay appearing therein is taken as the time accuracy. However, the time accuracy is considered for the signals and processes of interest in the description. It may be decided.

In the switching time determination unit 6, the switching time designation unit 3
The time at which the simulation model is actually switched is determined on the basis of the time specified by and the time accuracy of the two hardware models acquired by the time accuracy acquisition unit 4.

Specifically, a simulation model described in a simple manner (coarse time precision) (for example, simulation model in FIG. 8) to a detailed simulation model (fine time precision) (for example, simulation in FIG. 7). The switching time to the (model) is the coarsest (the one with the largest value) of the time accuracy of the two hardware models acquired by the time accuracy acquisition unit 4 from the time specified by the switching time specifying unit 3. The value that is advanced by the time accuracy is set as the actual switching time.

For example, here, the time designated by the switching time designation unit 3 is 50 ns, the time precision of the hardware model designated by the first hardware model designation unit 1 (see FIG. 8) is 10 ns, and the second precision is 10 ns. Since the time accuracy of the hardware model (see FIG. 7) specified by the hardware model specifying unit 2 is the delta delay, the maximum one of the two time accuracy, that is, the switching time 5 that specifies 10 ns.
Subtract from 0 ns and obtain 40 ns as the actual switching time (see FIG. 4).

Further, a simulation model described in detail (for example, FIG. 8) from a simulation model described in detail (for example, the simulation model in FIG. 7).
As for the switching time to the simulation model), the time specified by the switching time specifying unit 3 is determined as it is as the actual switching time.

The hardware model switching unit 7 switches the two pieces of hardware based on the switching time determined by the switching time determining unit 6 to execute the simulation.
The simulation executing unit 8 is controlled. For example, here, since the switching time determined by the switching time determining unit 6 is 40 ns, the simulation is executed up to 40 ns using the hardware model (see FIG. 8) specified by the first hardware model specifying unit 1. The simulation execution unit 8 is controlled so that the simulation execution unit 8 is controlled from 40 ns so that the simulation is executed by the hardware model (FIG. 7) designated by the second hardware model designation unit 2. (Fig. 4
reference).

The simulation executing unit 8 is designed to verify the operation of the hardware model given under the control of the hardware model switching unit 7.

Next, the hardware model switching unit 7
A method of switching from the model (see FIG. 8) to the second model (see FIG. 7) will be described.

The following methods are available as model switching methods.

The data structure of the second model of the switching destination is analyzed, and the values of the signals and variables stored in the predetermined storage area allocated for executing the simulation of the pre-switching model (first model) are calculated. All are copied to another storage area allocated for the simulation execution of the second model (see FIG. 5). In FIG. 5, the entire first model is re-elaborated (setting of the storage area) and the values are copied, but the completely common parts (signal CLK and signal C) are not elaborated and There is also a method of reusing the data structure part of the No. 1 model (see FIG. 6).

In the following description, the case of FIG. 5 is continued, but the case of FIG. 6 is exactly the same.

At time 40 ns, the hardware model becomes the first
The model (see FIG. 8) is switched to the second model (see FIG. 7), and the simulation execution unit 7 continues the execution as follows according to the description of FIG.

Step S1: The process "p0" is activated, the inversion of the signal "CLK" is substituted and reserved, and updated for one cycle.

Step S2: Since the substitution of Step S1 is executed and an event occurs in the signal "CLK", the process "p1" is started. At this time, the signal "CLK"
Since the value of "1" is "1", the value of the signal "C" (at this time "1") is assigned to the signal "A" and reserved, and one cycle is updated.

Step S3: Since the substitution in step S2 is executed and the event occurs in the signal "A", the processes "p2" and "p3" are activated. Here, 1 ns
The substitution of later transferring the value of signal "A" to signal "D" and transferring the inversion of signal "A" to signal "B" after 2 ns is reserved and updated one cycle. Here, the time is updated by 1 ns to be 41 ns.

Step S4: The substitution reservation of the line 23 in step S3 is executed. As a result, an event occurs in the signal “D”, so that the process “p4” is executed. That is, the process "p4" transfers the exclusive OR of the signals "B" and "D" to the signal "C" after 1 ns. Since the signals "B" and "D" are both "1",
"0" is reserved for substitution. At this time, the time elapsed from the time when the transaction last occurred on the signal “C” is output to the file, but since the time when the first transaction last occurred is 30 ns, the time 11 ns is output. To be done. 1 cycle is updated here, 1
The time of ns is updated to 42 ns. Step S5: Substitution of "0" into the signal "C" in step S4 is executed. At the same time, step S3
The substitution reservation of the line 19 is executed. This causes an event to occur in signal "B", so process "p4"
Is started. Since the signal “B” is “0” and the signal “D” is “1”, the substitution of “1” into the signal “C” is reserved after 1 ns. At this time, 0 ns, which is the elapsed time from the time (32 ns) when the transaction last occurred in the signal “C”, is output to the file. After that, one cycle is updated, the time is updated for 1 ns, and the time becomes 43 ns.

Step S6: The substitution reserved in step S5 is executed, and the signal "C" becomes "1".

Here, the first model (see FIG. 8) is switched to the second model (see FIG. 7) at 40 ns and 0 ns is switched.
15 and 11 show the output waveform and the output file obtained as a result of the simulation from 1 to 70 ns.

Output waveforms and output files obtained as a result of simulating from 0 ns to 70 ns by the simulation model of the second model (see FIG. 7) are shown in FIGS. 14 and 10, and the first model (FIG. 8). 0 ns to 7 depending on the simulation model
Output waveforms and output files obtained as a result of simulation up to 0 ns are shown in FIGS. 13 and 9.

By comparing the output waveforms of FIG. 14 and FIG. 13, the output waveform of FIG. 15 shows that the simulation is performed by the hardware model with the time accuracy of 10 ns up to 40 ns, that is, the first model (see FIG. 8). 40n
s, the detailed simulation model, that is, the second
It can be seen that the model is switched to the model (see FIG. 7).

By comparing the output files of FIG. 10 and FIG. 9, the output file of FIG.
It can be seen that the switching is performed before the designated switching time of 50 ns.

Further, instead of switching the hardware model at 40 ns, the designated switching time is 50 n.
Output waveforms and output files when the model is switched by s are shown in FIGS. 16 and 12, respectively.

In this case, 5 of the output waveforms in FIGS.
When the changes in the signal values in the model after 0 ns are compared, they are in agreement, but when the contents of the output files in FIG. 12 and FIG. 11 are compared, the output results differ at 51 ns. This is because the last transaction, which is the information used in the output part, occurs before the switch.

On the other hand, in FIG. 11, the transaction referred to by 51 ns is generated after 40 ns, and since the model is switched at 40 ns, the mismatch as shown in FIG. 12 does not occur.

Here, the case where the first hardware model designating section 1 and the second hardware model designating section 2 are designated once has been described. However, these are repeatedly used to generate three or more hardware models. It is also possible to sequentially switch and use. For example, with respect to three hardware models A, B, and C, a model switching from A to B is first performed, and then a model switching from B to C is also possible.

Further, as an extension of the present invention, instead of designating two hardware models and the time for switching them, three or more hardware models and the switching time for them are designated, so that three or more hardware models are selected. A usage method of sequentially switching hardware models is also conceivable.

Although the case where the switching time of the simulation model is designated before the start of the simulation has been described as an example, if the designated switching time is earlier than the current time, designation and switching of the simulation model switching time are performed. The designation of the second simulation model, which is the destination, can be designated and used during the simulation.

(1.2) Effects As described above, according to the first embodiment, when a plurality of hardware models having different time precisions are switched to perform a simulation, first, the time precision acquisition unit 4 is used. Analyze the time accuracy of the hardware model to be switched. Then, when switching from the hardware model described in a simplified manner to the hardware model described in detail, the switching time determination unit 6 sets the switching time designated by the user to a plurality (for example, two) of the hardware models. Of the time accuracy, the time advanced by the maximum time accuracy value is determined as the actual hardware model switching time. On the other hand, when switching from the hardware model described in detail to the hardware model briefly described, the switching time designated by the user is directly determined as the switching time of the actual hardware model.

As a result, in the detailed simulation after the switching time designated by the user, the state of transaction reservation can be correctly observed, and switching can be performed without losing the information necessary for detailed debugging.

Therefore, it is possible to freely perform high-speed simulation suitable for the level of hardware verification (detailed verification or simple verification) while switching a plurality of hardware models having different time precisions.

In order to investigate a bug that occurs after long-time execution, the simulation is not executed with a detailed hardware model for a long time, but a high-speed hardware model with low time accuracy is first used. The design time can be shortened by advancing the simulation time, switching to a detailed hardware model when a bug approaches, and executing the simulation.

(Second Embodiment) Next, as a second embodiment, when the operation verification of the hardware is performed, a plurality of (for example, two) simulators having different verification details are switched to perform the simulation. Will be described.

(2.1) It is assumed that, as the configuration and operation simulator, provision is made of an event-driven simulator for simulating up to the delta time in detail and a cycle-based simulator for guaranteeing the result only at clock breaks.

Here, a case will be described as an example where the simulation is performed by switching between the two simulators, but other simulators that can define the execution unit time of the simulator can be used. Also, here, although two simulators that have a fixed correspondence relationship between the delta time and the clock delimiter are used, the time precision in time between the two simulators that use the switching method is not fixed, and an equation or If a table format is obtained, those simulators can also be used.

FIG. 17 is a diagram schematically showing a configuration example of the design support apparatus according to the second embodiment. The first simulator designating section 101, the second simulator designating section 102, and the switching time designating section 103. , Simulator detail level acquisition unit 10
4, switching time determination unit 105, simulator switching unit 10
6, a hardware model storage unit 107, a first simulation execution unit 108, and a second simulation execution unit 109.

The hardware model storage unit 106 stores, for example, a hardware model described as shown in FIG. 7, and the first and second simulation execution units 108 are stored for this hardware model. 10,
The simulation is executed at 9.

The first simulator designating section 101 and the second simulator designating section 102 respectively designate two simulators having different verification details. Here, for example, the cycle-based simulator is specified by the first simulator specifying unit 101,
The case where the event driven simulator is designated by the second simulator designation unit 102 will be described as an example.

In the switching time designation unit 103, the user designates the switching time at which the simulator designated by the first and second simulator designation units 101 and 102 is switched from one to the other. Here, for example, it is assumed that the switching time designation unit 103 has designated a time of “50 ns”.

In the simulator time accuracy acquisition unit 104,
Depending on the information added to the simulator designated by the first and second simulator designating units 101 and 102, or by the analysis result of the simulator and the description,
Alternatively, the time information of each simulator is acquired by the input by the designer.

For example, here, information that the time accuracy is delta delay is added to the event driven simulator, and that the time accuracy of the cycle-based simulator is determined by the clock signal of the hardware description to be simulated. It is assumed that it has been added.

Since the time portion of the assignment statement for updating the signal "CLK" used as the clock signal in the description of FIG. 7 is 10 ns, the time accuracy of the cycle-based simulator is 10 ns in this case.

Here, for simplification, the clock signal is 1
If there are multiple clock signals,
Even when the phases are deviated, the time accuracy is determined by handling the clock signal in the cycle-based simulator. For example, a method of using the greatest common divisor such as the period of those signals or expressing the time accuracy of the cycle-based simulator by an equation can be considered.

In the switching time determining unit 105, similarly to the switching time determining unit 6 in the first embodiment, the switching time specified by the switching time specifying unit 103, for example, 50 ns, is acquired by the simulator time accuracy acquisition unit 104. Based on the maximum (here, 10 ns) of the time precision (0 ns and 10 ns) of the two simulators, the time from the simulator (for example, a cycle-based simulator) with rough time precision (that is, a simple verification level) is used. The actual switching time to a simulator (for example, an event driven simulator) having a fine accuracy (that is, a detailed verification level) is determined.

For example, 5 which is the designated switching time.
It is assumed that 10 ns is subtracted from 0 ns to obtain 40 ns as the actual switching time (see FIG. 18).

As for the switching time from the simulator with fine time accuracy to the simulator with coarse time accuracy, the time designated by the switching time designating section 3 is directly determined as the actual switching time.

The simulator switching unit 106 switches the two simulators based on the switching time determined by the switching time determining unit 105 to execute the simulation, and the first simulation executing unit 108 and the second simulation executing unit 109. Is to control.

First, the simulator designated by the first simulator designating unit 101 (hereinafter sometimes simply referred to as the first simulator), that is, the simulation by the cycle-based simulator is executed by the first simulation executing unit 108. Switching time determination unit 105
At the switching time determined in step 2, the second simulator specifying unit 1
It is assumed that the simulator specified by 02 (hereinafter, may be simply referred to as a second simulator), that is, the simulation by the event driven simulator is executed by the second simulation execution unit 109.

First, a cycle base simulator is executed as a simulator. There are some possible implementation methods for the cycle-based simulator, but here it is assumed that the cycle-based simulator operates as follows. This operation is common as a cycle-based simulator.

The following process is performed every 10 ns when the signal "CLK" is inverted.

1) When the signal "CLK" is "1", the value of the signal "C" is substituted for the signal "A" to obtain the signal "CLK".
Is 0, the inverted value of the signal “A” is substituted for the signal “A”.

2) Substitute the inversion of the value of the signal "A" into the signal "B" and the value of the signal "A" into the signal "D".

3) Reserve the exclusive OR of the signals "B" and "D" for the signal "C".

4) The elapsed time from the last transaction that occurred on the signal "C" is output to the file "outf".

When the switching time 40 ns determined by the switching time determining unit 105 is reached, the simulator switching unit 106
Switching from the first simulator (cycle-based simulator) to the second simulator (event-driven simulator).

The following methods are available as simulator switching methods.

One method is to use a shared memory to refer to the data structure generated by the first simulator by the second simulator. If the data stored in the simulator before and after switching is different, elaboration is additionally performed, and then the value information is copied from the first simulator. Another method is to elaborate the entire simulator after switching and copy the values.

At time 40 ns, the simulator is switched from the cycle-based simulator to the event driven simulator, and the execution is continued as follows according to FIG.

Step T1: The process "p0" is activated, the inversion of the signal "CLK" is reserved for substitution, and is updated for one cycle.

Step T2: Since the substitution of Step T1 is executed and an event occurs in the signal "CLK", the process "p1" is started. At this time, since the value of the signal “CLK” is “1”, the value of the signal “C” (“1” at this time) is assigned to the signal “A” and reserved, and one cycle is updated.

Step T3: Since the substitution of Step T2 is executed and the event occurs in the signal "A", the processes "p2" and "p3" are activated. Here, 1 ns
A substitution is reserved that later transfers the value of signal "A" to signal "D" and after 2ns transfers the inversion of signal "A" to signal "B". Then, one cycle is updated and 1 ns time is updated to 41 ns.

Step T4: The substitution reservation of line 23 of FIG. 7 in step T3 is executed. Since the event occurs at the signal “D”, the process “p4” is executed.
After 1 ns, the exclusive OR of the signals “B” and “D” is transferred to the signal “C”. Since the signals “B” and “D” are both “1”, “0” is reserved for substitution. At this time, the elapsed time from the time when the transaction last occurred in “C” is output to the file. First, since the time when the transaction last occurred is 30 ns, the time 11 ns is output. It One cycle is updated and 1 ns time is updated to 42 ns.

Step T5: Substitution of "0" into the signal "C" in step T4 is executed. At the same time, the substitution reservation of line 19 in FIG. 7 in step T3 is executed. Since the event occurs in the signal “B”, the process “p4” is activated. Since the signal “B” is “0” and the signal “D” is “1”, the substitution of “1” into the signal “C” is reserved after 1 ns. Also, at this time, the signal "C"
The last time a transaction occurred (32ns)
The elapsed time from 0 ns is output to the file. One cycle is updated and 1 ns time is updated to 43 ns.

Step T6: The substitution reserved in step T5 is executed, and the signal "C" becomes "1".

Here, as a result of simulating from 0 ns to 70 ns by switching from the cycle base simulator to the event driven simulator in 40 ns, the output waveform and the output file are shown in FIGS. 15 and 11, respectively.
Indicates.

Also, output waveforms and output files obtained as a result of simulation from 0 ns to 70 ns by the event driven simulator are shown in FIGS. 14 and 10, and output waveforms obtained as a result of simulation from 0 ns to 70 ns by the cycle-based simulator. The output files are shown in FIGS. 13 and 9.

By comparing with FIG. 13 and FIG.
It can be seen that in No. 5, the simulation is executed with time accuracy of 10 ns up to 40 ns, and the event is switched to the detailed event-driven simulator at 40 ns.

Further, by comparing the output files of FIGS. 10 and 9, it can be seen that the output file of FIG. 11 has also been switched up to 40 ns before the specified switching designation of 50 ns.

Furthermore, instead of switching the simulator at 40 ns, the output waveform and the output file obtained as a result of switching the simulator at the designated switching time 50 ns are shown in FIGS. 16 and 12, respectively.

In this case, 5 of the output waveforms in FIGS.
Comparing the changes in the signal values in the model after 0 ns, both are in agreement, but the contents of the output files in FIGS. 12 and 11 show that the output results are different at 51 ns. This is the information used in the output part,
The cause is that the last transaction occurred before switching.

On the other hand, in FIG. 11, the transaction referred to at 51 ns occurs after 40 ns, and since the simulator is switched at 40 ns, the mismatch as shown in FIG. 12 does not occur.

Here, the first simulator designating section 10
The case where the first and second simulator designating sections 102 are designated once has been described, but it is also possible to repeatedly use these to sequentially switch and use three or more simulators. For example, regarding three simulators A, B, and C, a method of switching the simulator from A to B first and then switching the simulator from B to C is also conceivable.

Further, as an extension of the present invention, instead of designating two simulators and a time for switching them, three or more simulators and a time for switching them are designated to sequentially switch the three or more simulators. It can also be used.

In addition, here, the case where the simulator switching time is actually specified before the start of the simulation is taken as an example, but if the switching time to be specified is earlier than the current time, the simulator switching time is specified. The designation of the second simulator of the switching destination can be designated and used during the simulation.

In the first embodiment described above, the method of switching the simulation model and the method of switching the simulator in the second embodiment have been described.
A method of switching the simulation model and the simulator to one by combining these can be easily realized.

(2.2) Effects As described above, according to the second embodiment, when a plurality of simulators having different time precisions are switched to perform a simulation, first, the time precision acquisition unit 104 performs the simulation. Analyze the time accuracy. Then, when switching from a simulator with coarse time accuracy to a simulator with fine time accuracy, the switching time determination unit 105 sets the switching time specified by the user to the maximum time accuracy among the time accuracy of a plurality of (eg, two) simulators. The time advanced by the value of is determined as the actual simulator switching time. On the other hand, when switching from a simulator with fine time accuracy to a simulator with coarse time accuracy, the switching time specified by the user is directly determined as the actual switching time of the simulator.

As a result, in the detailed simulation after the switching time designated by the user, the state of transaction reservation can be correctly observed, and switching can be performed without losing the information necessary for detailed debugging.

Therefore, it is possible to freely perform a simulation at a verification level (detailed verification or simple verification) at high speed by switching a plurality of simulators having different time precisions.

In order to investigate a bug that occurs after long-time execution, a detailed simulator is not executed for a long time, but the simulation time is first advanced by using a high-speed simulator with low time accuracy. The design period can be shortened by switching to the detailed simulation and executing it when approaching.

(Third Embodiment) (3.1) Configuration and Operation Let us consider a case where two hardware models having different degrees of abstraction are switched to perform a simulation as shown in the first embodiment.

FIG. 19 is a diagram schematically showing a configuration example of the design support apparatus according to the third embodiment. The same parts as those in FIG. 1 are designated by the same reference numerals, and different parts will be described. That is, as a result of executing the simulation in the simulation executing unit 8, the values (for example, waveforms) of some signals in the hardware model are sequentially displayed on the waveform display unit 10, and the user's instruction based on the display contents is displayed on the waveform display unit. It is adapted to be input to the first hardware model designation unit 1, the second hardware model designation unit 2, and the model switching time designation unit 3 via the input unit 9 to the.

With such a configuration, when the simulation is executed, the system operation is verified by referring to the values of some signals in the hardware model. At this time, the values of these signals are checked. Is displayed on the waveform display unit 10. FIG. 20 shows an example of the waveform display of the waveform display unit 10.

The user looks at the waveform displayed on the waveform display unit 10 and inputs an input for enlarged display as shown in FIG. 21 to the waveform display unit of FIG. 19 in order to check the detailed signal change. It is assumed that this is done through the input unit 9 of.

The input unit 9 to the waveform display unit is the waveform display unit 1
Under the control of 0, a user (for example, a designer) specifies a desired range with respect to a waveform displayed on the screen of a terminal used by, for example, a mouse or a keyboard.

As a result, the minimum unit of display time is 1
Simultaneously with the change from ns to 0.1 ns, a detailed hardware model is designated as the hardware model switching designation, and the same switching operation as in the first embodiment is performed.

Here, the simple hardware model is switched to the detailed hardware model, but the detailed hardware model is switched to the simple hardware model according to the value of the time scale displayed on the waveform display section 10. You may do it.

In the third embodiment described above, an example of switching hardware models having different temporal abstractions is shown. However, similar to the second embodiment, a hardware simulator having different temporal abstractions is used. Similarly to the above, it is possible to easily realize the switching designation by the input to the input unit 9 of the waveform display unit.

(3.2) Effects As described above, according to the third embodiment, designation of a plurality of simulators having different time precisions or a plurality of simulation models having different time precisions used at the time of switching is displayed as a waveform. By giving an instruction via the input unit 9 to the waveform display unit based on the simulation result (for example, the signal value of the simulation model) displayed on the unit 10, the user, for example, the hardware designer, can easily change the switching time. You can specify.

Therefore, a plurality of simulation models or simulators having different time accuracies can be switched as needed for debugging to improve the design efficiency not only in hardware design but also in simultaneous design of hardware and software. Can be achieved.

(Fourth Embodiment) (4.1) Configuration and Operation Let us consider a case where two hardware models having different degrees of abstraction are switched to perform a simulation as shown in the first embodiment.

FIG. 22 is a diagram schematically showing a configuration example of the design support apparatus according to the fourth embodiment. The same parts as those in FIG. 1 are designated by the same reference numerals, and different parts will be described. That is, in FIG. 22, when the simulation is executed,
A debug target designation unit 12 for designating a module, a block, or the like to be debugged in detail and advancing the verification at any time is provided.

Under the control of the debug target designation section 12, a block diagram of the evaluation target as shown in FIG. 23 is displayed on the screen of the terminal used by the user (for example, the designer),
The user's instruction for this display is input to the first hardware model designation unit 1, the second hardware model designation unit 2, and the model switching time designation unit 3 via the input unit 11 to the debug target designation unit, It is designed to switch the debug target.

The input unit 11 to the debug target designating unit is different from the block diagram shown in FIG. 23 displayed on the screen of the terminal used by the user (for example, the designer) under the control of the debug target designating unit 12. For example, a desired portion is designated with a mouse or a keyboard.

When the microprocessor block M of FIG. 23 is designated by this designation, the hardware model to be evaluated at that time is the first model designated by the first hardware model designation unit 1, and When the simplified hardware model is designated by the second hardware model designation unit 2, the first model is switched to the second model to debug the software.

On the other hand, when ASIC components such as the hardware blocks A and B in FIG. 23 are designated, the hardware model to be evaluated at that time is the first model designated by the first hardware model designation unit 1. When a more detailed hardware model is designated by the second hardware model designating section 2 (second model), the details of the hardware are switched from the first model to the second model. Debugging.

In the fourth embodiment, an example of switching of hardware models having different temporal abstractions is shown, but as in the second embodiment, switching designation of hardware simulators having different temporal abstractions is designated. In the same manner as described above, it may be possible to perform by inputting to the debug target designating unit 12.

As an example of the designation of the debug target, the designation is made on the displayed block diagram.
It is also conceivable to input a model name or block name in characters to the simulator, or to specify a model name or block name button displayed.

(4.2) Effects As described above, according to the fourth embodiment, when a plurality of hardware models having different time precisions are switched and the simulation is performed by coordinating the hardware and software. As a method of specifying the hardware model to be switched, a detailed simulation model is used as a hardware simulation model when hardware debug is specified, and a simple simulation model is used as a hardware simulation model when software debug is specified. The designer who is the user can easily switch the model to be simulated only by recognizing whether the debug target is software or hardware.

This applies not only to switching of simulation models but also to switching of a plurality of simulators having different time precisions.

Therefore, it is possible to remarkably improve the design efficiency in hardware design or simultaneous design of hardware and software by frequently switching a plurality of simulation models or simulators having different time accuracies for debugging as needed. Will be possible.

Each of the units described in the first to fourth embodiments is a program that can be executed by a computer, such as a magnetic disk (floppy disk, hard disk, etc.), optical disk (CD-ROM,
It can also be stored in a recording medium such as a DVD) or a semiconductor memory and distributed.

[0162]

As described above, according to the present invention,
Multiple hardware models (or simulators) with different time accuracy to speed up simulation
When switching and simulating with hardware, hardware with different time accuracy can be determined by determining the actual switching time based on the time specified by the user and the time accuracy (detailedness of verification) of the model (simulator). The model (simulator) can be switched smoothly, and accurate simulation can be performed.

As a result, the simulation suitable for the verification level can be performed easily and at high speed.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a configuration example of a design support device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a description example of a simulation model, which is a description example of a process in VHDL.

FIG. 3 is a diagram showing a description example of a simulation model, which is a description example of a process in Verilog HDL.

FIG. 4 is a diagram for explaining a switching time of a simulation model.

FIG. 5 is a diagram for explaining an example of a delivery method before and after switching of signals or variables when switching simulation models.

FIG. 6 is a diagram for explaining another example of the delivery method before and after switching the signal or variable when switching the simulation model.

FIG. 7 is a diagram showing a VHDL description example (detailed description example) of a simulation model.

FIG. 8 is a diagram showing another VHDL description example (simple description example) of the simulation model.

FIG. 9 is a diagram showing an example of an output file obtained as a result of executing a simulation using a simple simulation model (simulator).

FIG. 10 is a diagram showing an example of an output file obtained as a result of executing a simulation using a detailed simulation model (simulator).

FIG. 11 is a diagram showing an example of an output file obtained as a result of executing a simulation by switching from a simple simulation model (simulator) to a detailed simulation model (simulator) at 40 ns.

FIG. 12 is a diagram showing an example of an output file obtained as a result of executing a simulation by switching from a simple simulation model (simulator) to a detailed simulation model (simulator) at a designated switching time of 50 ns.

FIG. 13 is a diagram showing an example of output waveforms obtained as a result of executing a simulation using a simple simulation model (simulator).

FIG. 14 is a diagram showing an example of output waveforms obtained as a result of performing a simulation using a detailed simulation model (simulator).

FIG. 15 is a diagram showing an example of output waveforms obtained as a result of executing a simulation by switching from a simple simulation model (simulator) to a detailed simulation model (simulator) at 40 ns.

FIG. 16 is a diagram showing an example of output waveforms obtained as a result of executing a simulation by switching from a simple simulation model (simulator) to a detailed simulation model (simulator) at 500 ns.

FIG. 17 is a diagram schematically showing a configuration example of a design support device according to a second embodiment of the present invention.

FIG. 18 is a diagram for explaining a switching time of the simulator.

FIG. 19 is a diagram schematically showing a configuration example of a design support device according to a third embodiment of the present invention.

20 is a diagram showing a waveform display example displayed on the waveform display unit of FIG.

21 is a diagram showing another waveform display example displayed on the waveform display unit of FIG.

FIG. 22 is a diagram schematically showing a configuration example of a design support device according to a fourth embodiment of the present invention.

23 is a diagram showing a display example of a block diagram for designating a debug target in the debug target designating unit of FIG. 22.

[Explanation of symbols]

1 ... First hardware model designation unit 2 ... Second hardware model specification section 3 ... Model switching time designation section 4 ... Time accuracy acquisition unit 5 ... Hardware model storage 6 ... Switching time determination unit 7 ... Hardware model switching unit 8 ... Simulation execution unit 9 ... Input section to waveform display section 10 ... Waveform display section 11 ... Input section to debug target specification section 12 ... Debug target specification section 101 ... First simulator designating section 102 ... second simulator designating section 103 ... Switching time designation unit 104 ... Simulator detail level acquisition unit 105 ... Switching time determination unit 106 ... Simulator switching unit 107 ... Hardware model storage unit 108 ... First simulation execution unit 109 ... Second simulation execution unit

Claims (6)

(57) [Claims] 1. A design support device for verifying operation of hardware at different verification levels, wherein a plurality of models of different hardware are specified as verification targets for verifying operation of the hardware. A model designating unit, a unit for obtaining the greatest common divisor of delay times of circuit elements included in the model as the details of each of the plurality of models representing the difference in the verification level; and a first switching between the verification levels. A time designation unit that designates a switching time, and a second switching time determined based on the first switching time and the detail levels of each of the plurality of models, the model to be verified is switched, and the hardware is changed. A design support device comprising: a verification unit that verifies the operation of the wear. 2. A design support device for verifying operation of hardware at different verification levels, the specification means specifying a plurality of simulators for verifying the operation of the hardware, and the difference between the verification levels. As a level of detail of each of the plurality of simulators, a cycle-based simulator of the plurality of simulators determines the cycle time of the clock signal of the hardware as the level of detail of the simulator, and In the event driven simulator, the means for determining "0" as the detail level of the simulator, the time designating means for designating the first switching time which is the time when the verification level is switched, and the first switching time And the degree of detail of each of the plurality of simulators. In the switching time, the design support apparatus characterized by comprising a verification means for verifying the operation of the hardware by switching the simulator. 3. The verification means includes a first unit having the coarse degree of detail.
When switching between the second model having a small degree of detail and the second model at the second switching time that is advanced from the first switching time by a time determined based on the degree of detail of the first model, The design support device according to claim 1, wherein the design support device is switched from a first model to the second model. 4. The verification means includes the first coarse-grained first detail.
When switching between the first simulator and the second simulator having a finer degree of detail, the first switch is started from the first switching time.
The design support apparatus according to claim 2, wherein the first simulator is switched to the second simulator at the second switching time which is advanced by a time determined based on the detail level of the simulator. 5. A display means for displaying the waveform of the signal verified by the verification means, and a time period designated based on the waveform of the signal displayed by the display means, among the plurality of models. Of the plurality of models, the first verification means for verifying the operation of the hardware by switching to the model with a smaller degree of detail and the time specified based on the waveform of the signal displayed by the display means The design support apparatus according to claim 1, further comprising a second verification unit that verifies an operation of the hardware by switching to a model with a coarser degree of detail. 6. A display unit for displaying a waveform of a signal verified by the verification unit, and a detail of the plurality of simulators within a time designated based on the waveform of the signal displayed by the display unit. First verification means for verifying the operation of the hardware by switching to a simulator with a finer degree, and within the time specified based on the waveform of the signal displayed by the display means, details of the plurality of simulators The design support apparatus according to claim 2, further comprising: a second verification unit that verifies an operation of the hardware by switching to a simulator having a coarser degree.