JP3472090B2 - Recording method on optical disc - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for recording information on an optical disc preformatted in an area in which an auxiliary signal indicating a physical position of a signal track is different from that of the signal track, and in particular, discontinuity on the signal track. The present invention relates to an optical disc recording method and apparatus for recording information at a recording position.

[0002]

2. Description of the Related Art Conventional compact discs (hereinafter referred to as CDs) and digital versatile discs (Digital Ve
An optical disc such as a rsatile disc (hereinafter referred to as "DVD") has signal tracks for recording information formed in a spiral shape or a concentric circle shape. Further, the auxiliary signal is pre-formatted on the optical disc so that the signal tracks can be randomly accessed. This auxiliary signal divides the signal track into unit storage areas of a certain size and indicates the physical positions of these unit storage areas.

The auxiliary signal is pre-formatted on the optical disc by two methods, a hard sector method and a soft sector method. According to the former hard sector method, embossed pits (E
The formation of the mbossed Pit) allows the auxiliary signal to be pre-formatted on the optical disc. In this way, the optical disc with the auxiliary signal pre-formatted (10)
As shown in FIG. 1, a concentric or spiral signal track 12 is divided into sectors 14 having a constant length. Each of these sectors (14) has a sector identification signal section (16).
And a main information signal section (18). The sector identification signal part 16 includes a sync pattern, an address mark, a track number, and a sector number, and is used as an auxiliary signal that indicates the boundary between adjacent sectors and the physical position of the sector. User information is recorded in the main information signal section (18). Since the hard sector type auxiliary signal occupies a part of the signal track on which the user information is recorded, the recording capacity of the optical disc is reduced.

The latter soft sector type auxiliary signal is
The recording area of the optical disk can be increased by arranging it in a wobble area, which is different from the signal track of the optical disk. For an optical disc in which an auxiliary signal is pre-formatted in this soft sector system,
The groove (22) (hereinafter referred to as groove track) formed in a spiral shape or a concentric circle shape from the center to the outer periphery of the optical disc is bent in a constant cycle as shown in, and between the groove tracks (22). A land (20) (hereinafter referred to as a mountain track) is arranged in the area. Auxiliary signal, groove track
(22) Bent parts on both sides (hereinafter referred to as “wobble area”)
The auxiliary signal is pre-formatted.

The user information block recorded on the signal track of the optical disk on which the soft sector type auxiliary signal is preformatted as described above is composed of a user block identification section and a user block information section. The user block identification unit includes a sync pattern, address marks, track numbers, block numbers, etc., as in the hard sector type auxiliary signal. The user block identification unit constructed as described above indicates the physical position of the signal track of the optical disc during reproduction. Therefore, the soft sector type auxiliary signal is mainly used when the user information is recorded on the optical disc.

The auxiliary signal is the transmission speed of user information,
That is, the optical disc is pre-formatted in a form synchronized with a clock signal of a constant cycle in order to express the recording speed and the reproducing speed. In other words, the auxiliary signal pre-formatted on the optical disk contains a clock signal of a constant cycle. The clock signal included in each of the user block identification part and the sector identification signal part of the hard sector system has the same cycle as the bit of the user information, while the clock signal included in the auxiliary signal of the soft sector system is the bit of the user information. It has a relatively large cycle compared to. That is, the reference clock signal included in the soft sector auxiliary signal has a lower frequency than the bit of the user information. by this,
In an optical disk in which a soft sector type auxiliary signal is pre-formatted, the phase of the clock signal recorded on the signal track can change abruptly. When the phase of the clock signal suddenly changes in this way, the optical disc reproducing apparatus reproduces the clock signal having a cycle different from the bit of the user information, so that among the user information blocks recorded on the signal track, etc. Some user information blocks will not be played correctly. Such a phenomenon occurs from a recording position (hereinafter referred to as “discontinuous recording position”) on a signal track of an optical disc where user information is recorded discontinuously in time, and the user information is recorded on the signal track of the optical disc. As the number of information files to be recorded increases, the number of information files will occur more frequently. That is, the discontinuous recording position is recorded when the second information file is recorded from an arbitrary position after an arbitrary time after the first information file is recorded from an arbitrary position in the middle from the start position of the signal track. This occurs when new information is overwritten at an arbitrary position on the recorded signal track.

As shown in FIG. 3, the first user information is recorded in the section (S1) from the left side of the signal track (20 or 22) of the optical disk to the arbitrary point (DCP), and the next arbitrary period elapses. If the second user information is recorded rightward from an arbitrary point (DCP, that is, discontinuous recording position), the phase of the recording clock recorded in the signal track (20 or 22) is as shown in FIG. 4A. Discontinuous recording position (DC
P) makes a sudden change. This is because the recording clock recorded on the signal track (20 or 22) of the optical disc is generated based on the reference clock signal included in the auxiliary signal of the soft sector system. This recording clock has a large cycle during the period of hitting a certain section from the discontinuous recording position (DCP) as shown in FIG. 4B by the optical disk reproducing apparatus, or hits a certain section from the discontinuous recording position (DCP) as shown in FIG. 4C. It is regenerated to have a small cycle during the period. In this way, since the recording clock signal recorded in a certain section from the discontinuous recording position (DCP) on the signal track (20 or 22) is reproduced so as to have a large or small cycle, the user information recorded in that section is reproduced. Will not be played correctly.

In order to prevent such an error in the user information at the discontinuous recording position on the signal track of the optical disc, the variable frequency oscillation (Variable Frequency
requency Oscilating, hereinafter referred to as "VFO") signal "
A method of adding the clock stabilization information is proposed. Since this clock stabilization information is normally recorded over one sector section from the discontinuous recording position, the signal track of the optical disc is unnecessarily consumed. Therefore, the method of adding the clock stabilization information has a disadvantage that the recording capacity of the optical disc is significantly reduced as the number of discontinuous recording positions on the signal track of the optical disc increases.

[0009]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to dispose user information stably and to discontinuously record positions on a signal track of an optical disc so as to increase the recording capacity of the optical disc. An object of the present invention is to provide an optical disc recording method and apparatus capable of recording user information.

[0010]

In order to achieve the above object, an optical disk recording method according to the present invention is directed to an optical disk in which an auxiliary signal for dividing a signal track into unit blocks is preformatted in an area different from the signal track. The method includes recording clock stabilization information in a part of a unit block adjacent to a discontinuous recording position of a signal track, and recording user information in the remaining part of the unit block.

Another optical disk recording method according to the present invention is
The auxiliary sync signal and the auxiliary clock are divided from an optical disk in which the auxiliary signal including the auxiliary sync signal that divides the signal track into unit blocks and the auxiliary clock that indicates the information transmission rate is preformatted in another area different from the signal track. The first step of detecting, the second step of recording the clock stabilizing information in a part of the unit block adjacent to the discontinuous recording position on the signal track by using the auxiliary synchronizing signal and the auxiliary clock, and the auxiliary synchronizing signal and the auxiliary A third step of recording user information in the remaining portion of the unit block adjacent to the discontinuous recording position using a clock is included.

In still another optical disk recording method according to the present invention, an auxiliary signal including an auxiliary sync signal for dividing a signal track into unit blocks and an auxiliary clock for instructing a transmission rate of information is provided in another area different from the signal track. The first step of detecting the auxiliary sync signal and the auxiliary clock from the pre-formatted optical disc, the second step of generating the reference clock based on the detected auxiliary clock, and the detected auxiliary sync signal and the reference clock are used. The third step of recording the clock stabilization information in a part of the unit block adjacent to the discontinuous recording position on the signal track, and the unit block adjacent to the discontinuous recording position using the clock stabilization information and the reference clock. It includes a fourth step of recording user information in the remaining part.

In still another optical disk recording method according to the present invention, an auxiliary sync signal for dividing a signal track into unit blocks and an auxiliary signal including an auxiliary clock for instructing a transmission rate of information are recorded in another area different from the signal track. A first step of detecting an auxiliary clock from a formatted optical disk, a second step of generating a reference clock based on the detected auxiliary clock, a third step of reproducing a synchronization signal recorded on a signal track, and a reproduction The fourth step of recording the clock stabilization information in a part of the unit block adjacent to the discontinuous recording position on the signal track using the synchronized signal and the reference clock, and using the clock stabilization information and the reference clock A fifth step of recording user information in the remaining portion of the unit block adjacent to the discontinuous recording position is included.

In still another optical disc recording method according to the present invention, an auxiliary signal including an auxiliary synchronization signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission rate is provided in a different area from the signal track. A first step of detecting an auxiliary synchronization signal and an auxiliary clock from a pre-formatted optical disc, a second step of generating a reference clock based on the detected auxiliary clock, and a first step of reproducing the synchronization signal recorded on the signal track. 3 steps, 4th step of recording the clock stabilization information in a part of the unit block adjacent to the discontinuous recording position on the signal track using the reproduced synchronization signal, auxiliary synchronization signal and reference clock, and clock stabilization User information is recorded in the remaining part of the unit block adjacent to the discontinuous recording position by using the conversion information and the reference clock. That a fifth stage.

In still another optical disk recording method according to the present invention, an auxiliary signal including an auxiliary synchronization signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission rate is provided in another area different from the signal track. A first step of detecting an auxiliary synchronization signal and an auxiliary clock from a pre-formatted optical disc, a second step of generating a reference clock based on the detected auxiliary clock, and a first step of reproducing the synchronization signal recorded on the signal track. 3 steps, 4th step of recording the clock stabilization information in a part of the unit block adjacent to the discontinuous recording position on the signal track using the reproduced synchronization signal, auxiliary synchronization signal and reference clock, and clock stabilization The fifth step of generating a pseudo sync signal according to the digitized information, and the discontinuous recording position using the pseudo sync signal and the reference clock. The rest of the contact unit blocks including a fifth step of recording the user information.

In still another optical disc recording method according to the present invention, an auxiliary signal including an auxiliary sync signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission rate is provided in another area different from the signal track. A first step of detecting an auxiliary synchronization signal and an auxiliary clock from a pre-formatted optical disc, a second step of generating a reference clock based on the detected auxiliary clock, and a reference synchronization signal based on the detected auxiliary synchronization signal. Third to generate
And a fourth step of reproducing the sync signal recorded on the signal track, and a part of the unit block adjacent to the discontinuous recording position on the signal track by using the reproduced sync signal, auxiliary sync signal and reference clock 5th step of recording clock stabilization information on the 6th step, 6th step of generating a pseudo synchronization signal by the clock stabilization information, and the rest of the unit block adjacent to the discontinuous recording position using the pseudo synchronization signal and the reference clock. 7th step of recording user information in the part of
An eighth step of recording user information in at least one subsequent unit block connected to the unit block adjacent to the discontinuous recording position using the reference synchronization signal and the reference clock.

In the optical disc recording apparatus according to the present invention, the auxiliary signal for dividing the signal track into unit blocks is preformatted in an area different from the signal track, and the unit block adjacent to the discontinuous recording position on the signal track of the optical disc is pre-formatted. First recording means for recording the clock stabilization information in a part and second recording means for recording the user information in the remaining part of the unit block.

Another optical disk recording apparatus according to the present invention is
The auxiliary sync signal and the auxiliary clock are divided from an optical disk in which the auxiliary signal including the auxiliary sync signal that divides the signal track into unit blocks and the auxiliary clock that indicates the information transmission rate is preformatted in another area different from the signal track. A first recording for recording the clock stabilizing information on a part of the unit block adjacent to the discontinuous recording position on the signal track using the auxiliary signal detecting means for detecting and the auxiliary synchronizing signal and the auxiliary clock from the auxiliary signal detecting means. Means and second recording means for recording the user information in the remaining portion of the unit block adjacent to the discontinuous recording position using the auxiliary synchronization signal and the auxiliary clock from the auxiliary signal detecting means.

In still another optical disk recording apparatus according to the present invention, an auxiliary signal including an auxiliary sync signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission rate is provided in another area different from the signal track. Auxiliary signal detecting means for detecting the auxiliary synchronizing signal and the auxiliary clock from the pre-formatted optical disk, reference clock generating means for generating a reference clock based on the auxiliary clock from the auxiliary signal detecting means, and auxiliary from the auxiliary signal detecting means. From the first recording means, the clock stabilizing information is recorded on a part of the unit block adjacent to the discontinuous recording position on the signal track by using the synchronizing signal and the reference clock from the reference clock generating means. Discontinuous recording position using the clock stabilization information and the reference clock from the reference clock generation means. A second recording means for recording the user information to the rest of the adjacent unit blocks.

In still another optical disk recording apparatus according to the present invention, an auxiliary signal including an auxiliary synchronization signal for dividing a signal track into unit blocks and an auxiliary clock for indicating a data transmission rate is provided in another area different from the signal track. Auxiliary signal detecting means for detecting an auxiliary clock from the pre-formatted optical disk, reference clock generating means for generating a reference clock based on the auxiliary clock from the auxiliary signal detecting means, and reproducing the synchronization signal recorded on the signal track. Recording means for reproducing clock stabilization information in a part of a unit block adjacent to a discontinuous recording position on a signal track by utilizing a reproducing means, a reproduced synchronizing signal from the reproducing means and a reference clock from a reference clock generating means. 1 recording means, clock stabilization information from the 1st recording means and reference clock generating means The rest of the unit block adjacent to the discontinuous recording position using the reference clock comprises a second recording means for recording the user information.

In still another optical disk recording apparatus according to the present invention, an auxiliary signal including an auxiliary sync signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission rate is provided in another area different from the signal track. Auxiliary signal detection means for detecting an auxiliary synchronization signal and an auxiliary clock from a pre-formatted optical disk, reference clock generation means for generating a reference clock based on the auxiliary clock from the auxiliary signal detection means, and synchronization recorded on a signal track. The reproducing means for reproducing the signal, the reproduced synchronizing signal from the reproducing means, the auxiliary signal from the auxiliary signal detecting means and the reference clock from the reference clock generating means are used to be adjacent to the discontinuous recording position on the signal track. First recording means for recording clock stabilization information in a part of the unit block;
A second recording unit is provided for recording the user information in the remaining portion of the unit block adjacent to the discontinuous recording position by using the clock stabilization information from the first recording unit and the reference clock from the reference clock generating unit.

In still another optical disk recording apparatus according to the present invention, an auxiliary signal including an auxiliary sync signal for dividing a signal track into unit blocks and an auxiliary clock for indicating a data transmission rate is provided in another area different from the signal track. Auxiliary signal detection means for detecting an auxiliary synchronization signal and an auxiliary clock from a pre-formatted optical disk, reference clock generation means for generating a reference clock based on the auxiliary clock from the auxiliary signal detection means, and synchronization recorded on a signal track. Adjacent to the discontinuous recording position on the signal track using the reproducing means for reproducing the signal, the auxiliary synchronizing signal from the auxiliary signal detecting means, the reproduced synchronizing signal from the reproducing means and the reference clock from the reference clock generating means. Recording means for recording clock stabilization information in a part of the formed unit block, and first recording means Pseudo sync generation means for generating a pseudo sync signal based on the clock stabilization information, and a unit block adjacent to the discontinuous recording position by using the pseudo sync signal from the pseudo sync generation means and the reference clock from the reference clock generation means. Second recording means for recording the user information in the remaining part of the.

In the optical disc recording apparatus according to the present invention, an auxiliary signal including an auxiliary synchronization signal for dividing a signal track into unit blocks and an auxiliary clock for indicating an information transmission rate is pre-formatted in another area different from the signal track. Auxiliary signal detecting means for detecting an auxiliary synchronizing signal and an auxiliary clock from the optical disc, a reference clock generating means for generating a reference clock based on the auxiliary clock from the auxiliary signal detecting means, and an auxiliary clock from the auxiliary signal detecting means. A reference synchronization generating means for generating a reference synchronization signal based on the reproducing means, a reproducing means for reproducing the synchronizing signal recorded on the signal track, an auxiliary synchronizing signal from the auxiliary signal detecting means, a reproduced synchronizing signal from the reproducing means and a reference. Using the reference clock from the clock generation means, it is adjacent to the discontinuous recording position on the signal track. First recording means for recording clock stabilization information in a part of the unit block, pseudo-synchronization generation means for generating a pseudo-synchronization signal according to the clock stabilization information from the first recording means, and pseudo-synchronization signal from the pseudo-synchronization generation means. Second recording means for recording user information in the remaining portion of the unit block adjacent to the discontinuous recording position by using the reference clock from the reference clock generating means, and the reference synchronization signal and the reference clock from the reference synchronization generating means. A third recording unit is provided for recording the user information in at least one subsequent unit block connected to the unit block adjacent to the discontinuous recording position by using the reference clock from the generating unit.

[0024]

According to the present invention, according to the present invention, the clock stabilizing information is user information in the block section adjacent to the discontinuous recording position on the signal track of the optical disc in which the auxiliary signal is preformatted in a different area from the signal track. Recorded with. As a result, the user information recorded in the block section adjacent to the discontinuous recording position on the signal track can be reproduced stably, and the recording capacity of the optical disk becomes large. In the present invention, a blank section is selectively generated between the clock stabilization information and the discontinuous recording position on the signal track of the optical disc due to the phase relationship between the reproduction synchronization signal and the auxiliary synchronization signal included in the auxiliary signal. To be done. As a result, the clock stabilization information is recorded in the block section adjacent to the discontinuous recording position so as to be synchronized with the reproduction synchronization signal. Also, the present invention keeps the recording capacity of the optical disk constant by recording information on the optical disk only when the reference clock is synchronized with the auxiliary clock included in the auxiliary signal, and minimizes the occurrence of errors. Turn into.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. FIG. 5 illustrates an optical disc recording device according to an embodiment of the present invention. In FIG. 5, the optical disk recording apparatus includes a spindle motor (26) for rotating the optical disk (24), a servo section (30) connected to the optical pickup (28), and a motor drive section connected to the spindle motor (26). Can be said with (32). The optical pickup (28) irradiates the main track (22) of the groove of the optical disk (24) as shown in FIG. 2 with one main light beam (MB) and two auxiliary light beams (SB1, SB2). Information is recorded with the light beam (MB), and the preformatted auxiliary signal is read with the auxiliary light beams (SB1 and SB2). The optical pickup (28) is located between the laser diode (LD) and the photodetector (PD) and divides the laser light beam by a beam splitter (B).
S), optical disk (24) and beam splitter (B)
The objective lens (OL) installed between S). The objective lens (OL) focuses the laser light beam traveling from the beam splitter (BS) toward the optical disc (24).
The beam splitter (BS) is a laser diode (L
The laser light beam from D) is irradiated onto the surface of the optical disc (24) via the objective lens (OL), and the reflected light beam reflected by the optical disc (24) passes through the sensor lens (SL). Via the photodetector (PD). The sensor lens (SL) focuses the light beam traveling from the beam splitter (BS) toward the photodetector (PD) and adjusts the focus by the astigmatic difference method. The light beam generated by the laser diode (LD) is divided into three light beams (MB, SB) by the diffraction grating (GT).
1, SB2) are separated. And the diffraction grating (GT)
The light beams (MB, SB1, SB2) separated by the beam pass through the beam splitter (BS) and the objective lens (O
2) in the groove track of the optical disc (24) as shown in FIG.
It is focused on (22). Optical disc (24) groove track
Light beams reflected by (22) (MB, SB1, SB
2) is an objective lens (OL) and a beam splitter (B)
The light is focused on the surface of the photodetector (PD) by the sensor lens (SL) via S). The photodetector (PD) converts the auxiliary light beams (SB1, SB2) into electrical signals.
The servo unit (30) drives an actuator (ACT) in the optical pickup (28) by an electric signal from the photodetector (PD) to perform focusing servo, tracking servo and the like. On the other hand, the motor drive unit (32) adjusts the rotation speed of the spindle motor (26) according to the signal from the servo unit (30).

The optical disk recording apparatus further comprises a carrier signal detector (34) and an auxiliary signal decoder (36) connected in series to the photodetector (PD) of the optical pickup (28). The carrier signal detector (34) detects the carrier signal (Pc) from the electrical signal from the photodetector (PD), and the auxiliary signal decoder (36)
Decodes the auxiliary address (PAdd) and auxiliary clock (PCLK) from the carrier signal (Pc) and the auxiliary synchronization signal (PYre) as shown in FIG. The auxiliary sync signal (PYre) divides the signal track (20 or 22) of the optical disk (24) into unit blocks of a certain size, and the auxiliary address (PAdd) indicates the physical position of each unit block. In addition, the optical disc recording apparatus according to the embodiment of the present invention uses the auxiliary sync signal (P) from the auxiliary signal decoder 36.
Yre) is input from the reference synchronization signal generator (38) and the reference clock generator (40) to the stabilization information control signal (CVFO).
VF using the reference clock (SCLK) from the pseudo-synchronous signal generator (42) that inputs
A VFO signal generator (44) for generating an O signal is provided. The reference synchronization signal generator 38 generates a reference synchronization signal (SYre) that is phase-locked with the auxiliary synchronization signal (PYre). The reference clock generator (40) generates a reference clock (SCLK) as shown in FIG. 6 whose phase and frequency are synchronized with the auxiliary clock (PCLK) from the auxiliary signal decoder (36). The frequency of the reference clock (SCLK) increases from N times the auxiliary clock (PCLK) to M times the auxiliary clock for a certain period from the start of recording. After the lapse of the certain period, the frequency of the reference clock (SCLK) is increased from M times the auxiliary clock (PCLK) to the auxiliary clock (PC).
LK) N times lower. To describe this in detail, the reference clock (SCLK) corresponds to a section from the discontinuous recording position (DCP) to the position on the signal track (20 or 22) of the optical disc (24) where the recording of the VFO signal is completed. The frequency changes from N times the auxiliary clock (PCLK) to M times the auxiliary clock (PCLK) during the period. After the VFO signal is recorded, the reference clock (SCLK) is a period corresponding to a section from the end position of the section in which the VFO signal is recorded to the end point of the unit block adjacent to the discontinuous recording position (DCP) or a constant value. The frequency gradually decreases from M times to N times the auxiliary clock (PCLK) during a period corresponding to a number of unit blocks. And the reference clock generator (4
0) is a stabilization information control signal (CVFO) using the recording start signal (WRsta) from the control unit (50) and the auxiliary synchronization signal (PYre) from the auxiliary signal decoder (36) as shown in FIG. To occur. This stabilizing information control signal (C
VFO) is a signal track (20 or 22) on an optical disk (24)
The VFO signal can be inserted into the discontinuous recording position (DCP) on the signal track (20 or 22) of the optical disk (24) where the phase of the clock signal recorded in (1) is rapidly changed.
The stabilization information control signal (CVFO) is recorded on the optical disc as shown in FIG. 6 so that the VFO signal is recorded in a part of a unit block adjacent to the discontinuous recording position (DCP).
The pulse has a width considerably shorter than that of the unit block on the signal track (20 or 22) of (24). Further, the reference clock generator (40) uses the reference clock (SCLK) as an auxiliary clock (PCLK).
CLK), a locking signal (LK) having a specific logic (for example, high logic) can be generated when it has a frequency in a range of N times to M times a certain range. The pseudo sync signal generator (42) outputs the stabilization information control signal (CVFO) at the end point (eg, falling edge).
, A pseudo synchronization signal (PSre) that maintains a specific logic (for example, high logic) is generated for a certain period. The pseudo sync signal (PSre) has a pulse of a specific logic whose width is narrower than that of the reference sync signal. To this end, the pseudo sync signal generator (42) may include a monostable multivibrator.

Further, the optical disk recording apparatus has a recording information processing section (46) for inputting user information, and has a VFO.
VFO signal from signal generator (44) and recording information processing unit (46)
A control switch (SW1) for selectively supplying the recording signal from the optical controller to the light controller (48) is provided. Record Information Processing Unit (46)
Generates user block information by dividing user information into a certain size, and at the beginning of this user block information, the auxiliary address (P
Add) and the pseudo sync signal (PSre) from the pseudo sync signal generator (42) or the reference sync signal (SYre) from the reference sync signal generator (38) are added to form a user information block. Further, the recording information processing section (46) uses the user information as a recording signal in accordance with the reference clock (SCLK) from the reference clock generator (40) to control the switch (SW1).
Supply to. The user information block including the pseudo synchronization signal (PSre) is transmitted by the reference clock (SCLK) having a frequency M times as high as the auxiliary clock (PCLK), so that the VFO signal and the signal track (20 or 20) of the optical disc (24) are transmitted. 22) It is recorded in one unit block above. That is, the user information block including the pseudo synchronization signal (PSre) has a shorter cycle than the user information block including the reference synchronization signal (SYre) by being temporally compressed. The control switch (SW1) selectively transmits the VFO signal and the recording signal to the optical controller (48) according to the logic state of the stabilization information control signal (CVFO) from the reference clock generator (40). To explain this in detail, when the stabilization information control signal (CVFO) maintains a specific logic (that is, high logic), the control switch (SW1) outputs the VFO signal from the VFO signal generator (44). To the light controller (48). On the contrary,
The stabilization information control signal (CVFO) is a basis logic (eg,
When maintaining the low logic), the recording signal from the recording information processing unit (46) is transmitted to the optical controller (48). Light controller (4
8) is a signal track of the optical disc (24), that is, a mountain track (20) or a groove track (22) where the user information block is intermittently connected to the laser diode (LD) according to the logical value of the output signal of the control switch (SW1) ). At this time, the unit block adjacent to the discontinuous recording position (DCP) of the signal track (20 or 22), that is, the signal track in which the frontmost portion of the user information is recorded at the start of recording
As shown in FIG. 6, a pseudo sync signal (PSre) block identification code and user block information are sequentially recorded in an arbitrary unit block (20 or 22) including a VFO signal which is clock stabilizing information. On the other hand, a block section separated from the discontinuous recording position (DCP), a reference synchronization signal (SYre) block identification code, and user block information are recorded in each block section.

Finally, the control unit 50 controls the operation of the servo unit 30 and the motor driving unit 32, and also controls the operation mode of the optical controller 48. Further, the control unit (50) generates a recording start signal (WRsta) having a pulse of a specific logic (for example, high logic) at the time of recording start. This recording start signal (WRsta) is supplied to the reference clock generator (40) and VFO which is clock stabilization information is recorded in a certain section from a recording discontinuity point on the signal track (20 or 22) on the optical disk (24). Allow the signal to be recorded. Further, the control unit (50) can input the locking signal (LK) from the reference clock generator (40). The control unit 50 selectively enables the recording operation of the optical controller 48 according to the logic state of the locking signal LK. The controller 50 causes the optical controller 48 to perform a recording operation only when the locking signal LK maintains a specific logic (for example, a high logic), so that the recording density of the optical disk 24 is constant. Is maintained and the occurrence of errors is prevented.

FIG. 7 shows the reference clock generator (4
This is a block showing (0) in detail. In FIG. 7, a reference clock generator (40) includes a frequency divider (54) for inputting a reference clock (SCLK) from a voltage controlled oscillator (52) through a first AND gate (62), and this frequency divider. A phase comparator (56) for inputting the output signal of (54) and a frequency comparator (58) are provided. First
The AND gate (62) switches the reference clock (SCLK) supplied from the voltage controlled oscillator (52) to the frequency divider (54) by the stabilization information control signal (CVFO). The first AND gate (62) prevents the reference clock (SCLK) from the voltage controlled oscillator (52) from being supplied to the frequency divider (54) when the stabilization information control signal (CVFO) maintains a high logic.
That is, the first AND gate 62 supplies a low signal of low logic to the frequency divider 54. As a result, a logic signal of low logic or high logic is generated also in the frequency divider (54). At this time, since the phase comparator 56 compares the phase of the auxiliary clock (PCLK) from the auxiliary signal decoder 36 shown in FIG. 5 with the logic signal from the frequency divider 54, the phase comparator 56 rapidly increases. A phase error signal having a voltage signal is supplied to the integrator (60). A frequency comparator (58) that compares the frequency of the logic signal from the frequency divider (54) with the auxiliary clock (PCLK) also supplies a frequency error signal having a rapidly increasing voltage signal to the integrator (60). Integrator (60)
Is the phase error signal from the phase comparator (56) and the frequency comparator.
The frequency error signals from (58) are each integrated to remove the high frequency noise signals contained in these signals. Integrator
By the integrated phase error signal and frequency error signal from (60), the voltage controlled oscillator (52) receives the reference clock (SCL
The frequency of K) is rapidly increased from N times the auxiliary clock (PCLK) to M times the auxiliary clock (PCLK). As a result, the frequency of the reference clock (SCLK) sharply increases from N times to M times the auxiliary clock (PCLK) at the rising edge of the clock stabilization information control signal (CVFO), and
The M times the auxiliary clock (PCLK) is maintained until the falling edge instruction of the clock stabilization information control signal (CVFO). On the other hand, when the stabilization information control signal (CVFO) maintains the low logic, the first AND gate (62) divides the reference clock (SCLK) from the voltage controlled oscillator (52) by the frequency divider.
(54). In this case, the frequency divider (54) uses the reference clock (SCLK) from the first AND gate (62).
Is divided by N. At this time, the phase comparator (56) generates a phase error signal having a voltage signal that is gradually reduced due to the phase difference between the auxiliary clock (PCLK) and the divided clock signal from the frequency divider (54). To do. Similarly, a frequency comparator
Also, (58) generates a frequency error signal in which the voltage gradually decreases due to the difference in frequency between the clock signal from the frequency divider (54) and the auxiliary clock (PCLK). Then, the integrator (6
The voltage controlled oscillator (52) which inputs the phase error signal and the frequency error signal via 0) gradually advances the frequency of the reference clock (SCLK) from M times the auxiliary clock (PCLK) to N times the auxiliary clock (PCLK). Will be lower. Accordingly, the frequency of the reference clock (SCLK) is maintained for a certain period (for example, the clock stabilization information (CVFO)) from the falling edge of the clock stabilization information control signal (CVFO).
(VFO) from the end time of the section on the signal track (20, 22) to the end position of the unit block in which the clock stabilization information is recorded) from M times the auxiliary clock (PCLK) It becomes progressively lower up to N times. At the same time, the reference clock (SCLK) is supplied to the VFO signal generator (44) and the recording information processing unit (46) shown in FIG. In addition, when the divided reference clock signal has a frequency difference of a certain range as compared with the auxiliary clock (PCLK), that is, the reference clock (SCLK) has a frequency N times to M times that of the auxiliary clock (PCLK). , The frequency comparator 58 generates a locking signal (LK) having a specific logic (eg, high logic). This locking signal (LK) is supplied to the control unit (50) shown in FIG.

The reference clock generator (40) is shown in FIG.
The recording start signal (WRst
It further comprises a first latch 64 for inputting a) and a NAND gate 66 for inputting an auxiliary synchronizing signal (PYre) from the auxiliary signal decoder 36 shown in FIG. The first latch 64 has a specific logic (that is, high logic) at its own set terminal (S).
When the recording start signal (WRsta) is input, a high logic output signal is generated at its own output terminal (Q). The NAND gate 66 performs a NAND operation on the output signal of the first latch 64 and the auxiliary synchronization signal PYre, and selectively toggles the second latch 68 according to the result of the NAND operation. That is, the NAND gate 66 generates a low logic pulse only when both the output signal of the first latch 64 and the auxiliary synchronization signal PYre maintain a high logic. Second latch (6
8) changes the logic signal on its own output terminal (Q) from low logic to high logic from the rising edge of the low logic pulse from the NAND gate 66. The first and second latches (64,
68) is a stabilization information control signal (CVFO) of the base logic (that is, low logic) applied at its reset terminal (R)
Is initialized by.

Further, the reference clock generator (40) has a second AND gate (70) for inputting the reference clock (SCLK) from the voltage controlled oscillator (52) and a counter for inputting the output signal of the second latch (68). (72) and an inverter (74) for inputting a carry signal from the counter (72). Second AN
The D gate 70 counts the reference clock SCLK from the voltage controlled oscillator 52 only while the stabilization information control signal CVFO maintains a specific logic (ie, high logic).
It is transmitted to the clock terminal (CLK) of (72). The counter 72 is connected to the second latch 68 while the high logic signal is applied to the reset terminal R of the second latch 68.
Reference clock (SCLK) supplied from ND gate (70)
Counts by adding. Then, the counter 72 generates a carry signal of high logic when the count value reaches "K". Also, the counter 72, after generating the carry signal, stops the counting operation by the low logic signal supplied from the second latch 68 to its own reset terminal (R). The inverter (74) inverts the carry signal from the counter (72) and uses the inverted carry signal as a stabilization information control signal (CVFO) in the first and second AND gates (62, 70), the first and second AND gates. latch
(64, 68), the control switch (SW1) and the pseudo sync signal generator (42) shown in FIG. As a result, the second latch (68), the second AND gate (70), the counter (72) and the inverter (74) have a constant width from the falling edge of the first auxiliary sync signal (PYre) at the start of recording. Performs the function of a monostable pulse generator that generates a stabilized information control signal (CVFO) having a high logic pulse.

FIG. 8 is a block diagram of an optical disc recording apparatus according to another embodiment of the present invention. The optical disc recording apparatus according to another embodiment shown in FIG. 8 is different from the optical disc recording apparatus shown in FIG. 5 in that the second control switch (SW1) is connected between the control switch (SW1) and the optical controller (48). S
W2) is further provided. In addition, an optical disk recording apparatus according to another embodiment has a reference clock generator (40) shown in FIG.
Instead of the above, an adaptive reference clock generator (76) is provided.

This adaptive reference clock generator (76) is shown in FIG.
Similarly to the reference clock generator (40) shown in FIG. 9, a reference clock ( SCLK ) as shown in FIG. 9 is generated, and the reference clock ( SCLK ) is recorded in the recording information processing unit (46) and the VFO signal generator (44). Supply to. Then, the adaptive reference clock generator (76) outputs the recording start signal (WRst) as shown in FIG.
a) is generated, the first auxiliary sync signal (PYre)
Margin control signal (Cs
pc) and a stabilizing information control signal (CVFO).
The margin control signal (Cspc) causes the second control switch (SW2) to selectively connect the recording information processing unit (46) to the optical controller (48), thereby enabling the signal track (20 or 22) of the optical disc (24). ) to generate a margin section which information is not recorded
To do so. The blank section is located between the discontinuous recording position (DCP) on the signal track (20 or 22) of the optical disc (24) and the clock stabilization information section. That is, the block section adjacent to the discontinuous recording position (DCP) on the signal track (20 or 22) of the optical disk (24) has a blank section (SPC), a VFO signal (VFO), and a pseudo sync as shown in FIG. The signal (PSre), the block identification signal, and the user block information are recorded.

An optical disk recording apparatus according to another embodiment of the present invention is a photodetector (P) in an optical pickup (28).
A reproduction signal processing unit (51) for reproducing the output signal of D) and supplying a reproduction synchronization signal (RYre) to the adaptive reference clock generator (76) may be further provided. In this case, the adaptive reference clock generator (76) changes the logical state of the blank space control signal (Cspc) depending on the phase relationship between the reproduction sync signal (RYre) and the auxiliary sync signal (PYre). As shown in FIGS. 10 and 11, the adaptive reference clock generator (76) detects the phase of the reproduction synchronization signal (SYre) as the auxiliary synchronization signal (PYr).
If it is earlier than step e), the blank space control signal (Cspc) maintains the basic logic (that is, the low logic) so that the blank space does not appear on the signal track (20 or 22) of the optical disk (24). . That is, the signal track of the optical disc (24)
The VFO signal (VFO), the pseudo sync signal (PSre), the block identification signal, and the user block information are recorded in the unit block adjacent to the discontinuous recording position (DCP) on (20 or 22). On the other hand, as shown in FIG. 12, when the phase of the reproduction synchronization signal (RYre) is later than that of the auxiliary synchronization signal (PYre), the adaptive reference clock generator (76) outputs the margin control signal (Cspc) as the auxiliary synchronization signal (PYre). From the falling edge to the rising edge of the reproduction synchronizing signal (RYre), a blank section is generated on the signal track (20 or 22) of the optical disk (24). That is, the unit block adjacent to the discontinuous recording position (DCP) on the signal track (20 or 22) of the optical disc (24) has a blank space (SP) as shown in FIG.
C), VFO signal (VFO), pseudo sync signal (PSr
e), the block identification signal and the user block information are recorded.

FIG. 13 is a detailed circuit diagram of the first embodiment of the adaptive reference clock generator (76) shown in FIG.
In FIG. 13, the adaptive reference clock generator (76) is shown in FIG.
When comparing with the reference clock generator (40) shown in
A third latch (78), a second counter (84) and a second inverter (86) connected in series between the NAD gate (66) and the second latch (68), a voltage controlled oscillator (52) and a second counter. (84)
Second divider connected in series between the clock terminals (CLK) of
(80) and a third AND gate (82) are further provided. The adaptive reference clock generator (76) is the first AND gate shown in FIG.
Instead of the gate (62), the reference clock (SCLK) from the voltage controlled oscillator (52), the stabilizing information control signal (CVFO) from the first inverter (74) and the second inverter (86).
4th AND which inputs the blank control signal (Cspc) from
It is equipped with a gate (88).

The third latch 78 changes the logic signal on its output terminal (Q) from low logic to high logic at the rising edge of the output signal of the NAND gate 66. That is, as shown in FIG. 9, the third latch 78 receives the auxiliary sync signal (PYr) that is input first after the recording start signal (WRsta) is generated.
A high logic output signal is generated in response to the e) falling edge instruction. The second frequency divider (80) divides the reference clock (SCLK) from the voltage controlled oscillator (52) by N and supplies the divided reference clock to the third AND gate (82). The third AND gate (82) divides the reference voltage from the second divider (80) only while the margin control signal (Cspc) shown in FIG. 9 maintains a specific logic (that is, a high logic). The clock is transmitted to the clock terminal (CLK) of the second counter (84). The second counter (84) is added by the divided reference clock from the third AND gate (82) while the high logic signal is applied from the third latch (78) to its own reset terminal (R). To count. Also, the second counter
(84) generates a carry signal of high logic when the count value reaches "L". Also, the second counter 84, after generating the carry signal, stops the counting operation by the low logic signal supplied from the third latch 78 to its own reset terminal R. . The second inverter (86) inverts the carry signal from the second counter (84) and outputs the inverted carry signal to the blank space control signal (Csp).
As c), the third and fourth AND gates (82, 88), the third latch (78) and the second control switch (S) as shown in FIG.
Supply to W2). As a result, the third latch (78), the third A
The ND gate (82), the second counter (84) and the second inverter (86) are used to record the first auxiliary sync signal (PY) at the start of recording.
It functions as a monostable pulse generator that generates a blank control signal (Cspc) having a high logic pulse of constant width from the falling edge of re). The margin control signal (Cspc) causes the second latch 68 to generate a stabilization information control signal (CVFO).
Determine the time of occurrence of. That is, the second latch (68) starts the counting operation of the first counter (72) from the falling edge of the blank control signal (Cspc) from the second inverter (86), and then the first inverter (74). By initializing with the stabilizing information control signal (CVFO) of low logic, the stabilizing information control signal (CVFO) has a high logic of a certain width from the falling edge of the margin control signal (Cspc) as shown in FIG. To

On the other hand, the fourth AND gate (88) receives a reference clock (supplied from the voltage controlled oscillator (52) to the first frequency divider (54) by the margin control signal (Cspc) and the stabilization information control signal (CVFO). SCLK) is switched. 4th AND
The gate (88) receives the reference clock (SCLK) from the voltage controlled oscillator (52) when the high logic is maintained in any one of the margin control signal (Cspc) and the stabilization information control signal (CVFO). Make sure that it is not supplied to the 1-divider (54). That is, the fourth AND gate (88) is the optical disc (24)
The reference clock (SCLK) is not supplied to the first frequency divider (54) during the recording period of the blank signal and the VFO signal on the signal track (20 or 22). Unlike this,
Margin control signal (Cspc) and stabilization information control signal (CV
FO) maintains a low logic, the fourth AND gate
(88) is a reference clock (SCL from the voltage controlled oscillator (52)
K) is supplied to the first frequency divider (54).

Except for the second and third latches (68, 78), the third and fourth AND gates (82, 88), the frequency divider (80), the second counter (86) and the second inverter (86). The description of the operation of the remaining components of the adaptive reference clock generator (76) of FIG.

FIG. 14 is a circuit diagram showing in detail the second embodiment of the adaptive reference clock generator (76) shown in FIG. The adaptive reference clock generator (76) shown in FIG. 14 is the same as the adaptive reference clock generator (76) shown in FIG. 13, except that the fourth AND gate (88) is replaced by the clock adjuster (90).
It has the same circuit configuration as. The clock 90 is a reference clock for a certain period from a time when the margin control signal Cspc is enabled (for example, a period from a discontinuous recording point to a point where one unit block is ended). The frequency of (SCLK) is the auxiliary clock (PCL
Try to keep M times K) constant. To this end, the clock controller 90 controls the blank control signal Cspc from the second inverter 86 from low logic to high logic, and then, at a constant cycle during a period corresponding to one unit block. The reference clock (SCLK) transmitted from the voltage controlled oscillator (52) to the first frequency divider (54) is removed one by one. In this case, the phase error signal generated by the phase comparator (56) and the frequency error generated by the frequency (58) increase once at a constant cycle and then decrease. Then, the voltage controlled oscillator (52) responsive to the phase error signal and the frequency error signal adjusts the phase and frequency of the reference clock (SCLK) to adjust the reference clock (SCL).
The phase of K) is made to match the phase of the auxiliary clock (PCLK), and the frequency of the reference clock (SCLK) is kept constant M times higher than that of the auxiliary clock (PCLK). On the contrary, the margin control signal (Csp
c) and the stabilizing information control signal (CVFO) maintain the basic logic (low logic), the clock controller 90 keeps the reference clock (SCLK) from the voltage controlled oscillator 52 as it is as the first frequency divider. The frequency of the reference clock (SCLK) is transmitted to (54) to the auxiliary clock (PCLK).
N times constant.

FIG. 15 shows the clock adjuster (9
FIG. 3 is a circuit diagram illustrating (0) in detail. In FIG. 15, a clock controller 90 is a stabilizing information control signal CVFO from the first and second inverters 74 and 86 shown in FIG.
OR gate (92) for inputting the margin control signal (Cspc)
And a fifth AND gate for commonly inputting the reference clock (SCLK) from the voltage controlled oscillator (52) shown in FIG.
(94), a third frequency divider (96) and an exclusive OR (hereinafter referred to as "XOR") gate (98). The OR gate 92 performs an OR operation on the stabilization information control signal CVFO and the margin control signal Cspc to generate a pulse signal that maintains a high logic during the high logic period of these two signals.
The fifth AND gate 94 transmits the reference clock SCLK to the clock terminal CLK of the third counter 100 while the output signal of the OR gate 92 maintains the high logic. The third counter (100) counts the number of clock signals supplied from the fifth AND gate (94) to its own clock terminal (CLK). On the other hand, the third frequency divider (96) divides the reference clock (SCLK) by a constant frequency division ratio (for example, 4), and the divided reference clock is divided by the sixth AND gate (1).
It is supplied to the 4th counter (104) via 02). Fourth
The counter (104) counts the number of divided reference clocks from the sixth AND gate (102). 3rd counter
The count value of (100) and the count value of the fourth counter (104) are compared by a comparator (106). This comparator (106)
Supplies a high logic comparison signal to the sixth AND gate (102) when the two count values are the same, the reference clock divided by the third divider (96) is supplied to the fourth counter (1).
04) and XOR gate (98).
That is, the sixth AND gate (102) has the count value of the fourth counter (104) from the start of recording to the third counter (10
Until the count value becomes 0), the divided reference clock is supplied to the XOR gate (98).
The XOR gate (98) inverts the phase of the reference clock (SCLK) by 180 ° whenever the divided reference clock from the sixth AND gate (102) maintains a high logic, so that the XOR gate (98) shown in FIG. One cycle of the reference clock is deleted from the reference clock (SCLK) supplied to the one-frequency divider (54). The frequency division ratio of the third frequency divider 96 is equal to the high logic width of the margin control signal Cspc and the stabilization information control signal C
VFO) is determined by the ratio of the period corresponding to the high logic width and the period of the unit block.

FIG. 16 is a circuit diagram showing in detail the third embodiment of the adaptive reference clock generator (76) shown in FIG.
This adaptive reference clock generator (76) is a voltage controlled oscillator (5
2) Reference clock (SCLK) from the first AND gate
A first frequency divider (54) for input via (108), a phase comparator (56) for inputting an output signal of the first frequency divider (54), and a frequency comparator (58). The first AND gate (108) switches the reference clock (SCLK) according to the switching control signal. The first AND gate (108) prevents the reference clock (SCLK) from the voltage controlled oscillator (52) from being supplied to the first frequency divider (54) when the switching control signal maintains a high logic. That is, the first AND gate 108 supplies a low logic signal to the first frequency divider 54. As a result, a logic signal of low logic or high logic is also generated in the first frequency divider (54). At this time, since the phase comparator 56 compares the phase of the auxiliary clock (PCLK) from the auxiliary signal decoder 36 shown in FIG. 8 with the logic signal from the first frequency divider 54, the phase comparator 56 rapidly increases. A phase error signal having a voltage signal is supplied to the integrator (60). A frequency comparator (58) for comparing the frequency of the logic signal from the first frequency divider (54) with the auxiliary clock (PCLK) also has a frequency error signal having a voltage signal that rapidly increases.
Supply to 0). The integrator (60) integrates the phase error signal from the phase comparator (56) and the frequency error signal from the frequency comparator (58), respectively, and removes the noise signal of the high frequency component contained in these signals. The integrated phase error signal and frequency error signal from the integrator (60) allow the voltage controlled oscillator (5
2) is the frequency of the reference clock (SCLK) from N times the auxiliary clock (PCLK) to M of the auxiliary clock (PCLK).
Sharply increase to twice. As a result, the reference clock (SCL
The frequency of K) rises sharply from N times to M times the auxiliary clock (PCLK) at the rising edge of the switching control signal, and then the auxiliary clock (PCLK) until the falling edge of the switching control signal.
To maintain M times. When the switching control signal maintains the low logic, the first AND gate (108) divides the reference clock (SCLK) from the voltage controlled oscillator (52) into the first frequency divider.
Supply to (54). In this case, the first frequency divider (54) is the first AN
The reference clock (SCLK) from the D gate (108) is divided by N. At this time, the phase comparator (56) operates the auxiliary clock (PC
LK) and a phase error signal having a voltage signal that gradually decreases due to the phase difference between the frequency-divided clock signal from the first frequency divider (54). Similarly, the frequency comparator (58) also receives the clock signal from the first frequency divider (54) and the auxiliary clock (PC
The frequency difference with LK) produces a frequency error signal whose voltage gradually decreases. Then, the voltage controlled oscillator (52) which inputs the phase error signal and the frequency error signal through the integrator (60) changes the frequency of the reference clock (SCLK) from M times the auxiliary clock (PCLK) to the auxiliary clock (PC).
LK) gradually lower to N times. As a result, the frequency of the reference clock (SCLK) is maintained for a certain period (for example, the clock on the signal track (20 or 22) where the recording of the clock stabilization information ends) on the falling edge of the switching control signal. During the period up to the end position of the unit block in which the stabilization information is recorded, the auxiliary clock (P
CLK) from M times to N times. This recording clock (SCLK) is the VFO signal generator shown in FIG.
(44) and the recording information processing unit (46). Further, the frequency comparator (58) determines that the divided reference clock has a frequency difference of a certain range compared to the auxiliary clock (PCLK), that is, the reference clock (SCLK) is the auxiliary clock (PCLK).
A locking signal (LK) having a specific logic (eg, high logic) is generated when the frequency is N to M times higher than CLK). This locking signal (LK) is supplied to the control unit (50) shown in FIG.

The adaptive reference clock generator (76) receives the recording start signal (WRsta) shown in FIGS. 10 to 12 from the control unit (50) shown in FIG. ) And the auxiliary synchronization signal (PYre) from the auxiliary signal decoder (36) shown in FIG.
(112) and the second AND gate (116) for inputting the reproduction synchronization signal (RYre) from the reproduction signal processing unit (51) shown in FIG.
Is further provided. The first latch 110 outputs an output signal of high logic to its output terminal (Q) when a recording start signal (WRsta) of a specific logic (that is, high logic) is input to its set terminal (S). Occur. The NAND gate 112 performs a NAND operation on the output signal of the first latch 110 and the auxiliary synchronization signal PYre, and selectively toggles the second latch 114 according to the result. NAND gate (1
12) is the output signal of the first latch (110) and the auxiliary synchronization signal (PY
generates a low logic pulse when re) maintains high logic. The second latch 114 changes the signal on its output terminal (Q) from low logic to high logic at the rising edge of the low logic pulse from the NAND gate 112.
On the other hand, the second AND gate (116) performs an AND operation on the output signal of the first latch (110) and the reproduction synchronization signal (RYre) to make a first operation.
Playback synchronization only when the output signal of the latch (110) maintains high logic, that is, when the first user information block is recorded on the signal track (20 or 22) of the optical disc (24) at the start of recording. Pass the signal (RYre).

Further, the adaptive reference clock generator (76) includes a second frequency divider (118) connected in series with the voltage controlled oscillator (52),
The third AND gate 120, the first counter 122, and the first inverter 124 are provided. The second frequency divider (118) divides the reference clock (SCLK) from the voltage controlled oscillator (52) into a constant frequency division ratio (N), and the divided reference clock is supplied to the third AND gate (120). Supply to. The third AND gate 120 outputs the divided reference clock from the second divider 118 to the first counter 122 while the margin control signal Cspc maintains a specific logic (i.e., high logic). It is transmitted to the clock terminal of. The first counter 122 is driven by the divided reference clock supplied from the third AND gate 120 while the high logic signal is applied to the reset terminal R of the second latch 114. Count up. Then, the first counter 122 generates a carry signal of high logic when the count value reaches "L". Also, the first counter (122) generates a carry signal and then resets its own reset terminal (R) from the second latch (114).
The count operation is stopped by the logic signal of low logic supplied to the. Alternatively, the first counter (12
2) has a specific logic (for example, when a reproduction sync signal (RYre) of low logic is input from the second AND gate (116), that is, at the end of the first reproduction sync signal (RYre).
High logic) can be generated. This makes the first
The carry signal generated from the counter 122 is maintained at a high logic level or has a constant width from the end of the auxiliary synchronization signal (PYre), that is, less than or equal to N × L reference clock cycles. Will have a logic (eg, low logic) pulse. 1st inverter (12
4) inverts the carry signal from the first counter (122), and uses the inverted signal as the margin control signal (Cspc), the third AND gate (120), and the second control switch (SW2) shown in FIG. ) To. The margin control signal (Cspc) is the operation mode of the first counter 122, that is, the reproduction synchronization signal (RYre) and the auxiliary synchronization signal (PYr).
The pulse has a specific logic (that is, a high logic) selectively due to the phase relationship with e). The margin control signal (Cspc) is the auxiliary sync signal (PYr) after the reproduction sync signal (RYre) is finished as shown in FIGS.
Maintain the base logic (i.e., low logic) when e) is terminated. In this case, the signal track (2
No blank space is generated at 0 or 22). On the other hand, when the reproduction sync signal (RYre) ends later than the end of the auxiliary sync signal (PYre) as shown in FIG. 12, the margin control signal (Cspc) has a pulse of a specific logic. At this time, the pulse of the margin control signal (Cspc) is
It has a width corresponding to a period from the end time of the auxiliary sync signal (PYre) to the end time of the reproduction sync signal (RYre). In this way, when the specific logic pulse exists in the blank control signal (Cspc), the blank section (SPC) corresponding to the width of the specific logic pulse is generated on the signal track (20 or 22) of the optical disc (24). Will be done.

Furthermore, the adaptive reference clock generator (76) is connected to the output terminal of the second AND gate (116) in series with the fourth reference clock generator (76).
An AND gate 126, a third latch 128, a fifth AND gate 130, a second counter 132, and a second inverter 134 connected in series to the voltage controlled oscillator 52 are provided. The fourth AND gate 126 is connected to the margin control signal Cspc from the first inverter 124 and the second AND gate 11
The output signal of 6) is ANDed and the third latch (128) is selectively toggled according to the result. 4th AND gate
(126) is the falling edge of the blank space control signal (Cspc), that is, the end time of the blank space control signal (Cspc) or the second AND
At the falling edge of the output signal of the gate (116), that is, at the end of the first reproduction synchronizing signal (RYre), the third latch (128)
Toggle. At this time, the output signal of the third latch 128 changes from low logic to high logic. The fifth AND gate 130 is a voltage controlled oscillator only while the stabilization information control signal CVFO maintains a specific logic (ie, high logic).
Second counter for reference clock (SCLK) from (52)
It is transmitted to the clock terminal (CLK) of (132). The second counter (132) receives a reference clock (S) supplied from the fifth AND gate (130) while the high logic signal is applied to the reset terminal (R) of the third latch (128).
CLK) to count the addition. Also, the second counter
(132) generates a carry signal of high logic when the count value reaches "K". After generating the carry signal,
The second counter 132 stops the counting operation by the low logic signal supplied from the third latch 128 to its own reset terminal R. The second inverter (134) inverts the carry signal from the second counter (132) and outputs the inverted carry signal to the stabilization information control signal (CVF).
O) as the fifth AND gate (130) and the third latch (128)
To the first control switch (SW1) and the pseudo sync signal generator (42) shown in FIG. The stabilization information control signal (CVFO) is the margin control signal (Cs) as shown in FIG.
When the specific logic pulse is included in pc), the specific logic (for example, high logic) is maintained for a certain period from the end time of the margin control signal (Cspc). On the other hand, when the margin control signal (Cspc) does not include a pulse of a specific logic as shown in FIGS. 10 and 11, the stabilization information control signal (CVFO) is the first reproduction synchronization signal (RYr).
e) the falling edge, that is, for a certain period from the end point,
Maintain high logic. Then, the third latch 128 is initialized by the stabilizing information control signal CVFO of the base logic (that is, the low logic) applied to the reset terminal (R) of the third latch 128.

The adaptive reference clock generator (76) has a first
A fourth latch (138) toggled by the output signal of the NAND gate (112), an OR gate (136) to which the stabilizing information control signal (CVFO) is input, and a third inverter (140)
Equipped with. The OR gate (136) is connected to the margin control signal (Csp
c) and the stabilization information control signal (CVFO) are ORed,
The output signal of the second latch 114 is initialized by the calculated result. The fourth latch (138) is the second latch (114)
Similarly to the rising edge of the pulse of the low logic from the first NAND gate (112), that is, at the start of recording, the signal on its own output terminal (Q) is output from the end of the first auxiliary synchronization signal (PYre). Change from low logic to high logic.
Then, the fourth latch (138) supplies its own output signal to the first AND gate (108) and the second NAND gate (144) as a switching control signal. The third inverter 140 inverts the stabilization information control signal CVFO and applies the inverted stabilization information control signal to the toggle terminal T of the fifth latch 142. The fifth latch (142) supplies the toggle terminal (T) of the third inverter (140) to the toggle terminal (T) of the third inverter (140) to invert the rising edge of the stabilization information control signal, that is, the end point of the stabilization information control signal (CVFO) Generates a logic signal of high logic from its own output terminal (Q). The output signal of the fifth latch (142) is applied to the first latch (110) and the second N
It is supplied to the AND gate (144). Second NAND gate
(144) is the output signal of the first latch (110) and the fourth latch (13
AND the output signal of 8) and the output signal of the fifth latch (142)
Calculate and generate a low logic pulse. This second NA
The first by the low logic pulse from the ND gate (144),
The output signals of the fourth and fifth latches (110, 138, 142) are initialized. As a result, the output signal of the first latch 110 maintains a high logic from the rising edge of the recording start signal WRsta, that is, from the recording start time to the falling edge of the stabilization information control signal CVFO. The switching control signal generated from the fourth latch 138 is the falling edge of the auxiliary synchronization signal PYre, that is, the falling edge of the stabilization information control signal CVFO from the end, that is, the stabilization information control signal CVFO. High logic is maintained until the end time of a). On the other hand, the output signal of the fifth latch (142) is
Since the latch 142 forms a circular loop with the second NAND gate 144, it has a high logic pulse form. The first AND gate (108) switches the reference clock (SCLK) supplied from the voltage controlled oscillator (52) to the first frequency divider (54) by the switching control signal. First AND gate (108)
The reference clock (SCLK) from the voltage controlled oscillator (52) is a variable frequency divider when the switching control signal maintains high logic.
Do not supply to (54). When the switching control signal maintains a low logic, the reference clock (SCLK) from the first AND gate (108) voltage controlled oscillator (52) is a variable frequency divider.
Supplied to (54).

FIG. 17 is a circuit diagram showing in detail the fourth embodiment of the adaptive reference clock generator (76) shown in FIG.
The adaptive reference clock generator (76) shown in FIG.
The circuit configuration is the same as that of the adaptive reference clock generator (76) of the third embodiment shown in FIG. 16 except that the ND gate (108) is replaced by the clock adjuster (146). The clock adjuster 146 controls the reference clock (SCLK) from a time when the switching control signal is enabled to a certain time (for example, from a discontinuous recording position (DCP) to a point where one unit block is ended). The frequency of 1) is constantly maintained at M times the auxiliary clock (PCLK). To this end, the clock controller (146) controls the voltage controlled oscillator (52) at regular intervals while hitting one unit block after the switching control signal from the fourth latch (138) changes from low logic to high logic. ), The reference clock (SCLK) transmitted to the first frequency divider 54 is removed one by one. In this case, the phase error signal generated by the phase comparator (56) and the frequency error signal generated by the frequency comparator (58) increase once for each fixed cycle and then decrease. Then, the voltage controlled oscillator (52) responsive to the phase error signal and the frequency error signal adjusts the phase and frequency of the reference clock (SCLK) so that the phase of the reference clock (SCLK) becomes the phase of the auxiliary clock (PCLK). The frequency of the reference clock (SCLK) is kept constant M times as high as that of the auxiliary clock (PCLK). The clock adjuster (146) removes the OR gate (92) for inputting the stabilization information control signal (CVFO) and the margin control signal (Cspc) from the circuit elements of the clock adjuster (90) shown in FIG. And instead of the fourth in FIG.
This can be realized by supplying the switching control signal from the latch (138).

[0047]

As described above, according to the present invention, the clock stabilizing information is provided in the block section adjacent to the discontinuous recording position on the signal track of the optical disc in which the auxiliary signal is preformatted in a region different from the signal track. Recorded with user information. As a result, the user information recorded in the block section adjacent to the discontinuous recording position on the signal track can be reproduced stably, and the recording capacity of the optical disk becomes large. Further, according to the present invention, a blank section is selectively generated between the clock stabilization information and the discontinuous recording position on the signal track of the optical disc due to the phase relationship between the reproduction synchronization signal and the auxiliary synchronization signal included in the auxiliary signal. To be done. As a result, the clock stabilization information is recorded in the block section adjacent to the discontinuous recording position so as to be synchronized with the reproduction synchronization signal. Also, the present invention keeps the recording capacity of the optical disc constant by recording information on the optical disc only when the reference clock is synchronized with the auxiliary clock included in the auxiliary signal, and minimizes the occurrence of errors. Can be converted.

[Brief description of drawings]

FIG. 1 is a diagram schematically illustrating an optical disc in which a hard sector auxiliary signal is pre-formatted.

FIG. 2 is a diagram schematically illustrating an optical disc in which a soft sector type auxiliary signal is pre-formatted.

3 shows a state in which information is discontinuously recorded on a signal track of the optical disc shown in FIG.

4 shows a clock signal recorded on the signal track shown in FIG. 3 and a reproduced state of the clock signal.

FIG. 5 is a block diagram of an optical disk recording device according to an embodiment of the present invention.

FIG. 6 is an output waveform diagram for each portion shown in FIG.

FIG. 7 is a detailed circuit diagram of the reference clock generator shown in FIG.

FIG. 8 is a block diagram of an optical disc recording device according to another embodiment of the present invention.

9 is an output waveform diagram of each part shown in FIG.

FIG. 10 is an output waveform diagram of each part shown in FIG.

FIG. 11 is an output waveform diagram of each part shown in FIG.

FIG. 12 is an output waveform diagram of each part shown in FIG.

FIG. 13 is a detailed circuit diagram of the first embodiment of the adaptive reference clock generator shown in FIG.

FIG. 14 is a detailed circuit diagram of the second embodiment of the adaptive reference clock generator shown in FIG.

15 is a detailed circuit diagram of the variable phase delay device shown in FIG.

16 is a detailed circuit diagram of a third embodiment of the adaptive reference clock generator shown in FIG.

17 is a detailed circuit diagram of a fourth exemplary embodiment of the adaptive reference clock generator shown in FIG. 8. FIG.

[Explanation of symbols]

10, 24 ... Optical disc 12- ・ Signal track 14 ... ・ Sector 16 --- Sector identification signal section 18 --- Main information signal section 20 ... ・ Mountain truck 22 .. ・ Groove track 26 ・ ・ ・ ・ ・ ・ Spindle motor 28- ・ Optical pickup 30 ... ・ Servo section 32 .... Motor drive unit 34 .. Carrier wave signal detector 36 .... Auxiliary signal decoder 38 .... Reference sync signal generator 40 .. · Reference clock generator 42 .. ・ Pseudo sync signal generator 44 ··· VFO signal generator 46 .. · Recording information processing unit 48 ・ ・ ・ ・ ・ ・ Light controller 50 ・ ・ Control unit 51 .. ・ Reproduction signal processing unit 52 ・ ・ ・ ・ ・ ・ Voltage controlled oscillator 54 ... First frequency divider 56 ・ ・ ・ ・ ・ ・ Phase comparator 58 .. ・ Frequency comparator 60 ・ ・ ・ ・ ・ ・ Integrator 62, 108 ... First AND gate 64, 110 ... First latch 66, 112 ... NAND gate 68, 114 ... Second latch 70 and 116 ... Second AND gate 72,122 ... First counter 74, 124 ... First inverter 76 .... Adaptive reference clock generator 78, 128 ... 3rd latch 80, 118 ... 2nd frequency divider 82, 120 ... 3rd AND gate 84, 132 ... Second counter 86,134 ... 2nd inverter 88, 126 ... 4th AND gate 90,146 ... Clock adjusters 92 ... OR gate 94, 130 ... Fifth AND gate 96 ... ・ Third frequency divider 98 ... XOR gate 100 ... ・ 3rd counter 102 ... 6th AND gate 104 ・ ・ 4th counter 106 ・ ・ ・ ・ ・ ・ Comparators 138 ... Fourth latch 140 ··· Third inverter 142 ... Fifth latch

Continued front page       (56) Reference JP-A-6-124547 (JP, A)                 JP-A-5-73920 (JP, A)                 Japanese Unexamined Patent Publication No. 2-141976 (JP, A)                 JP-A-6-131824 (JP, A)                 JP 64-1167 (JP, A)                 JP-A-63-39137 (JP, A)                 JP-A-7-225949 (JP, A)                 JP-A-6-208723 (JP, A)

Claims (2)

(57) [Claims] 1. A user information to be recorded is divided into user blocks information multiple, each user block information obtained by dividing their respective to the unit block of the multiple the signal track of the optical di <br/> disk a recording method for recording among the plurality of unit blocks, a portion directly adjacent unit blocks in discontinuous recording position of the signal track,
Auxiliary signal indicating the physical position of this unit block
Accordingly , a method for recording on the optical disc, characterized in that the clock stabilization information based on a clock having a predetermined frequency is recorded. 2. A method for recording on the optical disc according to claim 1.
In the section, the portion of the unit block directly adjacent to the discontinuous recording position of the signal track is directly adjacent to the discontinuous recording position.
In the margin section is provided, subsequent to the margin interval the clock
A method for recording on an optical disk, characterized by recording stabilization information .