JP3472271B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention
Nonvolatile semiconductor memory device (EEPROM),
In particular, more than one bit of information is stored in one memory cell.
The present invention relates to an EEPROM for performing multi-value storage. [0002] 2. Description of the Related Art As one of EEPROMs, high integration is required.
Possible NAND EEPROMs are known. this
Has multiple memory cells next to their source and drain
Connected in series so that they are in common with each other
It is connected to a bit line. Memory cells are usually
FETMOS structure with load storage layer and control gate stacked
Have. The memory cell array is on a p-type substrate or n-type substrate
It is integrated and formed in the formed p-type well. NAND cell
The drain side of the device is connected to the bit line through the select gate.
The source side is also connected to the common source line via the select gate.
Connected to. The control gates of the memory cells are connected in the row direction.
They are arranged successively to form word lines. Operation of this NAND cell type EEPROM
Is as follows. Write data from the bit line
This is performed in order from the memory cell at the farthest position. chosen
The high voltage Vpp (= about 20 V) is applied to the control gate of the memory cell.
Degrees), and the memory cells on the bit line side
The intermediate voltage Vppm (= 1) is applied to the control gate and the selection gate.
0V) and apply 0V to the bit line according to the data.
Alternatively, an intermediate voltage Vm (= about 8 V) is applied. Bit line
When 0 V is applied, the potential is changed to the drain of the selected memory cell.
, And electron injection occurs in the charge storage layer.
As a result, the threshold value of the selected memory cell becomes positive.
Shift to This state is, for example, “1”. bit
When Vm is applied to the line, electron injection occurs effectively.
Therefore, the threshold value does not change and remains negative. This state
Is "0" in the erased state. Data writing is performed by the control
This is performed simultaneously for memory cells sharing the same data. [0004] Data erasing is performed on all the memories in the NAND cell.
This is done simultaneously for the molycelles. That is, all control games
And the p-type well is set to 20V. At this time
The selection gate, bit line and source line are also set to 20V. this
As a result, the electrons in the charge storage layer are p-type
And the threshold shifts in the negative direction. [0005] Data is read from a selected memory cell.
Control gate of 0V, and control of other memory cells
The gate and the selection gate are connected to the power supply potential Vcc (for example, 5 V)
To detect whether a current flows in the selected memory cell.
It is done by doing. Due to the restriction of the read operation, "1" write
The later threshold value must be controlled between 0 V and Vcc.
No. Therefore, the write verify is performed, and "1"
Detects only memory cells with insufficient writing and writes "1"
Rewrite is performed only for memory cells that are insufficient
Set the rewrite data (bit-by-bit
I). The memory cell for which “1” write is insufficient is selected
Set the control gate to, for example, 0.5 V (verify voltage)
It is detected by reading (verify reading). That is, when the threshold voltage of the memory cell is
With margin and not more than 0.5V
Current flows in the selected memory cell and "1" writing is insufficient
Is detected. A memory cell to be set to “0” write state
Since the current naturally flows, this memory cell
Current through the memory cell so that it is not mistaken for
A circuit called a verify circuit is provided to compensate for
You. This verify circuit enables fast write verify
The run is executed. The write operation and the write verify are repeated.
By writing data while returning, individual memory
Optimized write time for cell, write "1"
The threshold value is controlled between 0 V and Vcc. In this NAND cell type EEPROM, multi-valued
To realize storage, for example,
It is considered that there are three, "0", "1", and "2".
In the “0” write state, the threshold is negative, and the “1” write state
The state is such that the threshold value is, for example, 0 V to 1/2 Vcc, and "2" is written.
The threshold voltage is from 1/2 Vcc to Vcc.
I do. In the conventional verify circuit, the "0" write state
Memory cells to be written with “1” or “2”
It can be prevented from being mistaken as a memory cell. However, the conventional verify circuit has many
Memory for writing "2" because it is not for value storage
Check whether the threshold value of the cell is insufficient for writing “1”.
ベ リ Vcc or more but higher than the verify voltage for detection
If the status is insufficient writing, "1" is insufficient writing
No current flows in the memory cell when writing is detected
There was a drawback that it was mistaken as sufficient. Further, it is possible to prevent a mistake
"1" write enough to perform write verify
Put "2" write state in the memory cell
Rewrite is performed on the memory cell, and “2” write is insufficient.
And verify verify write
What should I do? However, in this case, writing "2"
After writing "1" to the memory cell to be set,
It takes time to write because "2" is written.
The writing speed becomes slower. [0012] As described above, the conventional N
Multi-value storage in an AND cell type EEPROM
Attempting to perform bit-by-bit verification with a phi circuit
There is a problem that verification occurs.In addition, ternary
When a memory cell is used, binary input data is converted to ternary input data.
Complicated processing was required to write to the molycell
Memory cells cannot be used effectively.
Was. The present invention has been made in view of the above circumstances.
So, the purpose is,Uses ternary memory cells
Requires complex processing for binary input data
Data can be written without
Effective use of resellProvide a measurable EEPROM
It is in. [0014] [MEANS FOR SOLVING THE PROBLEMS]
The present invention employs the following configuration. That is, the present invention relates to a nonvolatile semiconductor memory device.
The first, second, and third
22 memory cells capable of having a storage state are 11
Pairs, each of 10 pairs of the 11 pairs being 3
And the other pair stores 2 bits
And storing 32-bit data in the 11 pairs.
Features. [0016] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
This will be described according to the form. (First Embodiment) FIG. 1 shows a first embodiment of the present invention.
Of NAND cell type EEPROM according to the first embodiment
FIG. 3 is a block diagram illustrating a configuration. A read / write operation is performed on the memory cell array 1.
Bit line control circuit for controlling bit lines during writing
Path 2 and a word line driving circuit for controlling the word line potential.
A road 7 is provided. Bit line control circuit 2, word line drive
The circuit 7 has a column decoder 3 and a row decoder 3, respectively.
Selected by the user 8. The bit line control circuit 2
Input / output data conversion circuit 5 via data input / output line (IO line)
And read data / write data are exchanged.
The input / output data conversion circuit 5 converts the read memory cell
Convert multi-valued information to binary information for output to the outside,
The binary information of the write data input from the memory cell
Is converted to multi-valued information. The input / output data conversion circuit 5 is
Data input / output buffer 6 for controlling data input / output with the unit
Connected to. The data write end detection circuit 4
It detects whether the writing is completed. FIGS. 2 and 3 show the memory cell array 1 and the bit.
3 shows a specific configuration of the line control circuit 2. Memory cell
M1 to M8 and select transistors S1 and S2, NAN
Construct a D-type cell. One end of the NAND cell is a bit line
BL, and the other end is connected to a common source line Vs.
You. Select gates SG1 and SG2, control gates CG1 to CG
G8 is shared by a plurality of NAND cells, and one control
The memory cells sharing the control gate form a page. Me
The memory cell stores data at the threshold value Vt,
When the voltage is 0 V or less, "0" data, and when Vt is 0 V or more.
"1" data when 5V or less, Vt is 1.5V or more
If the voltage is lower than the voltage, the data is stored as "2" data. One method
A memory cell has three states and two memory cells have nine states.
There are different combinations. Of these, 8 combinations
Data of 3 bits with two memory cells
Remember. In this embodiment, the neighbors sharing the control gate
Stores 3-bit data in a set of two matching memory cells
I do. The memory cell array 1 is placed on a dedicated p-well.
Is formed. Clock synchronous inverters CI1 and CI2
, CI3 and CI4 form flip-flops respectively
Then, the write / read data is latched. Also,
They also operate as sense amplifiers. Clock synchronization
Flip-flop composed of inverters CI1 and CI2
Rops, "write" 0 "," 1 "or
“Do you want to write 2”?
And the memory cell holds "0" information.
Or holds the information of “1” or “2” ”
Latch as read data information. Clock synchronous
Flip flow composed of inverters CI3 and CI4
The tip is “Write“ 1 ”or Write“ 2 ”.
Do you want to
The resell indicates whether "2" is held, "0" or
"Does the information of" 1 "hold?"
Latch as information. Among the n-channel MOS transistors, Q
n1 is a voltage when the precharge signal PRE becomes "H".
Transfer VPR to the bit line. Qn2 is the bit line connection signal
Signal BLC goes to "H" and bit line and main bit line control
Connect control circuit. Qn3 to Qn6, Qn9 to Qn12
Is the data latched on the flip-flop
Voltage VBLH, VBLM, VBLL are selectively selected according to the
Transfer to the transmission line. Qn7 and Qn8 are signals SA, respectively.
When C2 and SAC1 become "H", flip-flop
And the bit line. Qn13 is flip-flop
Whether all the data for one page latched in the
It is provided in order to detect whether or not it is. Qn14, Qn15 and Q
n16 and Qn17 are column selection signals CSL1 and CS, respectively.
L2 becomes "H", and the corresponding flip-flop
Data input / output lines IOA and IOB are selectively connected. In FIG. 3, the inverter part is shown in FIG.
It is abbreviated as shown in FIG. 9 (a).
The circuit configuration is as shown in FIG. Next, the EEPROM constructed as described above will be described.
Will be described with reference to FIGS. Figure 4 is a read
Operation timing, FIG. 5 shows a write operation timing,
FIG. 6 shows the timing of the verify read operation.
You. In each case, the case where the control gate CG4 is selected is taken as an example.
Is shown. The read operation is performed in two basic cycles.
Is performed. In the first read cycle, first, the voltage VPR is applied.
When the source voltage becomes Vcc, the bit line is precharged and precharged.
The charge signal PRE becomes “L” and the bit line flows.
It is made to be Subsequently, select gates SG1, SG2
 , Control gates CG1 to CG3, CG5 to CG8 are Vcc
It is said. At the same time, the control gate CG4 is set to 1.5V.
You. When the Vt of the selected memory cell is 1.5 V or more
Only when data “2” is written
Only, the bit line is kept at "H" level. Thereafter, sense activation signals SEN2, SE
N2B is "L" and "H" respectively, and the latch activation signal LA
T2 and LAT2B become "L" and "H", respectively.
A lock synchronous inverter CI3 and CI4
The lip flop is reset. The signal SAC2 is
It becomes "H" and the clock synchronous inverters CI3 and CI
The flip-flop consisting of 4 and the bit line are connected.
First, the sense activation signals SEN2 and SEN2B
To “H” and “L”, and the bit line potential is sensed.
Thereafter, the latch activation signals LAT2 and LAT2B are
"H" and "L", and the clock synchronous inverter CI
3 and CI4 flip flop,
The information of “whether“ 2 ”data, 1” or “0” data is
Latched. The second read cycle is the first read cycle.
And the voltage of the selection control gate CG4 is not 1.5V
0 V, the signals SEN2, SEN2B, LAT2,
Instead of LAT2B and SAC2, signals SEN1 and SEN1
B, LAT1, LAT1B, SAC1 may be output
Wrong. Therefore, in the second read cycle, the clock is synchronized.
Flip-flop composed of the inverters CI1 and CI2
In the flop, “0” data, “1” or “2” data
Information is latched. According to the two read cycles described above,
Therefore, the data written in the memory cell is read out.
You. Prior to data writing, the memory cell data
Data is erased, and the threshold value Vt of the memory cell is 0 V or less.
It has become. Erase is performed on the p-well, common source line Vs,
The selection gates SG1 and SG2 are set to 20V and the control gate CG
1 to CG8 are set to 0V. In a write operation, first, a precharge signal
PRE goes to “L” and the bit line floats.
It is. The selection gate SG1 is at Vcc and the control gates CG1 to CG
G8 is set to Vcc. Select gate SG2 is write operation
Medium 0V. At the same time, the signals VRFY1, VRFY2,
FIM and FIH become Vcc. When writing "0"
Is composed of clock synchronous inverters CI1 and CI2.
Clock flip-flop
The data is latched so that the output of CI1 becomes "H".
Therefore, the bit line is charged by Vcc. “1”
Alternatively, in the case of "2" write, the bit line is at 0V. Subsequently, the selection gate SG1 and the control gate C
G1 to CG8, signal BLC, signal VRFY1 and voltage VS
A is 10V, voltage VBLH is 8V, and voltage VBLM is 1V.
You. In case of “1” writing, clock synchronous
Flip-flop composed of data CI3 and CI4
The output of the clock synchronous inverter CI3 becomes "H".
Data is latched as shown in FIG.
Is applied with 1V. Bit line for "2" write
Is 0V, and 8V in the case of "0" writing. After this,
The selected control gate CG4 is set to 20V. In the case of "1" or "2" write,
Electrons are generated due to the potential difference between the scanning line BL and the control gate CG4.
Injected into the charge storage layer of the memory cell, the threshold of the memory cell
The value rises. If "1" is written, write "2"
Charge to be injected into the charge storage layer of the memory cell
Since the amount must be reduced, the bit line BL is set to 1
V to reduce the potential difference with the control gate CG4 to 19V.
ing. However, it is possible to implement without easing the potential difference.
is there. At the time of writing “0”, the bit line voltage 8V
The threshold of the memory cell does not change effectively. At the end of the write operation, first, select gate
SG1, the control gates CG1 to CG8 are set to 0V, and "0"
The voltage 8V of the bit line BL at the time of writing is reset to 0V with a delay.
Set. When this order is reversed, it temporarily becomes “2” or
Is ready for "1" write operation, and "0" write
This is because sometimes wrong data is written. After the write operation, writing of the memory cells
Check the status and additionally write only to memory cells with insufficient writing
Verify read is performed to perform the write operation. Beli
During the file read, the voltage VBLH is Vcc and VBLL is 0.
V and FIM are 0V. The verify read is performed in two basic cycles.
Run from the This basic cycle is the second read
Similar to Icle. The difference is that the selected control gate C
The voltage of G4 and the signals VRFY1, VRFY2 and FIH are
(Verify read first cycle)
Only VRFY1). Signals VRFY1, VRFY2
 , FIH are select gates SG1, SG2, control gates
After CG1 to CG8 are reset to 0V, the signal SEN
1, SEN1B, LAT1, LAT1B are “L”,
It is output before it becomes “H”, “L”, or “H”. Paraphrase
The bit line potential depends on the threshold voltage of the memory cell.
After the determination, the clock synchronous inverters CI1 and C1
The flip-flop composed of I2 is reset
Before. The voltage of the selected control gate CG4 is read
1.5V (first cycle), 0V (second cycle)
2V (first cycle), 0.5V (first cycle)
2 cycles) and a threshold margin of 0.5 V
It is raised to be high. Here, the clock synchronous inverter CI
1 and CI2.
Data (data1), clock synchronous type
Flip-flop composed of data CI3 and CI4
The latched data (data2) and the selected
Voltage of bit line BL determined by threshold of memory cell
Will be described. data1 is “0” write or “1”
Or “2” write ”, and write“ 0 ”
Qn3 is in "ON" state, "1" or "2" is written
In this case, Qn6 is in the "ON" state. data2 is
"Whether" 1 "write or" 2 "write"
In the case of "1" write, Qn10 is in "ON" state, "2"
In the case of writing, Qn11 is in the "ON" state. When writing "0" data (initial write data)
Data is “0”) in the first cycle of verify read
Since the data of the memory cell is "0",
When CG4 becomes 2V, the bit line power is turned on by the memory cell.
The order becomes “L”. Thereafter, the signal VRFY1 becomes "H".
As a result, the bit line BL becomes “H”. When writing "1" data (initial write data)
Data is “1”) in the first cycle of verify read
Is because the data in the memory cell should be "1"
The threshold value of the memory cell is 1.5 V or less, and the control gate C
When G4 becomes 2V, the bit line potential is changed depending on the memory cell.
It becomes “L”. After that, the signal VRFY1 becomes "H".
Then, "1" is already written enough and data1 is written "0".
Bit line BL is "H" (see FIG. 6).
(1)), otherwise, the bit line BL is "L" ((2) in FIG. 6).
 ). When writing "2" data (initial write data)
Data is “2”) in the first cycle of verify read
Indicates that the data of the selected memory cell is not "2"
(“2” write insufficient), the control gate CG4
When the potential becomes V, the bit line potential becomes “L” depending on the memory cell.
((5) in FIG. 6). Selected memory cell is "2" written
If it is, the control gate CG4 becomes 2V.
However, the bit line potential remains "H" ((3) in FIG. 6).
(Four)). (3) of FIG.
This is the case where a1 indicates “0” writing. This place
In this case, the signal VRFY1 changes to "H",
Therefore, the bit line BL is recharged. When writing "0" data (initial write data)
Data is “0”) in the second verify read cycle.
Since the data of the memory cell is "0",
When CG4 becomes 0.5V, a bit
The line potential becomes "L". Then, the signal VRFY1 is
When the bit line BL becomes “H”, the bit line BL becomes “H”. When writing "1" data (initial write data)
Data is “1”) in the second cycle of verify read
Indicates that the data of the selected memory cell is not "1"
(“1” write insufficient), the control gate CG4
When the voltage reaches 0.5 V, the bit line potential varies depending on the memory cell.
It becomes "L" ((8) in FIG. 6). Selected memory cell is "1"
When writing is sufficient, the control gate CG4
Even if the voltage reaches 0.5 V, the bit line potential remains at "H"
((6) (7) in FIG. 6). FIG. 6 (6) shows that “1” has already been written.
Minutes when data1 indicates “0” write.
You. In this case, when the signal VRFY1 becomes "H",
The bit line BL is recharged by the voltage VBH. When writing "2" data (initial write data)
Data is “2”) in the verify read second cycle
Is because the data in the memory cell should be "2"
If the threshold value of the memory cell is 0.5 V or more, write "2".
Control gate CG4 is 0.5
V, the bit line potential remains "H" (FIG. 6).
(9) (10)). "2" Insufficient writing and memory cell
When the threshold value is 0.5 V or less, the bit line becomes "L".
((11) in FIG. 6). Thereafter, the signals VRFY1, VRFY2, F
Since IH becomes “H”, “2” is already sufficiently written.
Bit line when data1 indicates "0" write
BL is "H" ((9) in FIG. 6), otherwise the bit line BL
Becomes "L" ((10) (11) in FIG. 6). By this verify read operation, the write
Rewrite from write data and write state of memory cell
Data is set as shown in (Table 1) below. [0044] [Table 1] As can be seen from (Table 1), "1" is written.
"1" is written again only for the memory cells that are insufficient,
"2" is written again only to the memory cell where "2" is insufficiently written.
Is included. Also, all memory
When the cell has enough data to write,
Qn13 is turned "OFF" and the signal PENDB
Data write end information is output. FIG. 7 shows the data input / output operation timing.
(A) is a data input timing, (b) is a data input timing.
Data output timing. External data input 3
After the cycle, the input / output data conversion circuit 5
Data to be input to the line control circuit 2 is generated and input.
3-bit data from outside (X1, X2, X3)
Is converted into data (Y1, Y2) of two memory cells.
In effect, the clock synchronous type of the bit line control circuit 2 is
Registers R1 and C composed of inverters CI1 and CI2
Data input / output to / from register R2 composed of I3 and CI4
Conversion data is set via the force lines IOA and IOB.
Read data latched in registers R1 and R2
Is input / output data via data input / output lines IOA and IOB.
The data is transferred to the data conversion circuit 5, converted, and output. In FIG.
The same column selection signals CSL1i and CSL2i
Instead, split IOA and IOB into two systems
You can access two registers in one column at the same time
Easily possible and effective for reducing access time
It is. The following (Table 2) shows whether data is input externally.
These three bits of data (X1, X2, X3), memory
Two cell data (Y1, Y2) and Y1, Y2
The relationship between the data in the registers R1 and R2 corresponding to
ing. [0048] [Table 2]Register data is input / output during data transfer.
It is represented by the voltage level of the line IOA. Data input / output line
IOB is omitted because it is an inverted signal of IOA. under
The above (Table 3) is that at the time of data output. [0050] [Table 3] In this embodiment, the same data is input
The IOA level at the time of output and the IOA level at the time of output are inverted
It is supposed to. The two data (Y1, Y2) of the memory cell
Since one of the nine combinations is left over,
Can be used for file management information such as pointer information
Noh. Here, the pointer information is stored in the cell data (Y1,
Y2) = (2,2). FIG. 8 controls the EEPROM.
Write data as seen from microprocessor etc.
It shows the concept of a page, which is the only unit. Here 1
Page is N bytes, microprocessor, etc.
Displays the address (logical address) as viewed from
You. For example, only area 1 (logical addresses 0 to n) is written.
When no writing data is input, n = 3m + 2 (m = 3m + 2)
0, 1, 2, ...), (X1, X2, X3) is always
There is no problem because they are aligned. If n = 3m, only X1 is input
X2 = 0, X3 = 0 inside EEPROM
And (X1, X2, X3) are converted into an input / output data conversion circuit 5.
To enter. When n = 3m + 1, X3 = 0 is issued internally
Live. The same applies when n is equal to N. Data was written to area 1 (area 2
All the write data of “0”) is added to the area 2 after
When writing data, read the area 1
Add the write data of area 2 to that data
Just enter it. Alternatively, read the portion of area 1 and
If the start address of the area 2 is n + 1 = 3 m, the data of the area 1
Data is all "0", n + 1 = 3m + 2, address n
-1 and n are defined as X1 and X2,
In addition to data X3, the data up to address n-2 in area 1
Data are all "0", and n + 1 = 3m + 1.
Assuming that the data is X1, the data X at addresses n + 1 and n + 2
2, data up to address n-1 of area 1 in addition to X3
May be all set to “0”. These operations are based on the EEP
It is also easy to perform this automatically inside the ROM. This addition
(Table 2) and (Table 2) so that data can be written.
As shown in (3), (X1, X2, X3) and (Y1
 , Y2) are established. (Table 2) and (Table
(X1, X2, X3) and (Y1, Y2) shown in FIG.
 ) Is an example and is not limited to this.
No. Similarly, additional data is written even if the area is 3 or more.
Can be done. FIG. 9A shows a data write algorithm.
Is shown. After loading data, write and verify
B) The read and write completion detection operations are repeated
You. The operation within the dotted line is performed automatically in the EEPROM. FIG. 9B shows an additional data writing algorithm.
Shows rhythm. After reading and loading data, verify
File read / write completion detection and write operation are repeated.
It is done repeatedly. Automatically in the EEPROM inside the dotted line
Done. Verify read after data load
Is that "1" or "2" has already been written
However, this is to prevent writing.
Otherwise, overwriting may occur. FIG. 10 shows the EEPR constructed as described above.
OM shows the write characteristics of the threshold value of the memory cell.
ing. A memory cell to which "1" data is written
Memory cells to which "2" data is written are written simultaneously
And write time is controlled independently.
You. The following (Table 4) shows erasing, writing, and reading.
Read and verify read operations of each part of the memory cell array.
Indicates potential. [0059] [Table 4] (Second Embodiment) FIG. 11 shows a second embodiment of the present invention.
Of the NOR cell type EEPROM in the second embodiment.
Specific configuration of memory cell array 1 and bit line control circuit 2
Is shown. A NOR type cell is formed only by the memory cell M10.
Constitute. One end of the NOR type cell is connected to the bit line BL.
And the other end is connected to a common ground line. One control gate
The memory cells M sharing the WL constitute a page. Note
Recell M stores data at its threshold Vt,
1. When the voltage is equal to or higher than Vcc, "0" data;
"1" data when 5 V or more, Vt is 2.5 V or less 0 V
In the above case, it is stored as "2" data. One memory
Cell has 3 states, 2 memory cells have 9 states
Can be combined. Of these, eight combinations
Uses two memory cells to store 3-bit data
I do. In this embodiment, neighboring control gates share
3-bit data is stored in a set of two memory cells
You. Clock synchronous inverters CI5 and CI6
, CI7 and CI8 form flip-flops respectively
Then, the write / read data is latched. Also,
Also works as a sense amplifier. Clock synchronous invar
Flop composed of data CI5 and CI6
Is “write“ 0 ”or write“ 1 ”or“ 2 ”
Or write as the write data information
And whether the memory cell holds the information “0”
"Does information" 1 "or" 2 "hold?"
And latch it as data information. Clock synchronous invar
Flop composed of data CI7 and CI8
Is "write" 1 "or write" 2 "
Is latched as write data information.
Is "2", "0" or
"Does the information of" 1 "hold?"
Latch as information. Of the n-channel MOS transistors, Qn
18 is a voltage V when the precharge signal PRE becomes “H”.
Transfer PR to bit line. Qn19 is a bit line connection signal
BLC becomes "H" and bit line and main bit line control
Connect the circuit. Qn20 to Qn23 and Qn25 to Qn28 are
The data latched in the flip-flop described above
In response, the voltages VBLH, VBLM, and 0 V are selectively applied to the bit lines.
Transfer to Qn24 and Q29 are signals SAC2 and SAC, respectively.
When AC1 becomes “H”, flip-flop and bit
Connect the cable. Qn30 is a flip flop
Check whether all the data of one touched page is the same.
Provided to get out. Qn31, Qn32 and Qn33, Q
n34 is a column selection signal CSL1 or CSL2, respectively.
"H", corresponding flip-flop and data
The input / output lines IOA and IOB are selectively connected. Next, the EEPROM constructed as described above will be described.
Will be described with reference to FIGS. Figure 12 shows the reading
FIG. 13 shows the timing of the write operation.
FIG. 14 shows the timing of the verify read operation.
Is shown. The read operation is performed in two basic cycles.
Is performed. In the first read cycle, first, the voltage VPR is applied.
When the source voltage becomes Vcc, the bit line is precharged and precharged.
The charge signal PRE becomes “L” and the bit line flows.
It is made to be Subsequently, the control gate WL is set to 2.5 V
To be. Vt of selected memory cell is 2.5V or less
Only when the data “2” is written
Only in this case, the bit line goes to "L" level. Thereafter, sense activation signals SEN2, SE
N2B is "L" and "H" respectively, and the latch activation signal LA
T2 and LAT2B become "L" and "H", respectively.
Lock synchronous inverters CI7 and CI8
The lip flop is reset. The signal SAC2 is
Becomes "H" and the clock synchronous inverters CI7 and CI
The flip-flop consisting of 8 and the bit line are connected.
First, the sense activation signals SEN2 and SEN2B
To “H” and “L”, and the bit line potential is sensed.
Thereafter, the latch activation signals LAT2 and LAT2B are
"H" and "L", and the clock synchronous inverter CI
7 and CI8 flip-flop,
Information of "whether it is" 2 "data," 1 "or" 0 "data"
Is latched. The second read cycle is the first read cycle.
And the voltage of the selection control gate WL is V instead of 2.5 V
cc, the signals SEN2, SEN2B, LAT2, L
Instead of AT2B and SAC2, signals SEN1, SEN1B,
It is incorrect that LAT1, LAT1B, and SAC1 are output.
U. Therefore, in the second read cycle, the clock synchronization
Flip-flop composed of inverters CI5 and CI6
"0" data, "1" or "2" data
Is latched. According to the two read cycles described above,
Therefore, the data written in the memory cell is read out.
You. Before writing data, the data in the memory cell
Data is erased, and the threshold value Vt of the memory cell is higher than Vcc.
It has become. For erasing, the control gate WL is set to 20 V and
This is performed by setting the cut line to 0V. In the write operation, first, the precharge signal
PRE goes to “L” and the bit line floats.
It is. The signals VRFY1, VRFY2, FIM and FIL are
Vcc. In case of “2” write, clock synchronous type
Flip flow composed of inverters CI5 and CI6
Output of the clock synchronous inverter CI5
Since data is latched so as to become “H”,
The cut line is at 0V. When writing "1" or "2"
The bit line is charged to Vcc. Subsequently, the signals BLC, VRFY2, FI
M, FIL and voltage VSA are 10V, voltage VBLH is 8V,
The pressure VBLM becomes 7V. When writing “1”,
Of the clock synchronous inverters CI7 and CI8.
In the flip-flop, the clock synchronous inverter CI7
Data is latched so that the output becomes "H".
Therefore, 7 V is applied to the bit line BL. Write "2"
The bit line is 8 V in the case of only writing and 0 in the case of "0" writing.
V. After this, the selected control gate WL becomes -12
V. In the case of "1" or "2" write,
The electrons are recorded by the potential difference between the scanning line BL and the control gate WL.
Emitted from the charge storage layer of the recell and the threshold of the memory cell
Values fall. If "1" is written, write "2"
Charge to be discharged from the charge storage layer of the memory cell
Since the load must be reduced, the bit line BL
7V to reduce the potential difference with the control gate WL to 19V
ing. When writing “0”, the bit line voltage is 0V.
Therefore, the threshold value of the memory cell does not change effectively. After the write operation, the write operation of the memory cell is performed.
Check the status and additionally write only to memory cells with insufficient writing
Verify read is performed to perform the write operation. Beli
During the file read, the voltage VBLH is Vcc and FIM is 0V
It is. Verify reading is performed in two basic cycles.
Run from the This basic cycle is the first read cycle.
Similar to Icle. The difference is that the selected control gate W
L voltage and signals VRFY1, VRFY2 and FIH are output.
(Verify read first cycle
Then only VRFY1). The signals VRFY1, VRFY2,
FIH occurs after the control gate WL is reset to 0V.
The signals SEN1, SEN1B, LAT1, LAT1B are respectively
Output before it becomes “L”, “H”, “L”, “H”.
You. In other words, the potential of the bit line is
After the value is determined by the clock synchronous inverter
The flip-flop composed of CI5 and CI6 is reset.
Before it is set. The voltage of the selected control gate WL
Are 2.5V (first cycle) and Vcc (second
2V (first cycle), 4V
(Second cycle) and to secure the threshold margin
Lower. Here, the clock synchronous inverter CI
5 and CI6
Data (data1), clock synchronous type
Flip-flop composed of data CI7 and CI8
The latched data (data2) and the selected
Voltage of bit line BL determined by threshold of memory cell
Will be described. data1 is “0” write or “1”
Or “2” write ”, and write“ 0 ”
Qn20 is "ON" state, "1" or "2" is written
In this case, Qn23 is in the "ON" state. data2 is
"Whether" 1 "write or" 2 "write"
In the case of "1" write, Qn26 is in "ON" state, "2"
In the case of writing, Qn27 is in the "ON" state. When writing "0" data (initial write data)
Data is “0”) in the first cycle of verify read
Since the data of the memory cell is "0",
The bit line potential remains at “H” even when the WL becomes 2V.
is there. After that, when the signal VRFY1 becomes “H”, the bit
The gate line BL becomes "L". When writing "1" data (initial write data)
Data is “1”) in the first cycle of verify read
Is because the data in the memory cell should be "1"
The threshold value of the memory cell is 2.5 V or more and the control gate W
Even if L becomes 2V, the bit line potential remains "H".
You. After that, when the signal VRFY1 becomes “H”,
“1” write is sufficient and data1 indicates “0” write
In this case, the bit line BL goes low ((2) in FIG. 14),
Otherwise, the bit line BL becomes "H" ((1) in FIG. 14).
You. When writing "2" data (initial write data)
Data is “2”) in the first cycle of verify read
Indicates that the data of the selected memory cell is not "2"
(“2” write insufficient), the control gate WL is set to 2V
, The bit line potential is still "H" ((3) in FIG. 14).
 ). The selected memory cell is sufficient to write "2"
When the control gate WL becomes 2V, the bit line potential becomes
It becomes "L" by the memory cell ((4) (5) in FIG. 14).
FIG. 14 (5) shows that “2” has already been sufficiently written and data1 is
This is a case where "0" writing is indicated. In this case,
When the signal VRFY1 becomes “H”, the bit line BL is connected.
Ground. When writing "0" data (initial write data)
Data is “0”) in the second verify read cycle.
Since the data of the memory cell is "0",
The bit line potential is still "H" even when CG4 goes to 4V.
You. Thereafter, when the signal VRFY1 becomes “H”, the bit
The gate line BL becomes "L". When "1" data is written (initial write data
Data is “1”) in the second cycle of verify read
Indicates that the data of the selected memory cell is not "1"
(“1” write insufficient), the control gate WL is set to 4V
, The bit line potential is still "H" ((6) in FIG. 14).
 ). The selected memory cell is sufficient to write "1"
Memory cell when the control gate WL becomes 4V.
The bit line potential becomes "L" ((7) and (8) in FIG. 14). Figure
In (8) of 14, already writing "1" is enough and data1 is
This is a case where "0" writing is indicated. In this case,
When the signal VRFY1 becomes “H”, the bit line BL is connected.
Ground. When "2" data is written (initial write data
Data is “2”) in the verify read second cycle
Is because the data in the memory cell should be "2"
Write "2" if the threshold of the memory cell is 4V or less
When the control gate WL becomes 4 V, whether it is enough or not enough
The bit line potential becomes “L” ((10) and (11) in FIG. 14).
"2" Insufficient write and threshold of memory cell is 4V or less
In the above case, the bit line becomes "H" ((9) in FIG. 14). Thereafter, the signals VRFY1, VRFY2, F
Since IH becomes “H”, “2” is already sufficiently written.
Bit line when data1 indicates "0" write
BL is “L” ((11) in FIG. 14), otherwise bit line B
L becomes "H" ((9) (10) in FIG. 14). This verify read operation allows writing to be performed.
Rewrite from write data and write state of memory cell
Data is set as shown in Table 1 as in the first embodiment.
Is done. In addition, data writing is sufficient for all memory cells.
Minutes, Qn30 of all columns is turned off.
The signal PENDB indicates that the data write end information is
Is output. Data input / output operation timing, data writing
Writing algorithm, additional data writing algorithm
Are the first as shown in FIGS. 7 to 9 and (Tables 2 to 3).
This is the same as the embodiment. FIG. 15 shows the EEPR constructed as described above.
OM shows the write characteristics of the threshold value of the memory cell.
ing. A memory cell to which "1" data is written
Memory cells to which "2" data is written are written simultaneously
And write time is controlled independently.
You. The following (Table 5) shows erasing, writing, and reading.
Read and verify read operations of each part of the memory cell array.
The potential is shown. [0086] [Table 5] The circuits shown in FIG. 3 and FIG.
It can be deformed as shown in FIGS. FIG. 16 shows FIG.
The observed Qn3 and Qn4 are connected to p-channel MOS transistors.
Stars Qp1 and Qp2 have been replaced. FIG.
Qn22, Qn23, Qn25 to Qn28 found in
Np MOS transistors Qp3 to Qp8
is there. By doing so, the n-channel MOS transistor
It is necessary to prevent the transferable voltage from dropping due to the transistor threshold.
In this example, the voltage VSA is increased to 8 V during writing.
The breakdown voltage of the transistors that make up the circuit can be lowered.
I can do it. VRFY1B in FIG. 16 is VRFY in FIGS.
The inverted signal of RFY1, VRFY2B, FILB,
FIMB is that of VRFY2, FIL, FIM in FIG.
Each is an inverted signal. FIG. 8 explains additional data writing.
However, for example, as shown in FIG.
One page may be divided for ease of use.
This is an effective method. In this example, every 32 logical addresses
One region is constituted by 22 memory cells. By this
This makes it easy to write additional data in area units. Toes
When writing additional data to area 2
Assuming that all the write data in the area of FIG.
According to the data writing algorithm found in (a)
Just do it. [0089] As described above, according to the present invention,3
For binary input data, using a memory cell of value
Data can be written without complicated processing.
And memory cells can be used effectivelyEEPRO
M can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an EEPROM according to first and second embodiments.
FIG. 2 is a block diagram showing a schematic configuration of FIG. FIG. 2 is a diagram showing a specific configuration of a memory cell array according to the first embodiment. FIG. 3 is a diagram showing a specific configuration of a bit line control circuit according to the first embodiment. FIG. 4 is a timing chart showing a read operation in the first embodiment. FIG. 5 is a timing chart showing a write operation in the first embodiment. FIG. 6 is a timing chart showing a verify read operation according to the first embodiment; FIG. 7 is a timing chart showing a data input / output operation in the first and second embodiments. FIG. 8 is a view showing the concept of a page of a write / read unit in the first and second embodiments. FIG. 9 is a diagram showing a data write and additional data write algorithm in the first and second embodiments. FIG. 10 is a diagram showing write characteristics of a memory cell in the first embodiment. FIG. 11 is a diagram showing a configuration of a memory cell array and a bit line control circuit according to the second embodiment. FIG. 12 is a timing chart showing a read operation in the second embodiment. FIG. 13 is a timing chart showing a write operation in the second embodiment. FIG. 14 is a timing chart showing a verify read operation in the second embodiment. FIG. 15 is a diagram showing write characteristics of a memory cell according to the second embodiment. FIG. 16 is a diagram showing a modification of the bit line control circuit according to the first embodiment. FIG. 17 is a diagram showing a modification of the bit line control circuit according to the second embodiment. FIG. 18 is a diagram showing a unit of additional data writing in the first and second embodiments. FIG. 19 is a diagram showing a specific configuration example of an inverter section shown in FIG. 3; [Description of Signs] 1 ... memory cell array 2 ... bit line control circuit 3 ... column decoder 4 ... data write end detection circuit 5 ... input / output data conversion circuit 6 ... data input / output buffer 7 ... word line drive circuit 8 ... row decoder

Claims (1)

(57) Claims 1. Twenty-two memory cells which can be electrically rewritten and have first, second, and third storage states are provided.
Two pairs constitute one pair to form 11 pairs, and one of the 11 pairs
Each of the 0 pairs stores 3 bits of data, and the remaining 1
A nonvolatile semiconductor memory device, wherein a pair stores 2 bits and the 11 pairs store 32-bit data.