JP3473297B2 - Method for forming silicon oxide film and method for manufacturing thin film transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a method for forming a silicon oxide film and a method for manufacturing a thin film transistor.

[0002]

2. Description of the Related Art As a method of manufacturing a TFT (TFT) used as an active element of a liquid crystal display panel, an inexpensive glass substrate can be used from the viewpoint of increasing the area and cost of the liquid crystal display panel. A low temperature process is required. In such a process, even if it is a low temperature process, it is necessary to be able to form a large grain size polysilicon film comparable to a high temperature process and to sufficiently activate impurities, and at the same time, a high quality film having a film quality equal to or higher than that of a thermal oxide film. It is also important to be able to form a high quality gate insulating film.

Conventional techniques for forming a gate insulating film (silicon oxide film) at a low temperature include atmospheric pressure CVD and reduced pressure C.
Although there are film forming methods such as VD and ECR-CVD, the atmospheric pressure CVD and the low pressure CVD have high productivity, but the quality of the TFT gate insulating film is poor. For example, there are problems that the space charge and the interface charge in the silicon oxide film increase, the on-current characteristics of the TFT deteriorate, the off-leakage current characteristics decrease, and the threshold voltage shifts. Further, although the film quality is relatively good in the ECR-CVD method,
There is a problem that productivity is extremely low, and none of the conventional film forming methods satisfy the requirements for forming a gate insulating film of a large area circuit element such as an active element of a liquid crystal display device.

As a low temperature process for forming a silicon oxide film, there is a plasma chemical vapor deposition method (hereinafter referred to as a plasma CVD method) in addition to the above film forming method. In the plasma CVD method, as shown in FIG. 10, a substrate 205 is arranged on a sample table 203 (lower plate electrode) in a vacuum container 202 of a plasma chemical vapor deposition apparatus, and an upper plate arranged opposite to the substrate 205. When the source gas is supplied into the vacuum container 202 by the electrode 204 and is applied to the upper flat plate electrode 204 through the oscillation source 213 (power source), the amplifier 214 and the matching circuit 215, plasma is generated and silicon is generated on the surface of the substrate 205. An oxide film is formed. At this time, the sample table 203 is heated by the heater 207 incorporated therein to heat the substrate 205 to a predetermined temperature. Such a plasma CVD method has advantages such as a high film formation rate, a small stress applied to the substrate 205, and a good step coverage. Therefore, the plasma CVD method has hitherto been used for forming an interlayer insulating film of a semiconductor integrated circuit. It is used. Therefore, it has been considered to apply the plasma CVD method also for forming a gate insulating film of a TFT in manufacturing an active matrix substrate of a liquid crystal display panel.

[0005]

However, the plasma CVD method has been studied variously by changing each parameter, but in the process of forming a gate insulating film of a TFT or the like on a substrate for an active matrix of a liquid crystal display panel. It has not been applied yet. The reason is that, unlike the case where a silicon oxide film is deposited on a relatively narrow substrate such as a silicon wafer, the film formation rate is higher when a gate insulating film of a TFT is formed on a substrate for active matrix. Not only are they high, the stress on the substrate is low, the step coverage is good, but there are additional requirements specific to this field. That is,
For active matrix, etc., 360 mm x 465 m
It is required that a silicon oxide film can be uniformly formed on the entire surface of a large substrate such as m.
This is because the requirement of film thickness uniformity cannot be satisfied only by applying the same film forming conditions using the film forming apparatus used for forming the interlayer insulating film of the semiconductor integrated circuit. Moreover, as long as it is formed as the gate insulating film of the TFT,
The electrical characteristics related to the space charge and the interface state of the silicon oxide film described above are also required to be good, but the same is true using the film forming apparatus used to form the interlayer insulating film of the semiconductor integrated circuit. This requirement cannot be met simply by applying the film forming conditions as they are. Moreover, such a tendency is that tetraethoxysilane (S
_{i- (O-CH 2 -CH 3} ) 4 / hereinafter referred to TEOS. ) Is remarkable. Therefore, it is considered that the plasma CVD method using TEOS cannot stably form the gate insulating film of the TFT.

Therefore, as a result of investigating the cause of the above-mentioned problems, an object of the present invention is to add a new condition to the plasma CVD method using TEOS so that the uniformity of the film thickness on a large-area substrate can be improved. It is to provide a high silicon oxide film and a method for manufacturing a TFT.

[0007]

In order to solve the above-mentioned problems, a method for forming a silicon thin film of the present invention is to place a substrate on a sample table in a vacuum container of a plasma chemical vapor deposition apparatus,
In a method for forming a silicon oxide film, wherein plasma is generated by supplying a raw material gas into the vacuum container by a flat plate electrode facing the substrate to form a silicon oxide film on the substrate, tetraethoxysilane is used as the raw material gas. Is used to heat the substrate and the plate electrode.

That is, in the method for producing a silicon oxide film according to the present invention, a substrate is placed on a sample table in a vacuum container of a plasma chemical vapor deposition apparatus, and the vacuum container is provided by a flat plate electrode facing the substrate. When TEOS is used as a source gas for supplying silicon when a plasma is generated while supplying a source gas to the inside to form a silicon oxide film by a plasma chemical vapor deposition method, and TEOS is used together with the substrate on the sample table. The flat plate electrode is also heated, and the heating is performed by a heater arranged so as to surround the sample stage and the flat plate electrode in the vacuum container.

Further, the heating of the flat plate electrode is performed by a heater built in the flat plate electrode.

[0010]

[0011]

The substrate and the plate electrode are heated to the same temperature.

In the present invention, it is preferable that the substrate and the plate electrode are heated to 200 ° C. or higher.

[0014]

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Before describing the embodiments of the present invention, the examination results up to the present invention will be described. In this study, even if the silicon oxide film is formed by the plasma CVD method using TEOS while directly applying the film forming conditions used for forming the interlayer insulating film of the semiconductor integrated circuit,
This is a study to investigate the reason why it is not possible to form a silicon film on a large-sized substrate with a uniform film thickness and electrical characteristics such as space charge and interface states. In this study, 36
After forming an amorphous silicon film on a 0 mm × 465 mm substrate, a polycrystalline silicon film is formed by the solid phase growth method, and TEOS is applied to the surface of the polycrystalline silicon film in a plasma CVD apparatus while changing the substrate temperature variously. A silicon oxide film is formed by using. The flow rate of TEOS is 120 SCCM, the flow rate of oxygen is 3000 SCCM,
The power of the RF power source was 900 W, the distance between the parallel plate electrodes was 12.7 mm, the pressure in the reaction chamber was 650 mTorr, and the substrate temperature during film formation was 284 ° C. to 334 ° C.
A silicon oxide film is formed by changing the temperature range up to ° C, and the substrate temperature and film formation characteristics (deposition rate, film thickness variation on the same substrate, ideal flat band voltage) Deviation) was evaluated.

FIG. 1 is a graph showing the relationship between the substrate temperature and the film formation rate when a silicon oxide film is formed by the plasma CVD method under the above conditions using TEOS gas, and FIG.
FIG. 3 is a graph showing the relationship between the substrate temperature and the variation in film thickness when a silicon oxide film is formed by the plasma CVD method under the above conditions using EOS gas. FIG. 6 is a graph showing a relationship between a substrate temperature when a silicon oxide film is formed and a deviation from an ideal flat band voltage.

As can be seen from these graphs, TEO
The plasma CVD method using S gas tends to have a significantly large temperature dependency such as a film forming rate as compared with other film forming methods, and accordingly, the substrate temperature is controlled as compared with other film forming methods. Can be said to be important.

In obtaining such data, the variation in film thickness was obtained by measuring the film thickness after film formation on a diagonal line in a region excluding 12 mm from the edge of the substrate, and obtaining the variation in film thickness by the following formula. It is represented by a value.

[0019]

[Equation 1]

The uniformity of the film thickness is preferably 7% or less from the viewpoint of suppressing variations in characteristics among TFTs. Further, from the viewpoint of improving the throughput, the higher the film forming rate, the more preferable, but about 700 angstroms / minute is an acceptable level. In addition, among the measured values relating to the film thickness, the white circles in the graph show the measurement results by the step difference measuring method, and the black circles show the measurement results by the ellipsometry.

Among the electrical characteristics of the silicon oxide film, the space potential in the film and the interfacial charge at the film interface are evaluated as the deviation from the ideal flat band voltage (ΔV _FB ). This value can be obtained by the following method.
First, a silicon oxide film is formed on a silicon wafer by a plasma CVD method, and then aluminum electrodes are formed in dots on the silicon oxide film. Next, the aluminum electrode and the silicon wafer are respectively connected to the electrodes to form a MOS capacitor, and thereafter, the deviation (ΔV _FB ) from the ideal flat band voltage is obtained from the capacitance-applied voltage characteristic. That is, ideally, when the bias voltage (gate voltage) corresponds to the contact potential difference between aluminum and silicon, a flat band occurs, but in an actual device, the existence of space charges in the oxide film and contact with the oxide film There is a deviation from an ideal flat band due to the presence of interface charges due to the interface states on the semiconductor surface. Therefore, if you measure the degree of such deviation,
The quality of the inside of the element when the TFT is configured can be estimated with high correlation. Here, if a silicon oxide film having a small absolute value (ΔV _FB ) from the ideal flat band voltage is used for the gate insulating film, the electrical characteristics of the TFT are good and the ideal flat band voltage When a silicon oxide film having a large absolute value of the deviation (ΔV _FB ) is used for the gate insulating film, the on-current characteristic and the off-leak characteristic are deteriorated.

Regarding the evaluation results, in the thermal oxide film formed by the comparative high temperature process, the deviation (ΔV _FB ) from the ideal flat band voltage is around −0.6V.
Therefore, in the case of the low temperature process, the deviation from the ideal flat band voltage (ΔV _{F. B} ) is − on the negative side.
It should be larger than 1.0V and smaller than + 1.0V on the positive side. The reason is that the more the deviation from the ideal flat band voltage (ΔV _FB ) shifts to the positive side, the greater the variation in the electrical characteristics among the TFTs. On the other hand, as the deviation from the ideal flat band voltage (ΔV _FB ) shifts to the negative side, the ON current decreases, the rising steepness of the ON current decreases, the OFF leak current increases, the threshold voltage increases, and the CMOS increases. This is because an adverse effect such as an increase in power consumption when the circuit is configured occurs.

As shown in FIGS. 1 and 2, when the silicon oxide film is formed by the plasma CVD method using TEOS, if the substrate temperature during film formation is changed, the film formation rate and the film thickness vary greatly. fluctuate. Further, as shown in FIG. 3, when the silicon oxide film is formed by the plasma CVD method using TEOS, if the substrate temperature during film formation is changed, the deviation of the flat band voltage greatly changes. Therefore, it can be said that the temperature variation within the same substrate greatly affects the film formation characteristics of the silicon oxide film. However, in a conventional plasma CVD apparatus, when a silicon oxide film is formed on the entire surface of a substrate having a large area of 360 mm × 465 mm such as an active matrix of a liquid crystal display panel,
Unlike the case where a silicon oxide film is formed on a relatively narrow substrate such as a silicon wafer, the substrate does not come into close contact with the sample table due to distortion, etc., and temperature variations occur in the same substrate. It turns out that it will end up.

[Embodiment 1] Therefore, in the first embodiment of the present invention, when a plasma CVD apparatus is configured as shown in FIG. 4 and a silicon film is formed by a plasma CVD method using TEOS, a sample is used. The electrodes are heated together with the glass substrate on the table.

FIG. 4 is a sectional view schematically showing the plasma CVD apparatus according to this embodiment.

In this figure, a plasma CVD apparatus 20
0A is a capacitive coupling type, and plasma is generated between parallel plate electrodes by using a high frequency power source.

In the plasma CVD apparatus 200A, the reaction chamber 201 is isolated from the outside air by the vacuum container 202, and the pressure is reduced from about 5 mtorr to about 5 torr during film formation. Inside the vacuum container 202, a sample table 203 (lower plate electrode) and an upper plate electrode 204 are arranged in parallel with each other, and these two electrodes form a parallel plate electrode. Sample table 203 and upper plate electrode 2
The reaction chamber 201 is between the parallel plate electrodes 04 and 04. Here, 410 mm × 510 mm parallel plate electrodes are used, and the distance between the electrodes is variable. Volume of the reaction chamber 201 is also adjustable from 2091Cm ³ to 10455Cm ³ with the change of the distance between the electrodes. The distance between the electrodes can be changed by moving the position of the sample table 203 up and down, and can be set to an arbitrary distance. The deviation of the inter-electrode distance in the plane of the parallel plate electrode when the inter-electrode distance is set to a certain value is only 0.1 mm. Therefore, the deviation of the electric field intensity generated between the electrodes is 1.0% or less in the plane of the parallel plate electrodes, and the plasma is uniformly generated in the reaction chamber 201.

A large glass substrate 205 on which a thin film is to be deposited is placed on the sample table 203, and the edge portion 2 mm of the substrate 205 is pressed by the shadow frame 206. The shadow frame 206 is, for example, the substrate 20.
When a general-purpose glass substrate is used as the substrate 5, the substrate 205 is prevented from being deformed into a concave shape by heat from the heater 207, and the substrate 205 is pressed so that an unnecessary thin film is not formed on the edge portion and the back surface of the substrate. ing.

A heater 207 for heating the substrate 205 is provided inside the sample table 203, and the temperature of the sample table 203 can be arbitrarily set between 25 ° C. and 400 ° C.

A reaction gas consisting of a raw material gas and, if necessary, an additional gas is introduced into the upper flat plate electrode 204 through the pipe 208, and further the upper flat plate electrode 20.
The gas passes through the space between the gas diffusion plates 209 provided inside the chamber 4 and flows into the reaction chamber 201 from the entire surface of the upper flat plate electrode 204 with a substantially uniform pressure. During film formation, a part of the reaction gas is ionized when it comes out of the upper plate electrode 204, and plasma is generated between the parallel plate electrodes. Part or all of the reaction gas is involved in film formation. The residual reaction gas not involved in the film formation and the generated gas generated as a result of the chemical reaction of the film formation are exhausted as exhaust gas from an exhaust hole 210 provided in the upper peripheral portion of the vacuum container 202.

The conductance of the exhaust hole 210 is preferably 100 times or more the conductance between the parallel plate electrodes. Further, the conductance between the parallel plate electrodes is sufficiently larger than the conductance of the gas diffusion plate 209, and the value thereof is preferably 100 times or more the conductance of the gas diffusion plate 209. With this configuration, the reaction gas is introduced into the reaction chamber 201 at a substantially uniform pressure from the entire surface of the large 410 mm × 510 mm upper flat plate electrode 204, and at the same time, the exhaust gas is evenly distributed from the reaction chamber 201 in all directions. It is discharged at a flow rate.

The flow rates of various reaction gases are adjusted to predetermined values by a mass flow controller (not shown) before being introduced into the pipe 208. Also, the reaction chamber 20
The pressure inside 1 is adjusted to a predetermined value by a conductance valve 211 provided at the outlet of the exhaust hole. A vacuum evacuation device (not shown) such as a turbo molecular pump is provided on the exhaust side of the conductance valve 211. In this example, an oil-free magnetic levitation type turbo molecular pump is used as a part of the vacuum exhaust device, and the background vacuum degree in the reaction chamber is set to the order of 10 ⁻⁷ torr.

In FIG. 4, the gas flow is indicated by arrows.
The vacuum container 202 and the sample stage 203 are at the ground potential, and these and the upper plate electrode 204 are separated from each other by the insulating ring 21.
2 maintains an electrically insulated state. At the time of plasma generation, the RF wave output from the oscillation source 213 (power supply) is amplified by the amplifier 214 and then applied to the upper plate electrode 204 via the matching circuit 215.

In this example, the RF power source is used, but a power source that emits microwaves or VHF waves may be used. Also,
RF power supply, industrial RF frequency (13.56MHz)
27.12 MHz, 40.6 MHz, which is an integral multiple of 5
It may be set to any frequency such as 4.24 MHz or 67.8 MHz. Such a frequency change is performed by the oscillation source 21.
3, the amplifier 214, and the matching circuit 215 can be easily replaced. In addition, in the electromagnetic wave plasma, when the frequency is increased, the electron temperature in the plasma is increased and radicals are easily generated.

The plasma CVD apparatus 2 thus constructed
In 00A, a heater 5 for heating the upper flat plate electrode 204 is provided on the back side (upper side) of the upper flat plate electrode 204.
01 is configured. Therefore, when the silicon oxide film (gate insulating film of the TFT) is formed by the plasma CVD method using TEOS, the substrate 205 on the sample table 203 is used.
The heater 207 heats (the glass substrate for the active matrix of the liquid crystal display panel) and the heater 501.
Thus, the upper plate electrode 204 can be heated. Therefore, when a silicon oxide film is formed on the surface of a large glass substrate (substrate 205) whose distortion cannot be ignored by TEOS using a plasma CVD method, the distortion of the substrate 205 causes the substrate 205 to adhere closely to the sample table 203. In the case where the state is not in the state, the temperature variation tends to occur in the same substrate, but in this embodiment, the upper flat plate electrode 204 facing the substrate 205 is heated by the heater 501. Is also heated by the upper plate electrode 204. As a result, the temperature variation in the substrate 205 is compressed. Therefore, even if the silicon oxide film formed by the plasma CVD method using TEOS is used, the substrate 205
Since there is little variation in film thickness and deviation from the ideal flat band voltage (ΔV _FB ) inside the TF, there is little variation in electrical characteristics even when it is used as a gate insulating film.
T can be manufactured.

The conventional plasma CV shown in FIG.
In the D device, the temperature of the substrate 205 and the temperature of the sample table 203 do not match even if a sufficient time has elapsed after the substrate was installed. Here, FIG. 5 shows a graph showing the relationship between the pressure in the reaction chamber 201 and the substrate temperature in the conventional plasma CVD apparatus. As shown in this figure, conventional plasma CVD
Although the temperature of the sample table 203 is controlled to be constant at 350 ° C. in the apparatus, the reaction chamber 20
The substrate temperature fluctuates easily even if the pressure in 1 changes. That is, in the conventional plasma CVD apparatus, the substrate temperature is determined by the balance between the heat flow from the sample stage 203 to the substrate 205 and the heat flow from the substrate 205 mainly to the upper flat plate electrode 204. In order to accurately control the substrate temperature in the CVD apparatus, it is not enough to control the temperature of the sample table 203, but the pressure inside the reaction chamber 201, the temperature of the upper plate electrode 204, the close contact between the sample table 203 and the substrate 205. Sex, etc. must be controlled. However, the fact that the adhesion between the sample table 203 and the substrate 205 is controlled is
Have difficulty. That is, the substrate 2 for the active matrix
Since 05 is a large glass substrate, it is difficult to obtain a substrate without distortion. Moreover, since the size of the product of the active matrix is much larger than that of the semiconductor chip, the uniformity of the film thickness distribution is required in a wider area. However, according to the present invention, since the substrate 205 is heated from both the sample table 203 and the upper plate electrode 204, the pressure in the reaction chamber 201 and the substrate 205 and the sample table 2 are increased.
Even if the adhesiveness of No. 03 changes, the substrate temperature does not change, and the uniformity of the film thickness distribution is good over a wider area.

In the plasma CVD apparatus, when a silicon oxide film having a thickness of several μm is formed on the upper plate electrode 204 in the reaction chamber 201, particles are generated. It is necessary to regularly perform a cleaning process for removing the film attached to the plate electrode 204. In this step, the gas introduced into the reaction chamber 201 is switched to the NF ₃ gas, and the degree of vacuum is changed to 0.15 Torr to 0.3 Torr, the electrode distance is 40 mm, and the RF power is 900 W to 1500 W. Under this condition, the rate of removing the silicon oxide film adhering to the inner wall of the reaction chamber 201 and the upper plate electrode 204 is 1500 angstroms / minute to 3000 angstroms. Therefore, such a cleaning process causes a decrease in throughput. However, according to the present invention, as shown in FIG. 1, in the plasma CVD method using TEOS, the film forming rate decreases as the film forming temperature increases, and similarly to FIG. 6, the upper plate electrode in the plasma CVD method using TEOS in FIG. As shown in the relationship between the temperature of 204 and the film formation rate on the surface of the upper flat plate electrode 204, in the plasma CVD method using TEOS, the higher the temperature of the upper flat plate electrode 204 is, the higher the film formation rate on the surface of the upper flat plate electrode 204 speed)
The upper flat plate electrode 204
Is heated to prevent the silicon oxide film from adhering to the upper plate electrode 204. Therefore, maintenance of the plasma CVD apparatus is easy, and it is possible to prevent a decrease in throughput due to the cleaning process.

In the present embodiment and any of the embodiments described below, from the standpoint of suppressing the film quality of the silicon oxide film and the generation of the silicon oxide film on the upper plate electrode 204, the substrate 205 and the upper part are prevented. It is preferable to heat both of the flat plate electrodes 204 to 200 ° C. or higher. Further, from the viewpoint of stabilizing the substrate temperature, it is preferable to heat the substrate 205 and the upper flat plate electrode 204 to the same temperature.

[Second Embodiment] FIG. 7 is a sectional view schematically showing a plasma CVD apparatus according to a second embodiment of the present invention. In the plasma CVD apparatus according to this embodiment, parts having the same functions as those of the plasma CVD apparatus shown in FIG. 4 are designated by the same reference numerals, and their description will be omitted.

As shown in FIG. 7, in the plasma CVD apparatus 200B according to this embodiment, a heater 207 for heating the substrate 205 is provided inside the sample table 203. A heater 503 for heating the upper flat plate electrode 204 is formed inside the upper flat plate electrode 204.

When forming a film in such a plasma CVD apparatus 200 B, the substrate 205 on the sample table 203 is used.
(Glass substrate for active matrix of liquid crystal display panel) is heated by heater 207 and heater 502
Thus, the upper plate electrode 204 can be heated. Therefore, when the silicon oxide film is formed on the surface of the large glass substrate (substrate 205) by the plasma CVD method using TEOS, the substrate 205 is not in close contact with the sample table 203 due to distortion or the like. However, in the present embodiment, since the heater 502 heats the upper plate electrode 204 facing the substrate 205, the substrate 205 is heated.
Is also heated by the upper plate electrode 204. As a result, the temperature variation in the substrate 205 is compressed. Therefore, even if the silicon oxide film is formed by the plasma CVD method using TEOS, the variation in the film thickness in the substrate 205 and the deviation (ΔV _FB ) from the ideal flat band voltage are small. Even when used as a film, it is possible to manufacture a TFT with a small variation in electric characteristics.

Also in this embodiment, since the upper flat plate electrode 204 is also heated, adhesion of a thin film to the upper flat plate electrode 204 is suppressed, so that maintenance is easy and similar effects to those of the first embodiment are obtained. Play.

[Third Embodiment] FIG. 8 is a sectional view schematically showing a plasma CVD apparatus according to a third embodiment of the present invention. In the plasma CVD apparatus according to this embodiment, parts having the same functions as those of the plasma CVD apparatus shown in FIG. 4 are designated by the same reference numerals, and their description will be omitted.

As shown in FIG. 8, in the plasma CVD apparatus 200C according to this embodiment, the sample stage 203C does not have a built-in heater. Instead, the sample stage 203C and the upper plate electrode 204 are surrounded. A wall-shaped heater 503 is formed in the inside. Therefore, the vacuum container 202 is in a state of being doubly partitioned by the heater 503. Also in this plasma CVD apparatus 200C, a reaction chamber 201 is provided between the sample stage 203C and the upper flat plate electrode 204.
A vacuum exhaust device is connected to the vacuum container 202, and the inside and outside of the heater 503 communicate with each other inside the reaction chamber 201. Therefore, when the vacuum container 202 is in a depressurized state, the inside of the heater 503 (reaction chamber 201). Is about 5 mto
The pressure is reduced from rr to about 5 torr. However, in the inside and outside of the heater 503, the degree of vacuum is higher on the outside, so that the foreign matter does not easily enter from the outside to the inside of the heater 503.

The exhaust hole 21 is provided for the heater 503.
0 is configured, and an exhaust device is connected to the exhaust hole 210. Therefore, the residual reaction gas that is not involved and the product gas generated as a result of the chemical reaction of the film formation are directly exhausted from the inside of the heater 503 as exhaust gas from the exhaust hole 210.

A reaction gas consisting of a raw material gas and, if necessary, an additional gas is introduced into the upper flat plate electrode 204 through the pipe 208, and further the upper flat plate electrode 20.
The gas flows through the space between the gas diffusion plates 209 provided inside the chamber 4 and flows out of the reaction chamber 201 from the entire surface of the upper plate electrode 204 at a substantially uniform pressure. During film formation, a part of the reaction gas is ionized when it comes out of the upper plate electrode 204, and plasma is generated between the parallel plate electrodes. The rest of the configuration is the same as that of the plasma CVD apparatus described with reference to FIG. 4, and the description thereof will be omitted.

The plasma CVD apparatus 2 thus constructed
At the time of forming a silicon oxide film by the plasma CVD method using TEOS at 00C, the heater 503 heats the substrate 205 (the glass substrate for the active matrix of the liquid crystal display panel) on the sample stage 203C, and
The upper plate electrode 204 is also heated. Therefore, when a silicon oxide film is formed on the surface of a large-sized glass substrate (substrate 205), temperature variations tend to occur within the same substrate. However, in this embodiment, the heater 503 keeps the substrate 205 from surroundings. While heating, the substrate 20
5, the substrate 205 is also heated by the upper flat plate electrode 204 because the upper flat plate electrode 204 facing the surface 5 is heated. As a result, the temperature variation in the substrate 205 is compressed. Therefore, even if the silicon oxide film is formed by the plasma CVD method using TEOS, the variation in the film thickness in the substrate 205 and the deviation (ΔV _FB ) from the ideal flat band voltage are small. Even when used as a film, it is possible to manufacture a TFT with a small variation in electric characteristics.

Further, since the vacuum container 202 is in a state of being divided into two parts by the heater 503, adhesion of a thin film to the heater 503 as well as to the vacuum container 204 is suppressed, and therefore maintenance is easy. Embodiment 1
Has the same effect as.

[0049]

EXAMPLE As described below with reference to FIG. 9, the method of forming a silicon oxide film according to each of the above-described embodiments includes not only the gate insulating film but also the surface of the substrate for the active matrix of the liquid crystal display panel. It can also be used to form a base protective film and an interlayer insulating film. FIG. 9 shows TF on the surface of a glass substrate for an active matrix of a liquid crystal display panel.
FIG. 6 is a process sectional view illustrating a method for manufacturing T.

In FIG. 9A, first, by the plasma CVD method according to any one of the above-described first to third embodiments, the base protective layer 12 (silicon oxide film) having a film thickness of 2000 angstrom is formed on the surface of the glass substrate 205. ) Is formed. The source gases at this time are TEOS and oxygen gas, TEOS supplies silicon, and oxygen gas supplies oxygen. The base protection layer 12 can also be formed by another CVD method or the like. Further, an insulating film such as a silicon nitride film or a multilayer film thereof can also be used.

Next, an intrinsic silicon film 13 (amorphous silicon film) is deposited on the surface of the base protection layer 12 to a thickness of about 600 Å, and the silicon film 13 is formed by solid phase growth at a processing temperature of 600 ° C. for about 24 hours. Perform polycrystallization. For such polycrystallization, laser annealing or rapid thermal processing (RTA) having a lower processing temperature can be used. After that, the silicon film 13 is processed into a predetermined shape by using a photolithography technique.

Next, a gate insulating film 14 made of a silicon oxide film having a thickness of 1200 Å is formed on the silicon film 13. In this step, the film formation temperature is set to 4 by the plasma CVD method according to any one of the first to third embodiments.
A silicon oxide film is formed by a low temperature process of 00 ° C. or lower. The source gases at this time are TEOS and oxygen gas, TEOS supplies silicon, and oxygen gas supplies oxygen.

Next, after forming a tantalum thin film having a film thickness of 6000 angstroms on the surface side of the gate insulating film 14 by the sputtering method, it is patterned by using the photolithography technique, and as shown in FIG. 9C. , The gate electrode 15 is formed. The tantalum thin film can also be formed by the CVD method or the like.

Next, impurity ions are implanted into the silicon film 13 using the gate electrode 15 as a mask, using a bucket type mass non-separation type ion implantation device (ion doping device). As a result, the source / drain regions 16 are formed in self-alignment with the gate electrode 15. At this time, the portion of the silicon film 13 where the impurity ions are not implanted becomes the channel region 17. In this example,
As the source gas, phosphine (PH ₃ ) diluted with hydrogen gas to a concentration of 5% was used, and the acceleration voltage was 10
It is 0 keV. The total dose of ions is 1 × 10 ¹⁶ c
m ^-2 . When forming a P-channel TFT, diborane (B ₂ H ₆ ) diluted with hydrogen gas to a concentration of 5% is used as a source gas.

Next, as shown in FIG. 9D, a silicon oxide film having a film thickness of 5000 Å is formed as the interlayer insulating film 18 by the plasma CVD method according to any one of the first to third embodiments. . The source gas at this time is also TEOS gas and oxygen gas.

Next, heat treatment is performed in an oxygen atmosphere at 300 ° C. for 1 hour to activate the implanted phosphorus ions and modify the interlayer insulating film 18.

Next, a contact hole 19 is formed in the interlayer insulating film 18. Then, the source / drain electrodes 20 are electrically connected to the source / drain regions 16 through the contact holes 19 to form TFTs.

The above manufacturing method is merely an example,
A low-concentration region or an offset region may be provided in a region of the source / drain region 16 facing the end of the gate electrode 15, and the present invention can be applied in any case.

As described above, the silicon oxide film of the TFT (the base protective film 12, the gate insulating film 14, and the interlayer insulating film 1)
Since the plasma CVD method is used to form 8), the film formation rate is high, the stress applied to the substrate 205 is small, and the step coverage is good even though it is a low temperature process. Moreover, since the method for manufacturing the silicon oxide film according to the first to third embodiments is used,
Even though the substrate 205 is large and made of glass, since the film forming temperature is uniform in the same substrate, it is possible to form a silicon oxide film having a constant film thickness in the same substrate. Further, the silicon film forming the gate insulating film 14 has uniform electric characteristics such as space charges and interface states in the same substrate. Therefore, it is possible to manufacture an active matrix for a liquid crystal display panel in which the electric characteristics of all TFTs on the same substrate are uniform.

[0060]

As described above, in the method of manufacturing a silicon film and a TFT according to the present invention, in the plasma CVD method using TEOS, not only the substrate on the sample stage but also the flat plate electrode facing the substrate is used. However, it is characterized by heating. Therefore, according to the present invention, the substrate on the sample stage is heated from the plate electrode side, and the substrate temperature during film formation is made uniform. Therefore, a silicon oxide film having a high film thickness uniformity can be manufactured even on a large-area substrate. Further, since the flat plate electrode is also heated, adhesion of the thin film to the flat plate electrode is suppressed, so that there is an advantage that the maintenance becomes easy.

[Brief description of drawings]

FIG. 1 is a graph showing a relationship between a substrate temperature and a film formation rate in a plasma CVD method using TEOS.

FIG. 2 is a graph showing a relationship between substrate temperature and film thickness variation in a plasma CVD method using TEOS.

FIG. 3 is a graph showing a relationship between a substrate temperature and a deviation from an ideal flat band voltage in a plasma CVD method using TEOS.

FIG. 4 is a cross-sectional view of the vicinity of a reaction chamber of the plasma CVD apparatus for performing the plasma CVD method according to the first embodiment of the present invention.

FIG. 5 is a graph showing the relationship between the pressure in the reaction chamber and the substrate temperature in the conventional plasma CVD apparatus.

FIG. 6 is a graph showing the relationship between the temperature of the upper plate electrode and the film formation rate on the surface of the upper plate electrode in the plasma CVD apparatus to which the present invention is applied.

FIG. 7 is a cross-sectional view near a reaction chamber of a plasma CVD apparatus for performing a plasma CVD method according to a second embodiment of the present invention.

FIG. 8 is a sectional view around a reaction chamber of a plasma CVD apparatus for performing a plasma CVD method according to a third embodiment of the present invention.

FIG. 9 is a process cross-sectional view schematically showing an example of a method for manufacturing a TFT.

FIG. 10 is a cross-sectional view near a reaction chamber of a conventional plasma CVD apparatus.

[Explanation of symbols]

13 ... Silicon oxide film 14 ... Gate insulating film 15 ... Gate electrode 16 ... Source / drain regions 200A, 200B, 200C ... Plasma CVD apparatus 201 ... Reaction chambers 203, 203C ... Sample stage 204 ... Upper flat plate electrode 205 ... Substrate 207 ... Heater 213 ... Oscillation sources 501, 502, 503 ... Heater for heating upper flat plate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/31 H01L 21/316 H01L 21/336 H01L 29/786

Claims (4)

(57) [Claims] 1. A substrate is placed on a sample stage in a vacuum container of a plasma chemical vapor deposition apparatus, and plasma is generated while a source gas is supplied to the vacuum container by a flat plate electrode facing the substrate. In the method of forming a silicon oxide film on the substrate, in the method of forming a silicon oxide film, tetraethoxysilane is used as the source gas, the substrate and the flat plate electrode are heated, and the heating is performed in the sample in the vacuum container. A method of forming a silicon oxide film, which is performed by a heater arranged so as to surround the table and the plate electrode. 2. The method for forming a silicon oxide film according to claim 1, wherein the substrate and the plate electrode are heated to 200 ° C. or higher. 3. The method for forming a silicon oxide film according to claim 1, wherein the substrate and the plate electrode are heated to the same temperature. 4. A method of manufacturing a thin film transistor using the method of forming a silicon oxide film as defined in any one of claims 1 to 3, wherein a glass substrate is used as the substrate, and the silicon is provided on the front surface side of the glass substrate. A method of manufacturing a thin film transistor, wherein an oxide film is formed as a gate insulating film of the thin film transistor.