JP3474091B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor manufacturing apparatus and a manufacturing method thereof. More specifically, the present invention relates to a thin film transistor having a double gate structure.

[0002]

2. Description of the Related Art Thin film transistors (TFTs) are SRA
It is widely used in M and liquid crystal display devices, etc., and its technical importance is increasing. Especially low power consumption type SR
In AM, it is important to reduce the off current of the thin film transistor in order to reduce the data holding power, and in the TFT using polysilicon, the tunnel current is generated through the trap existing in the grain boundary of polysilicon, which is mainly caused by the off current. Various studies have been made so far in order to reduce the current. For example, as a LDD structure, a low-concentration region (offset region) is provided on the drain side, the trap density is reduced by increasing the grain size of polysilicon, the trap is inactivated by hydrogen or oxygen plasma, or the channel of a thin film transistor is formed. The interface state density existing at the interface between the channel and the oxide film is reduced by oxidizing the polysilicon. However, although using these methods is effective in reducing the off-current, it is not always sufficient in terms of increasing the on-current. Therefore, as one of the methods for improving the on-current, there is a double gate structure. By adopting the double gate structure, the entire region of the channel is inverted and the subthreshold characteristics are improved, so that the drive current, punch through breakdown voltage, short channel effect, etc. can be improved compared to the single gate structure. It has been confirmed that it is also advantageous for miniaturization.

In the double gate structure in which the gate voltage exists above and below the channel, the channel region occupies a planar size, and is not suitable for high integration of the device. As an improvement, there is one in which the channel region is formed vertically.
If you make it vertical, the area of the channel region can be ignored,
The area of the element is only the area of the source / drain region, which is advantageous for high integration. As an example of this, one is
Although it does not have a double gate structure, it is not shown in FIGS.
No. 47788), there is a bottom gate structure. However, since these have a single gate structure, the active layer is not effectively used. On the other hand, JP-A-7-18
As disclosed in Japanese Patent No. 3528, there is a configuration in which a channel region is formed vertically with a double gate structure. As shown in FIG. 6, this is the active layer 313a that becomes the channel region.
Is formed on a plane and the active layer 313b is formed vertically, and two gate electrodes 303 and 308 form gate electrodes above and below and on the left and right of the channel to increase the channel width and effectively utilize the area. FIG. 7 briefly shows the manufacturing method. After forming the gate electrode 303, the gate insulating film 304, and the active layer 313a, the dummy spacer 3 of the insulating film is formed on the active layer 313a.
14 is formed, and the active layer 313b is deposited thereon (see FIG. 7A). Next, etch back is performed to form a vertical active layer 313b (see FIG. 7B). Next, after removing the dummy spacers 314 (see FIG. 7C), the upper gate insulating film 306 and the upper gate electrode 308 are formed (see FIG. 7D).

[0004]

However, in the thin film transistor shown in FIG. 6, the upper gate electrode is added to form a double gate structure for the purpose of increasing the on-current. The accuracy becomes strict and it is not necessarily suitable for high integration. Further, the channel region also needs a planar dimension as shown in the plan view of FIG. In addition, since the gate width is expanded by utilizing the space in the vertical direction, the polysilicon layer of the channel is processed twice and the upper gate electrode is also formed on the active layer. There is a concern that the process margin at the time of microfabrication may be reduced in the subsequent process because a step difference is added.

Further, the dummy spacer 31 shown in FIG.
The field film is also etched if an etching mask such as a resist is not formed during the etching removal of No. 4. Further, since the end portions of the active layers 313a and 313b are surrounded by the gate electrodes on three sides, the electric field concentration increases the leak current at the off time. In addition, there is concern that the reliability of the gate insulating film formed at the corners of the edge may deteriorate. The object of the present invention is to suppress the increase of the off current of the thin film transistor and to effectively increase the on current of the thin film transistor while ensuring the process margin at the time of manufacturing, which is advantageous for the low voltage operation with the improved switching characteristics and is compatible with the miniaturization. It is to provide a possible thin film transistor.

[0006]

SUMMARY OF THE INVENTION According to the present invention, a channel width is formed by vertically arranging a channel of a polysilicon thin film so as to be located on a sidewall of a lower gate electrode and forming a transistor so as to surround the lower electrode. And a double gate structure with an upper electrode formed in a sidewall shape so as to surround the lower gate electrode in a self-aligned manner through a gate insulating film to improve the drive capability of the thin film transistor A thin film transistor having a large ON current and improved switching characteristics is provided.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings. The present invention is not limited to this. FIG. 1 is a structural explanatory view of a thin film transistor according to the present invention, FIG. 2 is a sectional view taken along the line AA ′, and FIG. 3 is a sectional view taken along the line BB ′. The manufacturing method will be described below. 2 and 3 are at the same stage.

In order to form a thin film transistor having a double gate structure, first, as shown in FIG. 2A, an oxide film is formed on a silicon substrate 1 as a first insulating film 2 for insulating the silicon substrate 1 and the lower gate electrode 3a. Silicon film from 200 to
After forming a first polysilicon film 3 having a thickness of 500 nm and a lower electrode of 300 to 500 nm thereon, boron is ion-implanted on the entire surface at a dose amount of 1E + 15 to 5E + 15 cm ⁻² to perform high concentration doping. Next, the lower gate electrode 3a is formed by dry etching using the resist as a mask. At this time, in order to set the gate length to the thickness of the first polysilicon film and to reduce the off-current by relaxing the electric field of the drain region at the gate end, the first insulating film which is the underlying silicon oxide film. The film 2 is over-etched by 60 to 130 nm corresponding to the film thickness of the lower gate insulating film 4 and the second polysilicon film 5.

Next, as shown in FIG. 2B, a silicon oxide film to be the lower gate insulating film 4 is formed on the entire surface in a thickness of 20 to 50 nm.
It is formed by the CVD method. Next, an amorphous silicon thin film is deposited on the entire surface by a CVD method at a temperature of 550 ° C. or lower at 40 to 80 nm, and is crystallized by solid phase growth in a nitrogen atmosphere at 600 ° C. or lower.
A second polysilicon film 5 to be a is formed. This layer constitutes the body of the thin film transistor. Next, the second polysilicon film 5 is ion-implanted as channel doping by a dose amount of 1E + 12 to 1E.
Phosphorus ions are obliquely implanted at about +13 cm- ² .
At this time, the second gate electrode located on the side surface of the lower gate electrode 3a
Ion implantation so that it is implanted into the polysilicon film 5.
Carry out. Then, the active layer 5a is formed by photo-etching so that a part of the lower gate electrode 3a is not covered like the pattern 5a in FIG. 1A (FIG. 3).
(B)).

Next, as shown in FIG. 2C, the surface thereof is thermally oxidized or a silicon oxide film to be the upper gate insulating film 6 is formed to a thickness of about 20 to 50 nm by a CVD method,
The entire surface and a dose of 1E + 13~1E + 14cm- relatively low concentration region other than vertical portion serving as the channel by injecting the vertical boron ions into the active layer 5a in ^2. this
In this case, the active layer 5 located on the side surface of the lower gate electrode 3a
The area other than the vertical portion of a is the low-density area. Next, a resist pattern is formed so that the edge of the lower gate electrode 3a is opened, and the lower gate insulating film 4 on the lower gate electrode 3a and on the side wall is removed using a dilute HF solution or the like to form the first contact 7. Form. After that, a third polysilicon film 8 to be the upper gate electrode 8a is formed on the entire surface by the CVD method.
After depositing 50 to 300 nm, boron is dosed 1E on the entire surface.
+ 15~5E + 15cm- after heavy doping in the ion implantation at approximately ^2, and etched back until the upper gate insulating film 6 is silicon oxide film is exposed, the side so as to surround the lower gate electrode Wall The upper gate electrode 8a having a striped shape is formed. At this time, FIG.
In the first contact portion 7 provided on the side wall of the lower gate electrode 3a, the lower gate electrode 3a and the upper gate electrode 8a can be connected to each other, and a double gate structure can be realized by self-alignment. Become. Then active layer 5a by ion implanting boron in the vertical direction at a dose of 1E + 15~1E + 16cm- ² about the entire surface
High-concentration source / drain regions 53 and 54 are formed therein. At this time, since it is not injected into the active layer 5a below the sidewall-shaped upper electrode 8a, the offset region 52 can be formed only on the drain side by self-alignment. The length of the offset is the sidewall width, that is, the third polysilicon film 8 to be the upper gate electrode 8a.
Generally determined by thickness.

Next, as shown in FIG. 2D, CVD is performed on the entire surface.
After the oxide film 9 is laminated and the second contact 10 is opened, a metal layer 11 of aluminum or the like is deposited on the entire surface, and then wiring is formed by photoetching. To take out the gate electrode, a second contact is formed in a portion not covered with the active layer 5a. As described above, a thin film transistor having a double gate structure is produced. In the above-mentioned embodiment, p for forming the high concentration region and the low concentration region of the thin film transistor is formed.
Boron has been used as the type impurity, but is not limited to boron. It is also possible to use n-type impurities such as phosphorus and arsenic of opposite types. In addition, by using the in-situ doping technique for the channel doping of the active layer 5a and the high concentration doping of the polysilicon used for the lower and upper electrodes, each ion implantation process can be eliminated, which is effective from the viewpoint of process simplification. is there.

As another embodiment, referring to FIG. 2C, a high concentration of boron ions are formed to form a low concentration region, and a high concentration of boron ions is implanted after the etching back of the third polysilicon film 8. If omitted, a thin film transistor without a low concentration region is formed as shown in FIG.

[0013]

As described above, the thin film transistor having the double gate structure according to the present invention has the following effects. The thin film transistor channel is vertically arranged so as to be located on the side wall of the lower gate electrode, and a transistor is formed so as to surround the lower electrode to widen the channel width. With the gate structure, the drive current (ON current) can be increased. Further, since the channel region is surrounded by electrodes on the left and right sides instead of the three sides, it is advantageous in terms of electric field concentration and reliability of the gate insulating film.

Not only can the processing accuracy of photo-etching which can realize the processing of the upper gate electrode and the formation of the offset region in a self-aligned manner be relaxed, the degree of freedom in design is improved, and it is suitable for miniaturization. A thin film transistor can be provided. Since the upper gate electrode does not exist on the active layer, the step margin corresponding to the film thickness does not reduce the process margin. When the first polysilicon film to be the lower gate electrode is processed, the underlying first insulating film is over-etched by at least about the thickness of the first gate film and the active polysilicon thin film, so that the drain at the gate end The effect of reducing the off current can also be obtained by relaxing the electric field in the region.

[Brief description of drawings]

1 (a) is a plan view according to the present invention, FIG.
1B and 1C are cross-sectional views taken along the line AA '.

2 (a) to 2 (d) are manufacturing process explanatory diagrams for explaining one embodiment of the present invention, and are process cross-sectional views taken along the line AA ′ in the configuration explanatory diagram.

3 (a) to 3 (d) are manufacturing process explanatory diagrams for explaining an embodiment of the present invention, and are process cross-sectional views taken along the line BB ′ in the configuration explanatory diagram.

FIG. 4 is an explanatory diagram showing an example of a conventional technique.

FIG. 5 is an explanatory diagram showing an example of a conventional technique.

FIG. 6 is an explanatory diagram showing an example of a conventional technique.

FIG. 7 is an explanatory diagram showing an example of a conventional technique.

[Explanation of symbols]

1 Silicon substrate 2 First insulating film 3, 3a Lower gate electrode (first polysilicon film) 4 Lower gate insulating film (silicon oxide film) 5, 5a Active layer (second polysilicon film) 6 Upper gate insulating film (silicon oxide film) 7 First contact 8, 8a Upper gate electrode (third polysilicon film) 9 Interlayer insulation film (CVD oxide film) 10 Second contact 51 channel area 52 Offset area Low density area 53, 54 Source drain region

Claims (6)

(57) [Claims] 1. A and the lower gate electrode formed on the insulating film, the insulating film during the lower gate electrode processing, the lower gate
Formed on the surface of the lower gate electrode and on the surface of the lower gate electrode, and a step corresponding to the film thickness of the gate insulating film and the active layer is formed. An active layer, a channel region formed in the active layer so as to be located on a sidewall of the lower gate electrode,
An upper gate insulating film formed on the surface of the active layer, an upper gate electrode formed on the upper gate insulating film so as to cover the channel region, and an upper gate electrode immediately below the upper gate electrode so as to be adjacent to the channel region. A low concentration impurity region formed in the active layer located on the insulating film, and the active layer in the active layer located on the insulating film so as to be adjacent to the low concentration impurity region and on the lower gate electrode. A high-concentration impurity region formed therein, a semiconductor device. Wherein a lower gate electrode formed on the insulating film, the insulating film during the lower gate electrode processing, the lower gate
Formed on the surface of the lower gate electrode and on the surface of the lower gate electrode, and a step corresponding to the film thickness of the gate insulating film and the active layer is formed. An active layer, a channel region formed in the active layer on the sidewall of the lower gate electrode, an upper gate insulating film formed on the surface of the active layer, and an upper gate insulating film. An upper gate electrode formed to cover the channel region, and a high concentration formed in the active layer located on the insulating film adjacent to the channel region and on the lower gate electrode. A semiconductor device comprising: an impurity region. 3. The semiconductor device according to claim 1, wherein the lower gate electrode is connected to the upper gate electrode through a side wall of the lower gate electrode, thereby forming a double gate structure. apparatus. 4. A first insulating film and a first polysilicon film to be a lower gate electrode are sequentially deposited on the entire surface of a semiconductor substrate, and the first polysilicon film is used as the first insulating film .
After patterning by over-etching so as to provide a step corresponding to the film thickness of the lower gate insulating film and the active layer ,
A lower gate insulating film is formed on the surface of the lower gate electrode and the first insulating film, and a second polysilicon film serving as an active layer of a thin film transistor is formed on the surface of the lower gate insulating film. A channel region is formed on the sidewall of the gate electrode, and a low-concentration impurity region is formed on the first insulating film so as to be adjacent to the channel region in the second polysilicon film serving as the active layer. And the second
Forming an upper gate insulating film so as to cover the surface of the polysilicon film and depositing a third polysilicon film to serve as an upper gate electrode, and then performing etch back to form a channel region on the sidewall of the lower gate electrode. Forming an upper gate electrode to cover the upper gate electrode and forming a high-concentration impurity region in the second polysilicon film serving as the active layer so as to be adjacent to the region on the lower gate electrode and the low-concentration impurity region. A method of manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 4, wherein when forming the low-concentration impurity region, a high-concentration impurity region is formed instead of a low concentration. 6. The method of manufacturing a semiconductor device according to claim 4, wherein before the third polysilicon film is deposited,
A method of manufacturing a semiconductor device, comprising: opening a part of an upper gate insulating film to expose a part of a first polysilicon film which is a lower gate electrode, and depositing a third polysilicon film.