JP3474166B2 - Electron beam drawing method and electron beam drawing apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron beam drawing method and an electron beam drawing apparatus, and more particularly to an electron beam drawing method and an electron beam drawing apparatus capable of performing overexposure on a pattern already drawn with high accuracy. .

[0002]

2. Description of the Related Art In recent years, an electron beam drawing apparatus and an optical reduction exposure apparatus have been used in combination to draw a pattern including many relatively fine patterns among a plurality of patterns to be overlaid and exposed by the electron beam drawing apparatus. Hybrid exposure is performed in which an LSI having a multilayer structure is manufactured by exposing a pattern using a light reduction exposure apparatus.

By the way, the exposure pattern formed by the optical reduction exposure apparatus includes the exposure distortion peculiar to the lens of the optical reduction exposure apparatus,
The exposure error due to the environmental change at the time of light reduction exposure is included. Therefore, when the electron beam drawing apparatus draws the pattern as designed on the pattern exposed by the light reduction exposure apparatus, a registration error occurs between the patterns in the upper and lower layers.

[0004]

In order to improve the overlay accuracy between the exposure pattern formed by the optical reduction exposure apparatus and the writing pattern formed by the electron beam writing apparatus, the marks formed on the wafer by the optical reduction exposure apparatus are improved. A method of measuring the position to determine the exposure distortion peculiar to the optical reduction exposure apparatus, and correcting the exposure distortion at the time of electron beam drawing to perform drawing is disclosed in Japanese Patent Laid-Open No. 62-62.
It is described in Japanese Patent No. 58621. However, in this method, in order to cope with the dynamic characteristic change of the optical reduction exposure apparatus, it is necessary to perform chip alignment on all the chips on the wafer, and it is necessary to measure the marks at high frequency. is there.

Further, Japanese Patent Laid-Open No. 186331/1982 discloses a method of arranging marks sufficient for evaluating the exposure distortion in the peripheral portion of the pattern and detecting and correcting the marks at the time of drawing. However, this method cannot improve the throughput because the number of mark detection points for evaluating the distortion is large. On the other hand, in the optical reduction exposure apparatus, recently,
As described in Japanese Patent Application Laid-Open No. 62-169329, there is an alignment method as an alignment method for detecting a mark at a designated point in a wafer to shorten the exposure time and correct the chip arrangement information of the entire wafer. It is used. This method has the advantages that (1) statistical processing can reduce the influence of mark detection errors, and (2) the time required for mark detection can be shortened. However, since this method only corrects the array information, in reality, corrections such as magnification change and rotation of the chip are finely adjusted manually by looking at the exposure result.

The present invention has been made in view of the problems of the prior art as described above, and has a high level with respect to a pattern having a static distortion and a dynamic distortion formed by a lower layer exposure apparatus, particularly a light reduction exposure apparatus. An object of the present invention is to provide an electron beam drawing method and an electron beam drawing apparatus capable of performing accurate overlay exposure with high throughput.

[0007]

According to the present invention, the positions of marks formed in advance on each chip on a wafer are measured for a predetermined number of chips, and the positions of the measured marks and the design of the marks. From position and statistical processing,
Wafer coordinates of each chip, shape distortion and misalignment of the chip
Find the relationship with the difference . Then, by using the relationship to correct the pattern drawn on each chip, the overlay accuracy is increased and the throughput is increased.

That is, the present invention is an electron beam drawing method for scanning an electron beam on a wafer to draw a desired pattern on a plurality of chips set on the wafer. Two marks are detected for each of a predetermined number of chips, and the relationship between the shape distortion and arrangement error of each chip in the wafer surface and the wafer coordinates is statistically processed from the detected mark position and the design position of the mark. It includes the steps of determining, the step of drawing a pattern on all the chips while correcting the pattern to be drawn on each chip by using the relationship between the shape distortion and alignment errors and wafer coordinates of chips obtained in the step Is characterized by. Marks can be placed on the corners of each chip
It

The relationship between the chip shape distortion and the array error and the wafer coordinates can have a plurality of series. Further, it is possible to determine the erroneous detection of the mark by using the obtained information on the distorted shape of the chip. The shape distortion of the chip can be obtained with high accuracy by excluding the information on the mark position determined to be erroneous detection and performing the statistical processing. For time-varying strain or dynamic strain that varies from chip to chip, for example, the relationship between the exposure sequence of multiple chips and the shape distortion of the chips was obtained, and the pattern to be drawn on each chip was obtained in this way. This can be dealt with by correcting using the relationship between the exposure order and the shape distortion.

The electron beam drawing apparatus according to the present invention is a wafer
Scan multiple electron beams on the wafer and set multiple chips on the wafer
For electron beam drawing equipment that draws a desired pattern for
And at least two marks formed in the chip.
Detector for each of a specified number of chips, and
The position of the mark detected by the output device and the design position of the mark
Distortion and alignment error of each chip on the wafer surface
Control calculation to obtain the relationship between the wafer coordinates and wafer coordinates by statistical processing
And the shape distortion of the chip calculated by the control computer.
And draw on each chip using the relationship between alignment error and wafer coordinates
Putting pattern on all chips while correcting the pattern to be drawn
It is characterized by drawing an image. Mark is the corner of each chip
Can be provided.

An electron beam drawing apparatus according to the present invention has a function of calculating overlay accuracy by an electron beam drawing method for obtaining shape distortion and arrangement error of chips by the statistical processing.
When the calculated overlay accuracy is within the preset accuracy, the electron beam drawing method for obtaining the shape distortion of the chip by the statistical processing is selected, and when the calculated overlay accuracy is lower than the preset accuracy, It is characterized by having a function of automatically switching to the other electron beam drawing method. The electron beam drawing method and the electron beam drawing apparatus of the present invention can be used for manufacturing a semiconductor element.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic view of an electron beam drawing apparatus used in the method of the present invention. The electron beam emitted from the electron source 1 passes through the first mask (rectangular forming diaphragm) 2,
After passing through the molded lens 4, the second mask (variable molded diaphragm) 6
To reach. When irradiating the second mask 6, the molding deflector 3 is designated by the control computer 19 in the molding deflection control circuit 15, and the molding deflector 3 causes the molding deflector 3 to specify.
A rectangular beam having a specified size on the wafer 12 is transmitted through the second mask 6 by applying a voltage to the second mask 6.

The electron beam (formed beam) 9 transmitted through the second mask is reduced by the reduction lens 7, and the control computer 19 is used.
A deflection signal is set in the positioning deflector 8 by setting the deflection position designated by the position in the positioning deflection control circuit 16, the shaped beam 9 is deflected to a designated position, and the wafer 12 on the sample stage 13 passes through the objective lens 10. Is irradiated.
The movement of the sample table 13 is performed by the sample table positioning mechanism 14 and the sample table position control circuit 18 in accordance with a command from the control computer 19.

By controlling the shaped beam 9 and the sample table 13 as described above, an LSI pattern having a specified shape can be drawn at a specified position on the wafer 12. Further, the backscattered electron signal of the shaped beam 9 applied to the mark on the wafer 12 is detected by the backscattered electron detector 11,
It is possible to notify the control computer 19 of the position of the mark formed on the wafer 12 by being processed by the mark detection circuit 17.

Next, the electron beam drawing method of the present invention using this electron beam drawing apparatus will be described. First, the distortion of the pattern formed by the optical reduction exposure apparatus will be described below. FIG. 2 shows an array of chips formed on the wafer 12. A rectangular shape 20 shown by a broken line in FIG. 2 is a designed chip shape. On the other hand, the quadrangle shown by the solid line is an exaggerated representation of the chip shape exposed by the optical reduction exposure apparatus. In this example, each chip is exposed with a cross-shaped mark 21 at the four corners of the chip together with the pattern, and the solid line quadrangle is a figure formed by connecting the marks arranged at the four corners of the chip.

When the optical reduction exposure apparatus exposes one chip in one shot, the shape of each chip has various distortions with respect to the design shape 20 as shown in the following 1 to 4. 1. Intrinsic distortion due to lens aberrations. 2. Magnification changes due to changes in environment (temperature, atmospheric pressure) during exposure. 3. Rotation of each chip shape depending on the exposure position. 4. Array error of each chip.

The distortion due to the lens aberration is a high-order distortion that is static with respect to the center of the chip. The amount of change in magnification is a small amount that occurs during one wafer exposure, and is an amount that changes from wafer to wafer. The rotation of each chip occurs due to yawing of the sample table of the optical reduction exposure apparatus. The array error of each chip is caused by an error in the stage length measuring system, for example, a change in the laser wavelength of the laser length measuring system due to a change in atmospheric pressure or a distortion of the length measuring mirror set in the stage.

The distortion of the chip shape can be expressed by the following equation. Now, an XY coordinate system is set on the wafer, and the coordinates of each chip from the wafer center are (X _w ,
Y _w ), the coordinates of the exposure position in the chip are (X _c , Y _c ),
The exposure position in the chip after correction in consideration of the distortion is (X ′ _c ,
'If _{c), X' Y c,} Y 'c can be expressed by the following equation (1) and expression (2).

[0019]

[Equation 1] X '_c= F₀(X_w, Y_w) + A₁・ X_c+ F_Two(X
_w, Y_w) Y_c+ F_Three(X_c, Y _c)

[0020]

[Formula 2] Y '_c= G₀(X_w, Y_w) + G₁(X_w, Y_w) X
_c+ B_Two・ Y_c+ G_Three(X_c, Y _c)

In the above [Equation 1] and [Equation 2], the function
f₀(X_w, Y_w) And g₀(X_w, Y _w) Is the shift i.e.
Represents parallel movement, a₁, B_TwoIndicates a change in magnification. Also,
Function f_Two(X_w, Y_w) And g₁(X_w, Y_w) Indicates rotation
And the function f_Three(X_c, Y_c) And g_Three(X_c, Y_c) Is static
Represents distortion.

On the other hand, in the optical reduction exposure apparatus, the temperature of the lens is changed by the energy accumulated on the lens and the lens is deformed. Therefore, considering this change, a ₁ ,
When b ₂ is a function of coordinates (X _w , Y _w ), the above [Equation 1] and [Equation 2] can be expressed as the following [Equation 3] and [Equation 4].

[0023]

Equation 3] _{X 'c = f 0 (X} w, Y w) + f 1 (X w, Y w) X
_{c + f 2 (X w,} Y w) Y c + f 3 (X c, Y c)

[0024]

## EQU4 ## _Y'c = g ₀ (X _w , Y _w ) + g ₁ (X _w , Y _w ) X
_{c + g 2 (X w,} Y w) Y c + g 3 (X c, Y c)

F in the above [Equation 3] and [Equation 4]₀, F₁，
f_Two, F_Three, G₀, G₁, G_Two, G _ThreeTo calculate
The entire wafer surface of chips exposed by the lower layer exposure system
The relational expression in can be calculated. And this relation
Exposure with high overlay accuracy by drawing the entire surface of the wafer using
can do. Next, refer to the flowchart in FIG.
To obtain the above relational expression and correct the drawing position
The order will be explained.

First, the sample stage 1 is set so that the mark position in the designated chip is at the zero deflection position of the shaped beam 9.
Move 3 After that, in step 30, the mark 21 is scanned with the shaping beam, and the mark position is detected by the mark detection circuit 17. The result is the control computer 1
Take in 9. Such processing is repeated for the number of designated marks in the chip, and in step 31, the matching coefficient formulas of the following [Equation 5] and [Equation 6] are calculated by the least square method. Here, the design coordinates of the mark position in the chip are (X
_mc , Y _mc ) and the measurement coordinates of the mark position in the chip are (X _mcm Y _{m cm} ).

[0027]

## _EQU00005 ## X _mcm = a ₀ + a ₁ X _mc + a ₂ Y _mc + a
₃ X _mc Y _mc

[0028]

## _EQU6 ## Y _mcm = b ₀ + b ₁ X _mc + b ₂ Y _mc + b
₃ X _mc Y _mc

The above equation is a matching coefficient when four-point marks are present in the chip, but a higher order matching correction coefficient can be calculated by increasing the number of marks. This mark detection and creation of the alignment correction coefficient are repeated for the designated chip (step 32). Next, the alignment coefficients a ₀ , a ₁ , a ₂ , a ₃ , measured for each chip,
The relational expressions of b ₀ , b ₁ , b ₂ and b ₃ and the coordinates of the chip from the wafer center are (X _w , Y _w ) are assumed as in the following [Equation 7] to [Equation 14].

[0030]

## EQU00007 ## a ₀ = A ₀₀ + A ₀₁ X _w + A ₀₂ Y _w + A
₀₃ X _w Y _w

[0031]

## EQU8 ## a ₁ = A ₁₀ + A ₁₁ X _w + A ₁₂ Y _w + A
₁₃ X _w Y _w

[0032]

## EQU00009 ## a ₂ = A ₂₀ + A ₂₁ X _w + A ₂₂ Y _w + A
₂₃ X _w Y _w

[0033]

## EQU10 ## a ₃ = A ₃₀

[0034]

B ₀ = B ₀₀ + B ₀₁ X _w + B ₀₂ Y _w + B
₀₃ X _w Y _w

[0035]

B ₁ = B ₁₀ + B ₁₁ X _w + B ₁₂ Y _w + B
₁₃ X _w Y _w

[0036]

B ₂ = B ₂₀ + B ₂₁ X _w + B ₂₂ Y _w + B
₂₃ X _w Y _w

[0037]

B ₃ = B ₃₀

Then, in step 33, the coefficients A ₀₀ , A ₀₁ , A ₀₂ , ... Of the equations 7 to 14 are expressed.
.., B ₂₂ , B ₂₃ , and B ₃₀ are calculated by the least squares method to obtain relations f ₀ , f ₁ , f ₂ , f ₃ , g ₀ ,
It becomes possible to calculate g ₁ , g ₂ , and g ₃ . The orders of the coefficients of [Equation 7] to [Equation 14] can be corrected to a higher order in accordance with the lower layer exposure apparatus. In particular,
Since the correction formulas for the chip array positions represented by [Equation 7] and [Equation 11] depend on the linearity of the mirror of the laser interferometer that is fixed to the sample table 13 and measures the position of the sample table 13, Higher-precision approximation can be achieved by using a third-order or fifth-order approximation formula.

Next, in the case of drawing the entire surface of the wafer, in step 34, a ₀ , a ₁ , a ₂ , a ₃ , b ₀ , b ₁ , represented by [Equation 7] to [Equation 14] are expressed. The wafer in-plane coordinates of the target chip are substituted into the relational expressions regarding b ₂ and b ₃ to calculate the strain coefficient. Subsequently, in step 35, the distortion coefficient calculated in step 34 is applied to the deflection target data in one chip, the designated coordinates are corrected to be the target coordinates, and one chip is drawn in step 36.
This process is performed on the chips on the entire surface of the wafer to complete the drawing of all the chips (step 37).

Next, as shown in FIG. 4, a plurality of patterns (see FIG. 4) are formed on the reticle 51 used in the optical reduction exposure apparatus.
In this case, A, B, and two types of patterns) are formed, and one pattern may be exposed by masking the pattern on one side. At this time, as shown in the figure, chips of pattern A and chips of pattern B are divided into two groups and formed on the wafer 12.

In such a case, if the correction is performed according to the above procedure,
Since the chip peculiar distortion differs between the pattern A chip and the pattern B chip, when the relational expressions [Equation 7] to [Equation 14] are commonly used on the entire surface of the wafer, the pattern A and the pattern B are unique. The difference in the strains causes a difference in the intrinsic strain, which causes a problem in superposition. Therefore, by having a plurality of relational expressions such as a relational expression regarding the pattern A chip and a relational expression regarding the pattern B chip, it is possible to perform drawing with high precision on the chips of any pattern.

At this time, a ₀ , a ₁ , a ₂ , a represented by [Equation 7] to [Equation 14] regarding the chip of the pattern A are expressed.
_The relational expressions for ₃ , b ₀ , b ₁ , b ₂ , and b ₃ are calculated by detecting the marks provided in the chip of the pattern A, and the relational expression of the correction for the chip of the pattern B is It goes without saying that the calculation is performed by detecting the mark provided in the chip.

In the above, the coefficients a ₁ and b ₂ of the magnification are calculated by the relational expression of the coordinates X _w and Y _w of the chip. However, as shown in FIG. 5, in the case of the light reduction exposure apparatus, the magnification is changed from the unexposed state, that is, the state where the lens is not irradiated with light, to the stable exposure state, that is, the lens is irradiated with light, and The temperature rises until it becomes saturated and the lens temperature becomes constant. It is difficult to express such changes with the relational expressions of the positions X and Y.

Therefore, the exposure order of each chip of the lower layer exposure apparatus is stored in advance in the control calculation formula, and the relational expression between this exposure order T _n and the coefficients a ₁ and b ₂ of the magnification change is given by the following [Equation 15]. And [Equation 16].

[0045]

## EQU15 ## a ₁ = C ₀ + C ₁ T _n + C ₂ T _n ²

[0046]

B ₂ = D ₀ + D ₁ T _n + D ₂ T _n ²

With respect to the change of the magnification, the temperature of the lens becomes stable after a certain period of time, so that the magnification does not change.
An error will occur if the above approximation formula is applied to all chips. Therefore, the amount of change in magnification is sequentially calculated for the next measurement target chip from the chip starting the lower layer exposure, and the chips up to a certain fixed amount are applied to the above relational expression, and the chips after that are averaged for the chips after that. Exposure is performed at a magnification.

By performing the exposure according to the relational expression regarding the exposure order of exposing the lower layer, it is possible to perform the overlapping exposure corresponding to the magnification change depending on the exposure order of the lower layer exposure apparatus. As for the target chip for mark measurement, the chips after exposure start at the time of lower layer exposure are densely specified, and the chips that are expected to be in a stable state are roughly specified, while suppressing the decrease in throughput. Highly accurate exposure can be performed.

According to the method described above, the relational expression of each coefficient
f₀, F₁, F_Two, F_Three, G₀, G ₁, G_Two, G_ThreeCalculate
Since the least squares method is applied to output, every 1 chip
Mark detection is performed on 1 chip according to the detection result.
Compared with the conventional chip alignment method for drawing,
It is possible to reduce the minute error due to the detection itself. But Mar
It is impossible to avoid a large error caused by breakage, etc.
The influence is reflected in the drawing result. Such mark detection error
As a method of removing the difference, the entire detected mark coordinates are
A method of first-order approximation and determining an abnormal mark from the difference is
It is considered. However, this method also includes anomalous marks.
Since the entire mark coordinates are first-order approximated,
It is a mark that is measured normally with respect to nearby marks.
Nevertheless, it may be considered as an anomaly mark.

In the method of the present invention, the chip shape for each chip is calculated. Therefore, by utilizing this change in the chip shape, accurate error determination can be performed. As described above, the second or higher-order strain with respect to the XY coordinates on the wafer is a static strain peculiar to the device. Therefore, a ₃ and b ₃ values in [Equation 5] [Equation 6] calculated for each measurement chip and A ₃₀ in [Equation 10] [Equation 14] calculated in the wafer plane,
The B ₃₀ value is used for mark anomaly detection evaluation.

A method of calculating the distortion coefficient excluding the abnormal mark will be described with reference to the flowchart of FIG. First, in step 60, with respect to the measurement chip, the difference between the a ₃ and b ₃ values obtained for each chip and the A ₃₀ and B ₃₀ values obtained for all the chips by the least squares method is calculated. The following [Equation 17] [Equation 18] is added to the difference value.
As described above, each coordinate data from the chip center of the mark is applied.

[0052]

DX = | (A ₃₀ −a ₃ ) X _mc Y _mc |

[0053]

DY = | (B ₃₀ −b ₃ ) X _mc Y _mc |

In step 61, [Equation 17] [Equation 18]
The data calculated in step ₁ is compared with the allowable value p ₁ designated in advance by the control computer 19, and the position, mark and distortion coefficient information of a chip having a mark exceeding p ₁ are stored. Also, coefficient equations [Equation 7] to [Equation 14] are recalculated only for chips in which all do not exceed p ₁ to obtain the following [Equation 19] to [Equation 26] (steps 62 and 64).

[0055]

A ₀ = A ′ ₀₀ + A ′ ₀₁ X _w + A ′ ₀₂ Y _w +
_A'03 X _w Y _w

[0056]

A ₁ = A ′ ₁₀ + A ′ ₁₁ X _w + A ′ ₁₂ Y _w +
A _'13 X _w Y _w

[0057]

A ₂ = A ′ ₂₀ + A ′ ₂₁ X _w + A ′ ₂₂ Y _w +
A _'23 X _w Y _w

[0058]

[Number 22] _{a 3} = _{A '30}

[0059]

B ₀ = B ′ ₀₀ + B ′ ₀₁ X _w + B ′ ₀₂ Y _w +
_B'03 X _w Y _w

[0060]

B ₁ = B ′ ₁₀ + B ′ ₁₁ X _w + B ′ ₁₂ Y _w +
B _'13 X _w Y _w

[0061]

B ₂ = B ′ ₂₀ + B ′ ₂₁ X _w + B ′ ₂₂ Y _w +
B _'23 X _w Y _w

[0062]

B ₃ = B ′ ₃₀

By doing so, it is possible to eliminate the abnormal mark and calculate a higher-order distortion of the chip that is more realistic. However, the more information about the chip shift, rotation, and magnification, the more accurate the approximation can be. Therefore, using the relational expressions of [Equation 19] to [Equation 26],
The following processing is performed on a chip (error chip) that exceeds the allowable value p ₁ to determine an error mark. It proceeds continuously to the step 66 when the processing chip determination in step 65 is an error chip. At step 66, [Equation 19]-
Using [Equation 26], the distortion coefficient for the error chip is calculated. Then, the chip coordinates are substituted into the calculation result, the estimated coordinates for each mark are calculated, and the absolute value of the difference between the coordinates and the measurement mark coordinates is obtained and compared with the allowable value p ₂ stored in advance in the control computer. To do.

In the judgment at step 67, the comparison result is the allowable value p.
Marks within ₂ are used for calculation of the distortion coefficient in steps 69 and 71, and those exceeding the allowable value p ₂ are treated as abnormal marks, and the process proceeds from step 67 to step 70.
Not used for tip distortion calculations. In the example described here, the number of marks is four in the chip, the coefficient is shifted,
Since the rotation, the magnification, and the XY term are used as the four marks, when the number of marks decreases, up to a coefficient that can be calculated is calculated according to the number of marks.

Using the distortion coefficient for the chip including the error mark and the distortion coefficient of the normal chip (step 68) obtained in this way, the coefficients of [Equation 7] to [Equation 14] are further calculated in Step 73. The calculation is performed again and the coefficient within the wafer surface is created. By performing exposure using the coefficient thus obtained, it is possible to perform high-precision exposure that is less likely to be affected by the abnormal mark.

By the way, according to such a method, it is possible to perform highly accurate exposure over the entire surface of the wafer, but since approximate calculation is performed for all, when random distortion exists in the drawing result of the lower layer exposure apparatus, The distortion component remains as an error. If there is no mark damage in the process and the mark detection accuracy is high, there is a problem in terms of throughput, but chip alignment that detects the mark for each chip and draws is effective. This is also effective when a highly accurate exposure result is desired even with one chip on the wafer surface. Therefore, the alignment method based on the statistical processing of the present invention described above and the other alignment methods such as the alignment for each chip can be designated in advance by the control computer 19, and the user can perform drawing by switching the designated alignment method. Can manufacture an LSI product with the desired accuracy.

Further, the mark ideal coordinates of each mark can be calculated backward by using the coefficient calculated by the alignment method by the statistical processing of the present invention. In this way, the result of the back calculation is compared with the actually detected mark coordinates. The dispersion value of the comparison result is calculated, and the dispersion value is compared with the allowable value p ₃ stored in advance in the control computer 19. If the dispersion value exceeds the allowable value p ₃ , the random value of the optical reduction exposure apparatus is randomized. Assuming that the distortion component is large, mark detection is performed for each chip,
By adding the function of switching to the alignment method for drawing the chip, it is possible to automatically perform high-precision drawing even on the lower layer having a lower throughput but random distortion.

Although the variable shaping electron beam drawing apparatus has been described here, the present invention is also applicable to a spot type electron beam drawing apparatus. Further, the present invention can be applied to any exposure apparatus as long as it can measure a plurality of marks in a chip and can arbitrarily change the drawing position in the chip. Although the case where the marks are arranged at the four corners of the chip has been described here, distortion in the chip (one shot) of the optical reduction exposure apparatus is caused by a combination of lenses of the optical reduction exposure apparatus. As a result, it is represented by a combination of high-order (third or higher) distortion equations. Therefore,
In order to correct the inside of the chip accurately and to cope with the alignment method by the statistical processing of the present invention, it is necessary to arrange a large number (10 or more) marks in the chip, which is a problem in throughput. Then, JP-A-62-58621
As described in the publication, a method of measuring the strain in the chip in advance can be considered.

However, there are some distortions in the chip due to the dynamic changes of the optical reduction exposure apparatus, and it is not possible to cope with the dynamic changes as they are. In order to cope with the dynamic change of the optical reduction exposure apparatus, it is necessary to measure the strain with high frequency. Therefore, items obtained by removing items such as magnification and rotation from the measurement result are stored as static distortion of the optical reduction exposure apparatus. This static distortion does not need to be measured for each wafer, and may be measured once for each optical reduction exposure apparatus unless the lens is mechanically changed.

The present invention is applied by removing this static distortion component from the mark detection result, and the data of the distortion correction coefficient of the present invention and the stored static distortion component are combined with the on-chip data at the time of drawing. By adopting this method, it is possible to improve the accuracy of alignment within the chip and the throughput.

[0071]

According to the present invention, overlay exposure with a lower layer can be performed with high throughput and high accuracy without manual adjustment.

[Brief description of drawings]

FIG. 1 is a schematic view of an electron beam drawing apparatus used in the method of the present invention.

FIG. 2 is a diagram illustrating an exposure result of a lower layer.

FIG. 3 is a flowchart illustrating a drawing method according to the present invention.

FIG. 4 is an explanatory diagram of an exposure method using a reticle on which a plurality of patterns are formed.

FIG. 5 is a diagram showing a relationship between an exposure order by a light exposure apparatus and a change in magnification of each chip.

FIG. 6 is a flowchart illustrating a method of calculating a distortion coefficient excluding an abnormal mark.

[Explanation of symbols]

1 ... Electron source, 2 ... Rectangular forming diaphragm, 3 ... Forming deflector, 4 ...
Forming lens, 5 ... Blanker, 6 ... Variable forming diaphragm, 7 ... Reduction lens, 8 ... Positioning deflector, 9 ... Forming beam, 10
... Objective lens, 11 ... Backscattered electron detector for mark detection, 1
2 ... Wafer, 13 ... Sample stage, 14 ... Sample stage positioning mechanism, 15 ... Molding deflection control circuit, 16 ... Positioning deflection control circuit, 17 ... Mark detection circuit, 18 ... Sample stage position control circuit, 19 ... Control computer, 20 ... Designed shape of chip to be exposed, 21 ... Mark for measuring chip distortion, 51 ... Reticle for optical reduction exposure apparatus

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Minoru Hojo 882 Ichige, Itamachi, Hitachinaka City, Ibaraki Prefecture Hitachi, Ltd., within the Measuring Instruments Division (72) Inventor Kazuki Onuki, 882 Ichige, Ichima, Hitachinaka City, Ibaraki Prefecture Hitachi Ltd., Measuring Instruments Division (72) Inventor Hiroyuki Ito, 882 Ichige, Ichige, Hitachinaka City, Ibaraki Prefecture Hitachi Ltd., Measuring Instruments Division (56) Reference JP-A-6-275496 (JP, A) JP Hei 9 -283404 (JP, A) JP-A-7-283101 (JP, A) JP-A-1-191416 (JP, A) S.M. Okazaki, F .; Mu lai, Y. Takeda, K. Mojiji, E .; Taked a, H.M. Kume, Electron-beam direct writing of n-MOS devices and analys of ofverity and line of thirty-nine years, 1981, 1981, 1981, 1987, .Cl. ⁷ , DB name) H01L 21/027 G03F 7/20 G03F 9/00

Claims (4)

(57) [Claims] 1. An electron beam drawing method for scanning an electron beam on a wafer to draw a desired pattern on a plurality of chips set on the wafer, wherein at least three of the chips formed in the chip are formed. A mark is detected for each of a predetermined number of chips, and from the position of the mark detected for each of the predetermined number of chips and the design position of the mark, the shape distortion of each chip in the wafer surface and the alignment error and the wafer coordinates All the chips while correcting the pattern to be drawn on each of the chips by using the relationship between the wafer coordinates and the shape distortion and array error of the chips obtained in the step And an electron beam drawing method. 2. The electron beam drawing method according to claim 1, wherein the mark is provided at a corner of each of the chips. 3. An electron beam drawing apparatus which scans an electron beam on a wafer to draw a desired pattern on a plurality of chips set on the wafer, wherein at least three of the chips formed in the chip are formed. A detector that detects a mark for each of a predetermined number of chips, a shape distortion of each chip in the wafer plane from the position of the mark and the design position of the mark that are detected for each of the predetermined number of chips by the detector, and A control computer that collectively obtains the relationship between the array error and the wafer coordinates by statistical processing is provided, and the shape distortion of the chips obtained by the control computer and the relationship between the array error and the wafer coordinates are used for each of the chips. An electron beam drawing apparatus, which draws a pattern on all chips while correcting a pattern to be drawn. 4. The electron beam drawing apparatus according to claim 3, wherein the mark is provided at a corner of each of the chips.