JP3474809B2 - DC voltage conversion circuit and integrated circuit using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC voltage conversion circuit for generating a voltage lower than a power supply voltage, and
The present invention relates to a semiconductor integrated circuit using this.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor integrated circuits has been remarkably improved. In a gigabit class semiconductor memory, hundreds of millions of semiconductor elements are included in one chip, and in a 64-bit microprocessor, millions to 1,000 parts are included in one chip. Tens of thousands of semiconductor devices are integrated. The improvement in the degree of integration is achieved by the miniaturization of elements, and 1G bit DRAM (Dynamic Rand)
In an om access memory), a MOS transistor having a gate length of 0.15 μm is used, and when the degree of integration is further increased, a MOS transistor having a gate length of 0.1 μm or less is used.

In such a fine MOS transistor, deterioration of transistor characteristics due to generation of hot carriers and TDDB (Time Dependent Die1ectric Breakdow) are caused.
Insulation film breakdown due to n) occurs. Further, in order to suppress the decrease in the threshold voltage due to the shortened channel length, if the impurity concentration in the substrate region or the channel region is increased, the junction breakdown voltage between the source and drain is lowered.

In order to maintain the reliability of these fine elements, it is effective to lower the power supply voltage. That is, by weakening the horizontal electric field between the source and drain, generation of hot carriers is prevented, and by weakening the vertical electric field between the gate and bulk, TDDB is prevented. Further, by lowering the power supply voltage, the reverse bias applied to the junction between the source and the bulk and between the drain and the bulk is reduced, and the withstand voltage is reduced.

On the other hand, in portable information equipment, which has been remarkably expanding in the market in recent years, a light source having a high energy density represented by a lithium ion battery is mainly used.
However, the voltage of the lithium-ion battery is 3 to 3.6.
There is about V, which is higher than the withstand voltage of the fine MOS transistor, and when applied to a circuit using such a fine transistor, it is necessary to step down the voltage using a DC voltage conversion circuit. The operating time of portable information devices is determined by the power consumption of the power supply system and its components.To use it for a longer period of time, a battery with high energy density, a high-efficiency DC voltage conversion circuit, and an integrated circuit with low power consumption are required. There is. It is desirable to use the stepped down power supply voltage for a baseband LSI that consumes a particularly large amount of power from the viewpoint of reducing the power consumption of the LSI.

FIG. 8 shows a conventional example of a DC voltage conversion circuit integratedly formed in a semiconductor chip. This is to add clock pulses PU and NU having arbitrary duty ratios to a main buffer circuit 100 composed of a p-channel MOS transistor M101 and an n-channel MOS transistor M102, and to output its output OUT to an inductor L3 and a capacitor C3.
The voltage VDD, which is lower than the power supply voltage, is output with high efficiency through the low-pass filter circuit consisting of. The power supply voltage of the buffer circuit 100 is VDDH, the clock pulse P
If the duty ratio of U and NU is R, VDD = (1-
R) VDDH.

Now, VDDH = 3V, R = 2/3, VD
Assuming that the current flowing through the load circuit of D is 300 mA,
When VDD = 1V and the conversion efficiency is 90%, the buffer circuit 1
The current flowing through 00 is 111 mA. Therefore, the MOS transistors M101 and M102 of the buffer circuit 100 are
Since a gate width of several millimeters is required, a pre-buffer circuit is required to drive this. 200
Indicates such a pre-buffer circuit, which is a signal INU composed of M201 to M210 for driving M101.
Is input and a five-stage inverter circuit to which the signal IND composed of M211 to M220 for driving M102 is input.

As described above, by using the DC voltage conversion circuit integrated in the semiconductor chip, the cost can be reduced.
It is possible to improve the reliability of the elements forming the integrated circuit in the semiconductor chip and further reduce the power consumption of the integrated circuit. However, in this type of conversion circuit,
Since the voltage applied to the element forming the conversion circuit becomes equal to the external voltage, there is a problem that a fine element cannot be used due to the breakdown voltage. As a result, there is a problem that it is necessary to use an element having a high breakdown voltage but a low driving capability, the loss increases, and it is difficult to realize a highly efficient DC voltage conversion circuit.

On the other hand, in portable information equipment, not only low power consumption during operation but also low power consumption during standby are required. To reduce the power consumption of the integrated circuit, there is a problem that the operating speed of the device is reduced or the device does not operate when the driving voltage is reduced. To solve this, the threshold voltage of the MOS transistor is reduced with the decrease of the power supply voltage. It has been lowered. However, when the threshold voltage is lowered, the off-leakage current increases, and there is a problem that the power consumption increases when the device is in the standby state. In order to solve this, a method has been proposed in which the voltage of the well in which the MOS transistor is formed is changed between the operating state and the standby state to increase the threshold voltage of the MOS transistor during the standby state.

In this system, in addition to the power supply voltage for driving the integrated circuit, two voltages applied to the p well and the n well are required. It is necessary to generate these voltages on-chip in order not to burden the system.
If these two voltages are created by different DC voltage conversion circuits, a total of three types of DC voltage conversion circuits including the drive voltage are required. Considering the circuits that control these, the circuit scale becomes large and the chip cost Cause an increase in

[0011]

As described above, conventionally, in the semiconductor integrated circuit using the fine element, the DC voltage conversion circuit has been used in order to maintain reliability and reduce power consumption. Therefore, when the conversion circuit is made to be on-chip, there is a problem that the MOS transistors forming the conversion circuit do not have the withstand voltage. Further, if a non-miniaturized element having a low driving capability is used in order to have a withstand voltage, there is a problem that efficiency is reduced. Further, in a system in which the well potential is changed between operating and standby to achieve low voltage operation and low power consumption during standby, a power supply stepped down from a voltage of 3 to 3.6 V from a lithium ion battery. When three types of on-chip DC voltage conversion circuits are used to generate the voltage and the two well voltages, there is a problem that the circuit scale increases and the chip cost increases.

The present invention has been made in consideration of the above circumstances, and an object thereof is to make it possible to lower the voltage applied to an element below an external voltage even when a miniaturized element is used. Another object of the present invention is to provide a DC voltage conversion circuit capable of outputting two types of conversion outputs with the circuit scale of

Another object of the present invention is to provide a semiconductor integrated circuit which uses the above DC voltage conversion circuit to reduce power consumption and cost.

[0014]

(Structure) In order to solve the above problems, the present invention adopts the following structure.

That is, according to the present invention, in a DC voltage conversion circuit for generating a voltage lower than a power supply voltage, a first inverter circuit connected between a first power supply terminal and an intermediate potential terminal, A second inverter circuit connected between a second power source terminal having a lower potential than the first power source terminal and the intermediate potential terminal, and a first low-pass connected to an output terminal of the first inverter circuit. A filter circuit; a second low-pass filter circuit connected to the output terminal of the second inverter circuit; a means for inputting a first drive signal having a predetermined duty ratio to the input terminal of the first inverter circuit; And a means for inputting a second drive signal having a phase opposite to that of the first drive signal to the input terminal of the second inverter circuit.

Here, the following are preferred embodiments of the present invention. (1) The first drive signal is a rectangular wave that oscillates from the first power supply end potential to the intermediate potential, and the second drive signal is a rectangular wave that oscillates from the second power supply end potential to the intermediate potential. (2) An inverter group for generating the first drive signal is connected between the first power source terminal and the intermediate potential terminal, and an inverter group for generating the second drive signal is connected to the intermediate potential terminal and the intermediate potential terminal. Two
Be connected to the power supply end of.

(3) The gates of the p-channel MOS transistors and the gates of the n-channel MOS transistors forming the inverter circuit are not commonly connected, and the gate of the p-channel MOS transistor of the first inverter circuit is connected to the first p-channel MOS transistor. The side drive signal is input to the gate of the n-channel MOS transistor of the first inverter circuit, and
Side driving signal is input, the second p-side driving signal is input to the gate of the p-channel MOS transistor of the second inverter circuit, and the n-channel MO of the second inverter circuit is input.
The second n-side drive signal is input to the gate of the S transistor.

(4) The first p-side drive signal is a rectangular wave that oscillates from the first power supply end potential to the intermediate potential, and the first n-side drive signal swings from the second power supply end potential to the intermediate potential. The second p-side drive signal is a rectangular wave oscillating from the first power source end potential to the intermediate potential, and the second p-side drive signal is oscillating from the second power source end potential to the intermediate potential. It must be a rectangular wave.

The present invention also relates to a semiconductor integrated circuit,
The first rectified output is connected between the DC voltage conversion circuit having the above-mentioned configuration and the first rectified output end that passes through the first low-pass filter and the second rectified output end that passes through the second low-pass filter. A logic circuit whose end is a power supply end and a second rectification output end is a ground end, and a p-channel MOS which constitutes this logic circuit
A first switching circuit for connecting the body region of the transistor to the first power supply terminal or the first rectification output terminal, and the body region of the n-channel MOS transistor forming the logic circuit for the second power supply terminal or the second power supply terminal. And a second switching circuit for connecting to the two rectified output terminals.

(Operation) According to the present invention, since the first inverter circuit and the second inverter circuit are vertically stacked, the voltage applied to the elements constituting these circuits is ½ of the external voltage. Become. In addition, in the two outputs that have been stepped down, the difference between the external voltage and the high voltage side output and the difference between the low voltage side output and the ground voltage become equal. Therefore, even if a miniaturized element is used, the voltage applied to the element can be made lower than the external voltage, and two types of converted outputs can be output with a minimum circuit scale.

[0021]

DETAILED DESCRIPTION OF THE INVENTION The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 is a circuit configuration diagram showing a DC voltage conversion circuit according to the embodiment of FIG. 10 in the figure is a p-channel MOS transistor M.
1, M3 and n-channel MOS transistors M2, M4
It is a main buffer circuit consisting of. That is, the source of M1 is connected to the power supply voltage VDDH, the gate is connected to the signal PU, the drain is connected to the output terminal OUTU, and M1
The source of 2 is connected to the node M, the gate is connected to the signal NU, and the drain is connected to the output terminal OUTU. The source of M3 is connected to the node M, the gate is connected to the signal PD, the drain is connected to the output terminal OUTD, the source of M4 is connected to the ground potential VSS,
The gate is connected to the signal ND and the drain is the output terminal OU
It is connected to TD.

Here, M1 and M2 form a first inverter circuit 11, and M3 and M4 form a second inverter circuit 12. In the first inverter circuit 11, the gates of M1 and M2 are not commonly connected,
Since in-phase drive signals are input to each gate as described later, they function as inverters. The same applies to the second inverter circuit 12.

In the main buffer circuit 10, the signal P
U and NU have the same phase and the same duty ratio, signals PD and ND have the same phase and the same duty ratio, and signal PD has a negative phase relationship with PU and signal ND has a negative phase relationship with NU. Signal P
When U is low level, the signal NU is low level and the signal P
Since D and ND are at high level, M1 and M4 are turned on and M2 and M3 are turned off. Therefore, the output OUTU is V
It is charged to DDH and the output OUTD is discharged to VSS.

When the signal PU is at high level, the signal NU is at high level and the signals PD and ND are at low level.
M1 and M4 turn off and M2 and M3 turn on. Therefore,
The voltage of the node M becomes a value VM obtained by resistance-dividing VDDH by the ON resistances of M2 and M3. As a result, the output OUTU
Are discharged to VM and the output OUTD is charged to VM.

The output OUTU is connected to a first low-pass filter circuit 21 composed of an inductor L1 and a capacitor C1, and the output OUTD is connected to a second low-pass filter circuit 22 composed of an inductor L2 and a capacitor C2. By these filter circuits 20 (21, 22), a constant voltage determined by the duty ratio of the signal PU appears at the outputs VDDU and VDDD of the filter.

Reference numeral 30 is a pre-buffer circuit for driving the main buffer circuit 10. In this example, it is composed of three vertically stacked inverter circuits in which two inverters are stacked between the power supply voltage VDDH and the ground potential VSS. That is, in the vertically stacked inverter circuit including the MOS transistors M21 to M24, the source of M21 is connected to the power supply voltage VDDH, the gate is connected to the signal BINU1, the drain is connected to the node INU3, and M22.
Source is connected to the node M, and the gate is the signal BINU
1 and the drain is connected to the node INU3.

The source of M23 is connected to the node M, the gate is connected to the signal BIND, the drain is connected to the node IND3, and the source of M24 is the ground potential VS.
It is connected to S, the gate is connected to the signal BIND, and the drain is connected to the node IND3.

The nodes INU3 and IND3 are respectively input to the vertically stacked inverter circuit composed of MOS transistors M25 to M28, and the outputs NU and PD of each inverter circuit become the output of the prebuffer circuit 30. The nodes INU3 and IND3 are connected to the MOS transistors M29 to M29.
Each of the inverter circuits 32 is input to the vertically stacked inverter circuit, and the outputs PU and ND of each inverter circuit become the output of the prebuffer circuit 30.

The number of stages of the vertically stacked inverter circuit from the input to the output of the prebuffer circuit 30 is not limited to two. The number of stages is determined according to the gate width determined by the drive current of the main buffer circuit 10. Further, the node M may not be common to the main buffer circuit 10. Further, the node M does not have to be common to all the vertically stacked inverter circuits.

Reference numeral 25 is a stabilizing circuit connected to the node M. The stabilizing circuit 25 is configured by using two resistors or normally-on MOS transistors. Also, a capacitor may be connected for further stabilization. These circuits may be on-chip or may be externally configured with individual elements.

Reference numeral 40 is a level shift circuit with a buffer which is composed of two inverter circuits and a level shifter. That is, the input signal INU is the MOS transistors M41 and M4.
Input to the inverter circuit consisting of 2 and its output BIN
U is input to the level shifter. Also, the input signal IND
Is input to an inverter circuit composed of MOS transistors M43 and M44, and BIND is output from this inverter circuit. The power supply terminals of these inverter circuits are V
It is connected to a power supply voltage VDDL lower than DDH.

The level shifter is composed of p-channel MOS transistors M45, M46 and n-channel MOS transistors M47, M48, M49. The reference potential VREF input to the gate of M48 and the gate voltage VGG of M49.
Controlled by. The power supply terminal of this level shifter is connected to the power supply voltage VDDH, and the signal BINU swinging between VDDL and VSS by the inverter circuit composed of M41 and M42 has a high level of almost V without changing the logic amplitude.
It can be converted into DDH signals BINU1 and BINU2.

As a concrete example, VDDL = 1.5V,
VDDH = 3V, duty ratios TH / T = 2/3 of input signals INU and IND (TH is a high-level time, T is a cycle), and operating waveforms assuming that the on-resistances of M2 and M3 are equal to each other are shown in FIG. Shown in. At this time, the high level of BINU is 1.5V and the low level is 0V. Reference potential VR
The EF is set to the intermediate voltage between them, for example, 0.75V. The gate voltage VGG is set to a voltage at which the MOS transistor M49 operates in the saturation region.

When BINU is 0V, which is lower than VREF, the MOS transistor M47 is in the cutoff state and M48 is in the ON state, so that the output BINU1 of the level shifter is charged and the BINU2 is discharged. BIN
When U is 1.5V, this is higher than VREF, so M
The OS transistor M47 is turned on, the transistor M48 is turned off, and BINU1 is discharged and BINU2 is charged.

By appropriately selecting the gate width of the MOS transistor, the high level of BINU1 can be set to about 3V and the low level of BINU1 can be set to about 1.5V. Therefore, the level shift circuit 40 converts the input voltage swinging between 0 and 1.5V into a swing between 1.5V and 3V.

Input BINU to the pre-buffer circuit 30
1, BIND, the high level of the output PU is 3V, the low level is 1.5V, TH = (2/3) T, NU is PU
Has the same waveform as. Further, the high level of the output PD is 1.5V, the low level is 0V, TH = T / 3, and ND is P.
It has the same waveform as D.

Since VM = VDDH / 2 = 1.5V, the high level of OUTU is 3V, the low level is 1.5V, the high level of OUTD is 1.5V, the low level is 0V, and VDDU = 2V. , VDDD = 1V. Therefore, the difference between VDDH and VDDU is 1V, VDDD
The difference between V and VSS is also 1V, and the two differences are equal.

In this operation, the MOS transistor M
The drain-source voltages of 1 to M4, M21 to M32, and M41 to M49 are all 0 to 1.5 V, and there is no reliability problem even when the drain breakdown voltage falls below 3 V.

Since this circuit has a CMOS structure, when it is integrated using a bulk substrate, especially in a vertically stacked inverter circuit, a MOS transistor forming an upper inverter and an MO transistor forming a lower inverter are formed.
It is necessary to separate the well of the S transistor. In this case, the wells can be separated by forming a triple well structure. In addition, by using a MOS transistor formed on an SOI substrate that does not require well separation, this circuit can be integrated by a simpler manufacturing process.

Further, the filter circuit 20 may be provided outside the chip by using individual elements, or may be integrated and formed on the same chip. Level shift circuit with buffer 4
At 0, the output was taken out from the level shifter BINU1 in order to invert the phase between the upper side and the lower side.
Instead of NU1, the output may be taken out from BINU2 and one inverter may be newly inserted on the lower side.

The level shift circuit 4 with a buffer is also provided.
In 0, VDDL lower than the external power supply voltage VDDH was supplied to the power supply ends of the two inverter circuits, but the current flowing through these inverter circuits is extremely small.
VDDL can be easily created from VDDH by resistance division or the like.

Further, in this embodiment, by using the level shift circuit, the drive signal oscillating from VDDH to VM is supplied to the upper inverter circuit in the buffer circuit.
A signal swinging from VSS to VM was input to the lower inverter circuit, but VD was input to the input terminals of both inverter circuits.
You may make it input the signal which oscillates from DH to VSS. In this case, the level shift circuit is unnecessary.

As described above, according to this embodiment, the buffer circuits 10 and 30 constituting the DC voltage conversion circuit are connected to the power source terminal V.
By vertically connecting two elements between DDH and the ground terminal VSS, the voltage applied to the elements forming the respective buffer circuits 10 and 30 can be halved of the external voltage. As a result, it is possible to use a fine element having a low breakdown voltage but a high noise level, and it is possible to realize a highly reliable and highly efficient DC voltage conversion circuit.

Further, each buffer circuit 1 which is vertically stacked
By taking out two output voltages VDDU and VDDD from 0, the difference between the external voltage VDDH and the high voltage side output VDDU can be made equal to the difference between the low voltage side output VDDD and the ground voltage VSS. As a result, in the system in which the well potential is changed between the operating time and the standby time to reduce the power consumption during the low voltage operation and the standby time, the voltage of 3 to 3.6 V from the lithium ion battery is stepped down. A power supply voltage and two well voltages can be easily generated, and a low-cost on-chip DC voltage conversion circuit can be realized.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
3 is a circuit configuration diagram showing a DC voltage conversion circuit according to the embodiment of FIG. The same parts as those in FIG.
The detailed description is omitted.

This embodiment differs from the first embodiment described above in the configuration of the pre-buffer circuit. The pre-buffer circuit 50 of the present embodiment is composed of four vertically stacked inverter circuits in which two inverters are stacked between the power supply voltage VDDH and the ground potential VSS.

That is, the output BIN of the level shift circuit 40
U1 and BIND are input to a vertically stacked inverter circuit composed of MOS transistors M51 to 54, and its output is MO.
It is input to the vertically stacked inverter circuit composed of S transistors M55 to M58, and the output is the MOS transistor M5.
9-M62 is input to the vertically stacked inverter circuit,
This output is input to the vertically stacked inverter circuit composed of MOS transistors M63 to M66, and the output is PU, P
It becomes D. The outputs NU and ND are PU and P, respectively.
It is the same as D.

The number of stages of the vertically stacked inverter circuit from the input to the output of the prebuffer circuit 50 is not limited to four. The number of stages is determined according to the gate width determined by the drive current of the main buffer circuit 10. Also, node M
Need not be common with the main buffer circuit 10. Further, the node M does not have to be common to all the vertically stacked inverter circuits.

Also in the present embodiment, the operation shown in FIG. 2 can be realized, and the MOS transistors M1 to M1.
The drain-source voltages of M4, M41 to M49, and M51 to M66 are all 0 to 1.5 V, and reliability problems do not occur even when the drain breakdown voltage falls below 3 V. Therefore, the same effect as that of the first embodiment can be obtained.

(Third Embodiment) FIG. 4 shows a third embodiment of the present invention.
3 is a circuit configuration diagram showing a DC voltage conversion circuit according to the embodiment of FIG. The same parts as those in FIG.
The detailed description is omitted.

The difference between this embodiment and the first embodiment is the configuration of the pre-buffer circuit. The pre-buffer circuit 60 of the present embodiment is composed of four vertically stacked inverter circuits in which two inverters are stacked between the power supply voltage VDDH and the ground potential VSS.

That is, the output BIN of the level shift circuit 40
U2 and BIND are input to the vertically stacked inverter circuit composed of MOS transistors M51 to M54, and the output is M
It is input to the vertically stacked inverter circuit composed of the OS transistors M55 to M58, and the output is the MOS transistor M.
It is input to the vertically stacked inverter circuit composed of 59 to M62.

Then, the MOS transistors M59 to M6
The outputs of the vertically stacked inverter circuit composed of 2 become PD and ND, and drive the lower MOS transistors M3 and M4 of the main buffer circuit 10. Also, PD and ND are MO
It is input to the vertically stacked inverter circuit composed of S transistors M63 to M66, and the outputs thereof are PU and PD, and the MOS transistor M1 on the upper side of the main buffer circuit 10 is provided.
And drive M2.

As a concrete example, VDDL = 1.5V,
FIG. 5 shows operation waveforms on the assumption that VDDH = 3V, duty ratios TH / T = 2/3 of the input signals INU and IND, and on resistances of M2 and M3 are equal. PU high level is 3V, low level is 1.5V and TH = (2/3)
The high level of T and NU is 1.5V, the low level is OV and TH = (2/3) T, the high level of PD is 3V, the low level is 1.5V and TH = T / 3, and the high level of ND is The voltage is 1.5V, the low level is 0V, and TH = T / 3.

When PU is at a low level of 1.5 V,
Since NU is 0V, PD is 3V, and ND is 1.5V,
M1 and M4 of the main buffer circuit 10 are turned on, M2
And M3 are off. Therefore, OUTU becomes a high level of 3V and OUTD becomes a low level of 0V.
When PU is high level 3V, NU is 1.5V,
Since PD is 1.5V and ND is 0V, M1 and M4 of the main buffer circuit 10 are turned off.

At this time, since the current supply to the inductor L1 is stopped, the voltage of OUTU drops from 1.5V to about 1V due to the nature of the inductor, and M2 is turned on. Further, since the current is not drawn from the inductor L2, the voltage of 0UTD rises from 1.5V to about 2V due to the nature of the inductor, and M3 is turned on. As a result, the voltage VM of the node M becomes stable.

After that, due to the resonance operation of the filter circuits 21 and 22, OUTU rises to a voltage slightly higher than 1.5V, and OUTD falls to a voltage slightly lower than 1.5V. As a result, the voltage V passed through the filter circuits 21 and 22
DDU is about 2V and VDDD is about 1V. Therefore,
The difference between VDDH and VDDU is 1V, the difference between VDDD and VSS is 1V, and the two differences are equal.

In this embodiment, the drain-source voltages of the MOS transistors M1 to M4 are 0 to 2V, and the drain-source voltages of M41 to M49 and M51 to M66 are 0 to 1.5V, respectively. Even if the breakdown voltage is lower than 3V, the reliability problem does not occur.
Then, the voltages VDDU (2V) and VDDD (2V) can be generated from the power supply voltages VDDH (3V) and VSS (0V), and the same effect as that of the first embodiment can be obtained.

In the pre-buffer circuit 60, the output of the third stage of the vertically stacked inverter circuit drives the MOS transistors M1 and M4, and the output of the fourth stage drives the MOS transistors M2 and M3. Good. The number of stages of the vertically stacked inverter circuit from the input to the output of the prebuffer circuit 60 is not limited to four. The number of stages is determined according to the gate width determined by the drive current of the main buffer circuit 10. The node M does not have to be the same as the main buffer. Further, the node M does not have to be common to all the vertically stacked inverter circuits.

(Fourth Embodiment) FIG. 6 shows a fourth embodiment of the present invention.
3 is a circuit configuration diagram showing a semiconductor integrated circuit according to the exemplary embodiment of FIG.

Reference numeral 70 in the figure denotes a DC voltage conversion circuit, which is, for example, the DC voltage conversion circuit of the first embodiment shown in FIG. 1 except the low-pass filter circuits 21 and 22. OUTU, OU by inputting IND
Output TD. Further, instead of inputting the input signals INU and IND, a pulse generation circuit that generates an arbitrary duty ratio may be incorporated.

Reference numeral 20 is a filter circuit composed of the low-pass filter circuits 21 and 22 as in the first embodiment.
Output VDDU to UTU, VD to input OUTD
Output DD. Reference numeral 80 denotes a logic circuit having a p-channel MOS transistor and an n-channel MOS transistor, which operates using the power supply voltage VDDU as the power supply voltage and VDDD as the ground voltage. In addition, M that constitutes the logic circuit 80
The body region of the OS transistor is separated from VDDU and VDDD.

P-channel MOS forming the logic circuit 80
As the voltage VN of the body region of the transistor,
VDDH or VDDU is provided by the transistors M91 and M92. That is, the source of M91 is VDD
It is connected to U, the gate is connected to the signal SL, the drain is connected to VN, the source of M92 is connected to VDDH, the gate is connected to the inverted signal BSL of the signal SL, and the drain is connected to VN.

Further, as the voltage VP of the body region of the n-channel MOS transistor forming the logic circuit 80,
VDDD by MOS transistors M93 and M94
Alternatively, VSS is given. That is, the source of M93 is V
Connected to SS, gate is connected to signal SL, drain is connected to VP, source of M94 is connected to VDDD, gate is connected to signal BSL, drain is VP
It is connected to the.

When the logic circuit 80 is in operation, SL is set to low level. At this time, since M91 and M94 are turned on and M92 and M93 are turned off, VN = V
DDU, VP = VDDD, and the threshold voltage of the MOS transistor forming the logic circuit 80 becomes the threshold voltage VT0 when the substrate bias is not applied. When the logic circuit 80 is in the non-operation state, SL is set to the high level. At this time, M91 and M94 are turned off, and M92 and M94 are turned off.
Since 93 is turned on, VN = VDDH, VP = V
SS, the threshold voltage of the MOS transistor forming the logic circuit 80 becomes the threshold voltage VT when the substrate bias is applied.

Since | VT |> | VT0 |, the absolute value of the threshold voltage becomes small when the logic circuit 80 operates, and high-speed operation at a lower voltage is possible, and the logic circuit 80 does not operate. In the state, the absolute value of the threshold voltage is increased, and useless leak current can be reduced.

FIG. 7 shows a specific example of the logic circuit 80. In this figure, only two M81 and M82 of the plurality of p-channel MOS transistors are shown, and
Only two of M83 and M84 among OS transistors are shown. The sources of M81 and M82 are connected to VDDU, the bodies are connected to VN, the sources of M83 and M84 are connected to VDDD, and the bodies are connected to VP. When the logic circuit 80 is formed on the bulk substrate, VN
Is the n-well voltage and VP is the p-well voltage.

When the logic circuit 80 is formed on the SOI substrate and has a body potential, VN is the body potential of the p-channel MOS transistor and VP is the body potential of the n-channel MOS transistor. Further, when the body potential is not taken by SOI, an n well and a p well are formed on the support substrate, VN is an n well voltage, and VP is a p well voltage. In this case, a p-channel MOS transistor is formed on the insulating film within the range of the n-well, and an n-channel MOS transistor is formed on the insulating film within the range of the p-well.

The DC voltage conversion circuit 70 in this embodiment may be formed on the same chip as the logic circuit 80. Furthermore, the present invention is effective when the filter circuit 20 is formed on the same chip.

The present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0072]

As described above in detail, according to the present invention, the first inverter circuit and the second inverter circuit are vertically stacked, so that the voltage applied to the elements constituting these circuits is the same as the external voltage. It can be reduced to 1/2. Moreover, the difference between the external voltage and the output on the high voltage side can be made equal to the difference between the output on the low voltage side and the ground voltage in the two outputs that have been stepped down. Therefore, even if a miniaturized element is used, the voltage applied to the element can be made lower than the external voltage, and two types of converted outputs can be output with a minimum circuit scale. Further, by constructing a semiconductor integrated circuit using this DC voltage conversion circuit, it is possible to reduce power consumption and cost.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a DC voltage conversion circuit according to a first embodiment.

FIG. 2 is a timing chart for explaining an operation in the first embodiment.

FIG. 3 is a circuit configuration diagram showing a DC voltage conversion circuit according to a second embodiment.

FIG. 4 is a circuit configuration diagram showing a DC voltage conversion circuit according to a third embodiment.

FIG. 5 is a timing chart for explaining an operation in the third embodiment.

FIG. 6 is a circuit configuration diagram showing a semiconductor integrated circuit according to a fourth embodiment.

FIG. 7 is a circuit configuration diagram showing a specific example of a logic circuit used in a fourth embodiment.

FIG. 8 is a circuit configuration diagram showing a conventional DC voltage conversion circuit.

[Explanation of symbols]

10,100 ... Main buffer circuit 20 ... Low-pass filter circuit 25 ... Stabilization circuit 30, 50, 60, 110 ... Pre-buffer circuit 40 ... Level shift circuit with buffer 70 ... DC voltage conversion circuit 80 ... Logic circuit M1 to M94 ... MOS transistors C1 to C3 ... Capacitor L1, L3 ... Inductor

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H02M 3/155

Claims (4)

(57) [Claims] 1. A first inverter circuit connected between a first power supply end and an intermediate potential end, a second power supply end having a lower potential than the first power supply end, and the intermediate potential end. A second inverter circuit connected in between, a first low-pass filter circuit connected to the output terminal of the first inverter circuit, and a second
Second low-pass filter circuit connected to the output terminal of the inverter circuit, means for inputting the first drive signal having a predetermined duty ratio to the input terminal of the first inverter circuit, and input to the second inverter circuit A DC voltage conversion circuit, characterized in that it comprises a means for inputting a second drive signal having a phase opposite to that of the first drive signal at the end. 2. A first drive signal is a rectangular wave that oscillates from a first power source end potential to an intermediate potential, and a second drive signal is a rectangular wave that oscillates from a second power source end potential to an intermediate potential. The DC voltage conversion circuit according to claim 1, wherein 3. An inverter group for generating a first drive signal is connected between a first power source terminal and the intermediate potential terminal, and an inverter group for generating a second drive signal is the intermediate group. The DC voltage conversion circuit according to claim 1, wherein the DC voltage conversion circuit is connected between the potential terminal and the second power source terminal. 4. The DC voltage conversion circuit according to claim 1, a first rectified output terminal via a first low-pass filter, and a second rectified output via a second low-pass filter. A logic circuit connected between the first rectification output end and the second rectification output end as a power supply input end and a ground end, and a body region of a p-channel MOS transistor forming the logic circuit. A first switching circuit for connecting to a power supply end or a first rectification output end of the same, and a body region of an n-channel MOS transistor forming the logic circuit is connected to a second power supply end or a second rectification output end. And a second switching circuit for operating the semiconductor integrated circuit.