JP3474938B2 - Absolute encoder - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a serial code represented by a binary code of 0 and 1 (referred to as a binary serial code in this specification). Related to the absolute encoder. 2. Description of the Related Art Conventionally, an absolute value encoder has used a code plate for arranging a plurality of tracks having different numbers of slits to form a binary code or the like having a desired number of bits. Therefore, there is a problem that the number of tracks increases and it is difficult to reduce the size of the absolute value encoder. In view of this, an absolute value encoder using an M-sequence random number code and providing a code plate in which a binary serial code is arranged on a single track has been proposed. This type of absolute value encoder has a 2 ⁿ number of divisions corresponding to a desired resolution.
Hex serial code is engraved on the code plate in the form of a slit or the like, and n
In this configuration, the absolute position data is obtained by reading the code string with the number of detecting elements, so that a reading error occurs in the detection value in the boundary area (unstable area) of the divided value (minimum reading unit) of the binary serial code. The problem that occurs. In order to solve this problem, two sets of n detection elements are prepared by dividing them into groups A and B, and the detection elements of group A and the detection elements of group B are arranged with a phase difference. For the purpose of discriminating an area (unstable area), an incremental code track divided into twice the serial code, ie, 2 × 2 ⁿ , is separately provided on the code plate, and this incremental code is detected by another detecting element. Using the results, select a stable region of the detection value of the detection element of the group A or the group B,
A configuration for obtaining a detection value without a reading error is known. [0005] As described above, in the conventional absolute value encoder in which a single track is provided with a binary serial code, in order to obtain absolute position data without reading errors,
A 2 × 2 ⁿ divided incremental code must be provided on a separate track from the 2 ⁿ binary serial codes, and a complex area for determining a stable area based on the read incremental code is required. However, there is a problem that a complicated data conversion circuit is required. In this case, since the number of divisions of the incremental track to be provided is twice the number of divisions of the serial code, the pitch of slits formed in the code plate is reduced to half. In general, when the pitch of the slits becomes narrow, the distance between the code plate and the detection element must be reduced, which imposes a mechanical limitation, making it difficult to realize a small size and high resolution. An object of the present invention is to provide an absolute encoder which reads a plurality of codes from a code plate provided with a binary serial code and outputs absolute position data indicating the absolute position of the read position. In order to obtain the absolute position data of the 4N division, instead of forming the track of the binary serial code of the 4N division and the incremental track of the 2 × 4N division for discriminating the boundary area on the code plate, two different N are used.
Forming a divided binary serial code on a code plate, providing an absolute value encoder with few mechanical restrictions and no reading error, and utilizing the features of two different serial codes,
An object of the present invention is to provide an absolute value encoder capable of generating an incremental signal based on a signal detected from these two serial codes. A feature of the present invention for solving the above-mentioned problem is that a plurality of consecutive codes are read from a code plate provided with a binary serial code and absolute position data is output. In the 4N-divided absolute value encoder, first and second code tracks are provided on a code plate, and first and second detectors for reading absolute position data from these code tracks are provided. . In the first code track, the read results of all K + 1 consecutive codes (here, an integer value of 2 or more satisfying 2 ^{K -1} <N ≦ 2 ^K ) have different contents, and
The first N-divided binary serial code created under the condition that the sum of any two read binary values does not add up to 2 ^{K + 1} −1. On the other hand, in the second code track, a second N-ary binary serial code and an exclusive-OR of the N-divided incremental signal are used to create a second N-ary binary serial code.
Are divided by N-divided binary serial code. The first and second N-divided binary serial codes thus created have the following relationship.
In other words, although the binary serial codes are of the same division, the serial codes themselves are different, and the two serial codes have their respective changing points not overlapping each other. That is, at the changing point (edge) of one of the serial codes, The other serial code has the characteristic that the signal is in the stable region. By the way, exclusive OR of the signals X, Y, and Z (the operation symbol is denoted by * in this specification)
It is generally known that when X * Y = Z holds, Y * Z = X and Z * X = Y also hold. Therefore, the second N-divided binary serial code is created by calculating the exclusive OR of the first N-divided binary serial code and the incremental signal. To generate an incremental signal by arranging the detection element at the position of the second code track and arranging the detection element at the position opposite to the second code track, and calculating the exclusive OR of the detection signals from the respective detection elements. Can be. In the present invention, the first and second N-divided binary serial codes are detected as described above, and an incremental signal is output by providing circuit means for calculating an exclusive OR of these. The first and second N-divided binary serial codes are the same-divided binary serial codes, but the serial codes themselves are different, and the two serial codes have their changing points different from each other. Non-overlapping, that is, at one serial code transition point, the other serial code is in the stable region, and the exclusive logical conjunction of the corresponding codes of these two sets of N-divided binary serial codes. Therefore, since the incremental signal obtained by the calculation is synchronized with the change point of the serial code, detection without reading error can be performed without using a complicated conversion circuit. Further, although the obtained absolute position data is divided into 4N divisions, the serial code formed on the code plate can be divided into N divisions. The distance from the detection element can be increased, and small size and high resolution can be realized. An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram showing the configuration of a rotary absolute value encoder 1 according to the present invention. The absolute value encoder 1 includes a code plate 2 fixed to a rotating shaft of a detection object (not shown), a light source 3 disposed on one side of the code plate 2, and an absolute position data read by the code plate 2. Detection elements SA1 to SA6 for optically reading the code of the code plate 2 by receiving light from the light source 3 through a slit representing a binary cyclic serial code formed on the code plate 2 as described later. And a reading device 4 having SB1 to SB5. As shown in FIG. 2, in the present embodiment, the code plate 2 is provided with a first code track T1 and a second code track T2 concentrically. T2 is divided into eight equal parts. Each of the divided segments is configured such that a white portion (light-transmitting portion) is "1" and a black portion (light-shielding portion) is "0" to optically display eight binary cyclic serial codes. ing. Further, since the present embodiment is a rotary type absolute value encoder, these binary serial codes need to be circulated. The first code track T1 to the attached is in which eight divisions of the code plate 2 ⁽² 2 <8 ≦ 2 ³ from K = 3) first of 2
The hexadecimal cyclic serial code FA is obtained as follows: “Absolute position data indicated by any consecutive K + 1 = 4 codes have different contents, and the sum of any two read binary values is 2 ^{3 + 1} −
Does not become 1. In the present embodiment, an example created under the condition "" is [11110100]. This first binary cyclic serial code FA is a white portion (light transmitting portion) on the first code track T1 of the code plate 2 of the absolute value encoder 1.
Is formed as a slit with “1” as a black portion (light shielding portion) as “0” (see FIG. 2). On the other hand, in the second code track T2 of the code plate 2, a binary serial code obtained by taking the exclusive OR of the first binary cyclic serial code FA and the same number of incremental codes is stored in the second code track T2. Attached as a binary cyclic serial code FB. In the present embodiment, an incremental code [10101010] starting from "1" is prepared, and the exclusive code of the incremental code and the first binary cyclic serial code FA is ORed to obtain a serial code [0101110]. Which is the second binary cyclic serial code FB. When an incremental code starting from "0" is used, the result of [10100001] is obtained, but this can be used at all. First and second binary cyclic serial codes FA, F
B is arranged on each of the code tracks T1 and T2 with the following correspondence (see FIG. 2). T1 (FA) 1111010 0 T2 (FB) 01101110 The reading device 4 is composed of detecting elements SA1 to SA6 and detecting elements SB1 to SB5, and each detecting element SA1 to SA6 for reading the code of the first code track T1.
Are arranged along the first code track T1 as shown in FIG. Here, detection elements SA1, SA2, SA
4. The output from SA6 is used as a signal constituting the first absolute position data. On the other hand, the second code track T2
Each of the detection elements SB1 to SB5 for reading the sign of
As shown in FIG. 2, they are arranged along the second code track T2, and outputs from the detection elements SB1, SB2, and SB5 are used as signals constituting second absolute position data. FIG. 3 is an expanded view showing the arrangement intervals of the detection elements when the minimum reading unit of each code track is λ. Here, a general example of the arrangement of the detection elements will be described with reference to FIGS. FIG. 4 shows a basic arrangement of the detecting elements when K ( ^K satisfying 2 ^{K -1} <N ≦ 2 K, K is an integer of 2 or more) is minimum, that is, K = 2. The detection element SA1 is arranged at an arbitrary position on the first code track T1, and the detection element SB1 is placed on the second code track T2 opposite to the position.
Is arranged. Pitch λ than detection elements SA1 and SB1
/ 2, the detecting elements SA2 and SB2 are arranged
The detecting element S is further displaced from the position by a pitch of 3 / 4λ.
A3 and SB3 are arranged. The detection elements SA4 and SB4 are arranged at a position shifted from the detection element SA4 by a pitch of λ / 2, and the detection element SA5 is arranged at a position shifted by λ / 2 from the detection element SA4. That is, in this case, the first detector SA is K + 3
= 5 detection elements SA1 to SA5, and the second detector SB is composed of K + 2 = 4 detection elements SB1 to SB4. Then, the detecting elements SA1 to SA4 and S
B1 to SB4 are used to generate two incremental signals having a phase difference λ / 4 divided into 2N pieces.
The detecting elements SA1, SA3 and SA5 are connected to the first code track T
The absolute position data is read from the code of 1 and the detection element SB
1, SB2 and SB4 are used to read the absolute position data from the code of the second code track T2. When the value of ^K that satisfies 2 ^K-1 <N ≦ 2 ^K increases, the first code track T1 is pitched with respect to the detection element SA5 and the second code track T2 is pitched with respect to the detection element SB4. The detecting element is shifted by 1 according to the value of K at a position shifted by mλ.
What is necessary is just to add and arrange each pair. This will be described with reference to FIG. In FIG. 5, when the right direction is (+) and the left direction is (−) in FIG. 5, 1 ≦ m and m ≦ −2. However,
When m = −2, the detection element groups are densely packed. Therefore, it is actually preferable that m ≦ −3. The additional arrangement of the detection elements is as follows: m = 1, 2, 3,
, Or m = −3, −4, −5,... May be added only in one direction, but the basic element group is arranged at the center where the light amount distribution is relatively stable. Then, m = −3, 1, −4, 2, −5, 3,.
・ ・ Additional detection element
It is preferably used as a detecting element for reading the absolute position data from the code of each track. The output from each of the detection elements arranged as shown in FIG. 2 is shaped by the waveform shaping circuit 5 shown in FIG. 1, and output as output signals DA1 to DA6 and DB1 to DB5. FIG. 6 shows the waveform of the output signal obtained by each detection element when the code plate 2 makes one rotation. Returning to FIG. 1, the incremental signal I
In order to obtain A and IB, output signals DA2 to DA5 and DB
2 to DB5 are input to a logical operation circuit 6 including Ex-OR gates G1 to G6. Ex-OR gate G1
To G4 output operation output signals DG1 to DG4. The operation output signal DG3 from the Ex-OR gate G6,
In response to DG4, an incremental signal IA is obtained.
The operation output signals DG1, DG2 are output from the x-OR gate G5.
, Another incremental signal IB is obtained. The waveforms of the operation output signals DG1 to DG4 and the incremental signals IA and IB are shown in FIG. Here, if the operation of exclusive OR of α and β is generally expressed as α * β, an incremental signal DG1 divided into N = 8 by DA2 * DB2 is obtained, and DA3 * DB3 N = 8 divided incremental signals DG3 shifted by λ / 2 phase from DG1
6 can be obtained from FIG. Furthermore, DG1 * DG
With 2, the incremental signal IB (= DO5) divided into 2N = 16 is obtained. At this time, the four output signals DA2, DB
Looking at the relationship between 2, DA3, and DB3, at the change point (edge) of a given signal, the other three signals are in a stable region where the waveforms are at “H” or “L” level. When these four signals are divided at the changing point of each signal, each divided region has a feature that there is only one changing point. Therefore, any one of the detection elements SA2, SB2, SA3, and SB3 for detecting these four signals is provided at the boundary between the light transmitting portion of the slit of the code plate 2 and the light blocking portion, that is, when the output level is zero. Even if it is in an unstable area where it cannot be determined whether it becomes (L) or 1 (H), erroneous data is not output. Further, 2N = 1 by these four signals.
The incremental signal divided into six is IB (DO
5) Therefore, by detecting the area of another signal based on the incremental signal IB, that is, by switching based on the logic of the incremental signal IB, it is possible to perform detection without reading errors. A set of output signals DA1, DA2, DA4, D detected by the detection elements SA1, SA4, SA6
A6 and another set of output signals DB1, DB2, D detected by the detection elements SB1, SB2, SB3, SB5.
A secretor 7 is provided to select one of B3 and DB5 in response to the level of the incremental signal IB. The secretor 7 includes a first group of input terminals A1 to A
4 and a second group of input terminals B1 to B4, and each output signal is input to these input terminals as shown in FIG. The secretor 7, as shown therein, generally has two inputs An, Bn and a terminal G
Is selected as an output Yn when the level of the incremental signal IB applied to the inverter is "L", and four sets of selection circuits for extracting the input Bn as an output Yn when the level is the reverse. . From the above description, the incremental signal I
When the level of B is “L”, in each selection circuit,
Output signals DA1, DA2, DA4, and DA6 input to the first group of input terminals A1 to A4 are output terminals Y1 and Y6.
2, Y3, Y4 to absolute position data DO1, DO2, D
Output as O3 and DO4. On the other hand, when the level of the incremental signal IB is “H”, the output signals DB1, DB2, DB3, and DB5 input to the second group of input terminals B1 to B4 in each selection circuit are output to the output terminal Y.
1, Y2, Y3, Y4 to absolute position data DO1, DO
2, DO3 and DO4. Here, the output signals DA2, DB2, DB3
As described above, the change points (edges) of the output signals DA2, DB2, and DB3 coincide (synchronize) with the change points (edge) of the incremental signal IB. On the other hand, the output signals DA1, DA4, D
The relationship between A6, DB1, DB5 and the incremental signal IB is based on the output signals DA1, DA4, DA6, DB1, D
Each change point of B5 is out of phase by λ / 4 with respect to the change point of the incremental signal IB, and in the case of the present embodiment, each change point of the output signals DA1, DA4, and DA6 is
The fact that the incremental signal IB exists only in the region of the “H” level and that the output signals DB1 and DB5 change only in the region where the incremental signal IB is the “L” level is the same as the time in FIG. You can see from the chart. In this embodiment, when the incremental signal IB is at "L" level, the output signals DA1, DA4,
Since DA6 is in the stable region and the output signals DB1 and DB5 are in the stable region when the incremental signal IB is at the "H" level, the output signals DA1, DA2, DA4, and DA6 are output when the incremental signal IB is at the "L" level. Output signal DB when IB is at "H" level
1, DB2, DB3, and DB5 are selected by the selector 7 and output as absolute position data DO1 to DO4.
Here, the incremental signal IB is the absolute position data D
Used as O5, 2N = 16 divided absolute position data DO1 to DO5 are obtained. In which case the level of the incremental signal IB is used to determine which of the first group of input terminals and the second group of input terminals to use is determined by the binary cyclic serial code used. The selection logic in the selector 7 may be appropriately changed depending on the serial code to be used. Further, by the following logical operation in the EX-OR gate G6, DG3 * DG4, an incremental signal IA divided into 2N = 16 is obtained. Since the incremental signal IA has a λ / 4 phase shift with respect to the incremental signal IB, E
By the operation IA * IB in the X-OR gate G7, 4
An incremental signal DO6 divided into N = 32 is obtained. By this incremental signal DO6, the resolution of 2N = 16 absolute position data previously obtained is 2
As a result, 4N = 32 absolute position data as shown in FIG. 7 are obtained. In the above embodiment, the optical rotary encoder having a circular code plate has been described as an example. However, a linear encoder having a linear code plate, a magnetic encoder that magnetically detects a code, or the like is used. Needless to say, the present invention can be similarly applied. In the above embodiment, the description has been given of the 2 ³ split, the present invention is not limited thereto, 2 ⁴ split, 2 ⁵ divided and applied in the same manner in the case of ..., similar Ru it is possible to obtain the effect. According to the present invention, as described above, an absolute value encoder which reads a plurality of bits of a code from a code plate provided with a binary serial code and outputs absolute position data indicating an absolute position is provided. Therefore, it is possible to easily configure an absolute value encoder that prevents all the read absolute position data from overlapping, and to use a serial code having a resolution lower than the resolution of the obtained absolute position data. Since it is sufficient to form the absolute value encoder on the code plate, the detection distance between the code plate and the detection element can be widened, and an absolute value encoder with few mechanical restrictions can be realized. Further, by making use of the features of the two sets of serial codes attached to the two tracks of the code plate, an incremental signal is created from the signals detected from these serial codes. , It is also possible to detect the code attached to the track without reading errors.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of an embodiment of an absolute value encoder according to the present invention. FIG. 2 is a diagram showing an arrangement relationship between a code plate and a detection element of the absolute value encoder shown in FIG. FIG. 3 is an explanatory view showing the detection elements in an expanded manner to explain an arrangement pattern of the detection elements with respect to the code plate shown in FIG. 2; FIG. 4 is an explanatory diagram for explaining a basic arrangement of a detection element according to the present invention. FIG. 5 is an explanatory diagram for explaining a general arrangement of detection elements according to the present invention. FIG. 6 is a time chart showing waveforms of signals of respective parts when the code plate of FIG. 1 is rotated once. FIG. 7 is a view showing 32 absolute position data obtained in the configuration of FIG. 1 ;

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Claims (1)

(1) In a 4N-division absolute value encoder for reading a plurality of codes from a code plate to which a binary serial code is attached and outputting absolute position data, a first code track And a second code track. In the first code track, the read results of all K + 1 consecutive codes have different contents, and the sum of the binary values of any two read results is 2 ^{K + 1} N split created under the condition that not a ^{-1 (2 K-1 <N} ≦ 2 K, K is an integer of 2 or more, N is the even number of 4 or more) is provided a first binary series code , The second code track is provided with an N-divided second binary serial code formed by taking the exclusive OR of the first binary serial code and the N-divided incremental code. A first code track and / or a second code track. An absolute value encoder comprising: detector means for reading absolute position data from the first code track; and means for reading a required code from the first code track and the second code track to create an incremental signal. .