JP3475686B2 - IC tester and signal generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generating device which requires high time accuracy, and more particularly, to applying a test signal to an IC under test and fetching a response signal from the IC under test to obtain the response signal. The present invention relates to an IC test apparatus for making a pass / fail judgment.

[0002]

2. Description of the Related Art Conventionally, an IC tester has been used for testing an IC. The IC test apparatus determines whether the response signal is good or bad by applying a test signal to the IC under test and capturing the response signal from the IC under test.

By the way, high time accuracy is required for generation of a test signal applied to an IC under test and determination of a response signal of the IC under test.

A conventional IC test apparatus will be described below.

FIG. 15 is a schematic configuration diagram of a conventional IC test apparatus.

The conventional IC test apparatus shown in FIG. 15 has pin circuits 7 _{1 to} 7 _N respectively connected to pins to be tested of the IC 6 under test (hereinafter, these are also referred to as pin circuits 7).
And a pattern generator circuit 9 that outputs data necessary for generating a test signal at a timing specified by a test clock cycle data generated by a test cycle generation circuit 71 described later. , Are provided.

The pin circuit 7 includes a test cycle generation circuit 71 for generating test clock cycle data, an edge generation circuit 72, a waveform generation circuit 73, a driver 74, an analog comparator 75, and a comparison / determination circuit 76. I have it.

The edge generation circuit 72 uses the test clock cycle data generated by the test cycle generation circuit 71 and the original oscillation 8
An edge clock signal is generated based on the clock signal from.

The waveform generation circuit 73 includes a test cycle generation circuit 71, an edge generation circuit 72, and a pattern generation circuit 9.
A test signal is generated based on the signal from.

The driver 74 amplifies the test signal generated by the waveform generation circuit 73 to a predetermined voltage level, and the IC under test is tested.
6 is applied.

The analog comparator 75 is an IC to be tested.
It is determined whether the voltage level of the response signal from 6 is a predetermined value or more.

The comparison / determination circuit 76 compares the signal output from the analog comparator 75 with the data output from the pattern generation circuit 9 to determine the quality of the response signal.

In FIG. 15, the edge generating circuit 72 is set to 1
Although only two are provided, actually three edge clock signals are provided for inputting two edge clock signals to the waveform generation circuit 73 and one to the comparison / determination circuit 76, respectively.

Next, the edge generating circuit 72 will be described in detail.

FIG. 16 is a schematic block diagram of the edge generating circuit 72.

The edge generating circuit 72, as shown in FIG. 16, is a data operation circuit 721, an AND circuit 722, a delay circuit 723, and a flip-flop (FF) circuit 724.
a, 724b, the coincidence detection circuit 725, and the counter 72
6 and.

The data arithmetic circuit 721 generates timing data of the edge clock signal. The timing data is the count data E input to the coincidence detection circuit 725.
(F) ct and delay time data E (f) dly input to the delay circuit 723.

The counter 726 counts the number of pulses output from the original oscillator 8.

The coincidence detection circuit 725 compares the count value of the counter 726 with the count data E (f) ct of the data operation circuit 721 latched by the FF circuit 724b. Then, when both match, a match signal (logical value H at the time of match) is output.

FIG. 18 is a timing chart for explaining the operation of the edge generating circuit 72 for generating the edge clock signal.

In FIG. 18, the original vibration 8 generates pulses at a constant cycle. The counter 726 is counting up according to the pulse of the original vibration 8.

The test cycle generation circuit 71 generates test clock cycle data R (f) according to the number of times the test clock cycle data is output.

Here, when the number of times the test clock cycle data is output is n, R (n) = 3 cycles of the original oscillation, when n + 1, R (n + 1) = 4 cycles of the original oscillation, and when n + t, R.
The test clock cycle data R (f) is changed such that (n + t) = source vibration 3 + t cycles.

The data operation circuit 721 is an AND circuit 72.
According to the clock signal output from 2, the match detection circuit 7
The count data E (f) ct input to 25 and the delay time data E (f) dly input to the delay circuit 723 are output.

Here, the data operation circuit 721 generates the count data E (f) ct in accordance with the test clock cycle data output from the test cycle generation circuit 71.

Here, when the clock signal from the AND circuit 722 is received, the test clock cycle data is R.
In case of (n-1), E ( n ) ct = 2, in case of R (n), E (n + 1 ) ct = 3, and in case of R (n + t), E (n + 1).
+ T) ct = 3 + t, and count data E
(F) ct is changed.

The data arithmetic circuit 721 also generates delay time data E (f) dly indicating a constant delay time.

Here, when the clock signal from the AND circuit 722 is received, E ( n ) dly, E (n + 1 ) dl
y, ..., so that E (n + 1 + t) = 0.5,
Delay time data E (f) dly showing a constant delay time is generated.

Next, the operation of the edge generating circuit 72 will be described.

First, when the clock signal of the AND circuit 722 is input to the data calculation circuit 721, the data calculation circuit 721 causes the count data E (f) to follow the above procedure.
ct, delay time data E (f) dly is output. The count data E (f) ct and the delay time data E (f) dly are
The FF circuit 724b latches once by the clock signal of the AND circuit 722, and then the match detection circuit 7
25 and the delay circuit 723.

Next, the coincidence detection circuit 725 operates as the FF circuit 7.
The count data E (f) ct output from 24b is compared with the count value of the counter 726. Then, when both match, a match signal (logical value H at the time of match) is output.

The coincidence signal is output by the FF circuit 724 in synchronization with the pulse of the original vibration 8 and input to the AND circuit 722. As a result, the pulse of the original oscillation 8 is output from the AND circuit 722 for one clock at the timing when the coincidence detection circuit 725 outputs the coincidence signal.

Next, the delay circuit 723 includes an AND circuit 72.
The clock signal output from 2 is delayed by the time specified by the delay time data E (f) dly output from the FF circuit 724b. As a result, the edge clock signal is output.

By doing so, the edge clock signal is generated in a cycle corresponding to the test clock cycle data of the test cycle generating circuit 71.

In the edge generating circuit 72 shown in FIG. 16, when the clock signal is output from the AND circuit 722, the delay time data E (f) dly output from the FF circuit 724b is output as shown in FIG. Although switching to the next one, the delay circuit 723 holds the delay time data E (f) dly before switching until the clock signal of the AND circuit 722 passes through the delay circuit 723.

As described above, the edge generation circuit 7
2 outputs the edge clock signal to the waveform generation circuit 73.
One is provided to the comparison and determination circuit 74, and three are provided for inputting each. Each edge generation circuit 72
Is designed to output edge clock signals of the same cycle at different timings (phases).

Next, the waveform generating circuit 73 will be described in detail.

FIG. 17 is a schematic configuration diagram of the waveform generation circuit 73 and the comparison / determination circuit 76.

Here, the edge clock signals 1 to 3 are 3
The edge clock signal output from each of the two edge generation circuits 72 is shown.

As shown in FIG. 17, the waveform generation circuit 73 includes a waveform generation data generation circuit 731 and a delay circuit 7 for deskewing a test signal applied to the IC under test 6.
32a to 732d, logic circuits 733a and 733b each including an AND circuit and an OR circuit, and a flip-flop (F
F) circuit 734.

The waveform generation data generation circuit 731, in accordance with the waveform generation data output from the pattern generation circuit 9,
Output test signal generation data.

The delay circuits 732a and 732c adjust the output timing of the edge clock signal 1 to control the IC under test.
The skew of the test signal applied to 6 is adjusted.

The delay circuits 732b and 732d adjust the output timing of the edge clock signal 2 to control the IC under test.
The skew of the test signal applied to 6 is adjusted.

Next, the operation of the waveform generating circuit 73 will be described.

FIG. 19 is a timing chart for explaining the operation of the waveform generation circuit 73 for outputting the test signal.

First, the waveform generation data generation circuit 731
The test signal generation data is output according to the waveform generation data output from the pattern generation circuit 9.

Here, in the test signal generation data A shown in FIG. 19, the input B and the input D of the logic circuit 733a are logical values H and L, respectively, and the input B and the input D of the logic circuit 733b are logical. When the data has the value L and the logical value H, the logical circuit 733a outputs the logical value L only when the edge clock signal 1 is output from the delay circuit 732a.
Is output . In response to this, the FF circuit 734 operates as shown in FIG.
As shown in, the output signal of the logic circuit 733a (logical value L) is set and the test signal (logical value H) is output.

On the other hand, the logic circuit 733b is the delay circuit 73.
The logic value L is output only when the edge clock signal 2 is output from 2d.

In response to this, the FF circuit 734 operates as shown in FIG.
As shown in, the output signal of the logic circuit 733b (logical value L) is reset and the output of the test signal is stopped (logical value L).

As a result, an RZ (Return to Zero) waveform test signal is output.

As described above, the waveform generation circuit 731 selects the edge clock signal to be passed through the logic circuits 733a and 733b based on the test signal generation data generated by the waveform generation data generation circuit 731, and the selected edge clock signal. A test signal is generated based on

The test signal generated by the waveform generating circuit 73 is amplified to a predetermined voltage level by the driver 74 and applied to the IC under test 6. Normally, a signal for controlling whether the driver is turned on or off is used for the driver 74, but it is omitted here.

Next, the comparison / determination circuit 76 will be described in detail.

As shown in FIG. 17, the comparison / decision circuit 76 has a delay circuit 761, a flip-flop (FF) circuit 762, and a pass / fail comparison circuit 763.

The delay circuit 761 uses the edge clock signal 3
Is delayed for a predetermined time.

The FF circuit 762 latches the response signal of the IC under test 6 sent via the analog comparator 75 in accordance with the edge clock signal 3 output from the delay circuit 761.

The pass / fail judgment circuit 763 compares the level of the response signal latched by the FF circuit 762 with the expected value data sent from the pattern generation circuit 9. Thereby, the quality of the response signal is determined.

[0058]

In the conventional IC test apparatus described above, the original oscillation 8-edge generation circuit 72 (AND circuit 722-delay circuit 723) -waveform generation circuit 73 (delay circuits 732a to 732d-logic circuit 733a, 733b-
The path connecting FF circuit 734) -driver 74-IC6 under test is a path through which a signal with high time accuracy passes in order to apply a test signal to IC6 under test.

By the way, in the above-mentioned conventional IC test apparatus,
In all the pin circuits 7 _{1 to} 7 _n , when the test signals having the same RZ waveform are to be output at the same timing,
The time accuracy between the pin circuits 7 _{1 to} 7 _n varies due to variations in characteristics of devices forming the pin circuits 7 or differences in operating environment such as temperature and voltage.

Therefore, in the conventional IC test apparatus, the skew adjustment data between the pin circuits 7 _{1 to} 7 _n is set in the delay circuits 732 a to 732 d of the waveform generation circuit 73, so that the time accuracy varies. I am adjusting.

For example, as shown in FIG. 20, the test signals which the pin circuits 7 ₁ and 7 ₂ try to output at the same timing are Ts with respect to the skew adjustment time T.
When there is a skew of Kew1 and Tskew2, the delay circuits 732a to 732d are used to adjust so that the test signal is output during the skew adjustment time T.

However, in the above-mentioned conventional IC test apparatus, the delay times set in the delay circuits 732a to 732d cannot be dynamically changed.

Therefore, when the external conditions such as the temperature and the power supply voltage are dynamically changed, the pin circuit 7 is correspondingly changed.
There is a problem that it is not possible to adjust the variation in time accuracy between _{1 to} 7 _n .

Particularly, in the conventional IC test apparatus, a circuit that requires high time accuracy, such as an edge clock generation circuit, is used.
The bipolar ECL is configured so that the time accuracy is not deteriorated (skew between the pin circuits of the test signal applied to the IC under test) under ambient conditions such as ambient temperature and power supply voltage. As a device related to this type of IC test device, an edge generation circuit, a waveform generation circuit, and a comparison / determination circuit are constructed by a bipolar ECL, "1989 International Test Conferenc".
e (Page 558 to 566) ”.

However, in recent years, there has been a tendency to adopt a per-pin architecture in order to increase the number of pins and increase the accuracy, and accordingly, a CMOS device which can be highly integrated several times more than the bipolar ECL is required. A method of configuring a circuit that requires high time accuracy, such as an edge clock generation circuit, has been considered.

However, in the CMOS device, when compared with the bipolar ECL, the signal propagation time of the device fluctuates more than twice as much as the fluctuation of the temperature and the power supply voltage.

Therefore, using a CMOS device,
When a circuit that requires high time accuracy such as an edge clock generation circuit is configured, variations in time accuracy between pin circuits due to changes in external conditions such as temperature and power supply voltage become more significant than ever.

For example, in the conventional IC test apparatus described above, the original oscillation 8-AND circuit 722-delay circuit 723-delay circuits 732a to 732d-logic circuits 733a and 733b.
When the path up to (to be referred to as path A hereinafter) is composed of CMOS devices, the adverse effect on the accuracy of the IC test apparatus is as follows.

The propagation delay time of each gate of the path A is AN
1 ns in the D circuit 722, 2 ns in the offset of the delay circuit 723, 3 ns in the delay time of the delay circuit 723, 2 ns in the offset of the delay circuits 732a to 732d, 10 ns in the delay time set for the skew adjustment, and 2 ns in the waveform generation circuit 73. In that case, the total is 20 ns.

Here, attention is paid to a certain two pin circuits (for example, the pin circuit 7 ₁ and the pin circuit 7 _n ).

When the propagation time of the path A of each of the pin circuits 7 ₁ and 7 _n is 20 ns as estimated above, the pin circuit 7
_It is assumed that the propagation time of the route A of _n actually fluctuates by + 5% from the above estimated time due to the difference in fluctuation of temperature and power supply voltage.

In this case, the pin circuit 7 ₁ and the pin circuit 7 _n
A skew of 20 ns × 0.5% (= 1 ns) will be generated between and.

The IC test apparatus guarantees the time accuracy with the maximum width of the skew. For example, the IC test apparatus guaranteeing 0.5 ns or less exceeds the guarantee range in the above case.

As described above, in the conventional IC test apparatus, the guarantee of the propagation time fluctuation of the signal that requires high time accuracy is taken into consideration even when the external conditions such as the temperature and the power supply voltage dynamically change. Absent.

The present invention has been made in view of the above circumstances, and an object of the present invention is to output timing of an edge clock signal in accordance with a change in propagation time of a path through which a signal having high time accuracy passes. The purpose of the present invention is to provide an IC test apparatus in which skew is reduced by adjusting.

Another object of the present invention is to provide a signal generating device for generating a signal which requires high time accuracy.

[0077]

In order to solve the above problems, an IC test apparatus according to the present invention generates pulse data at a predetermined cycle, and cycle data of an edge clock according to a predetermined standard. For generating the edge clock signal by extracting the pulse of the pulse generating means according to the cycle data generated by the cycle data generating means, and the edge clock generating for the test signal A test signal generating means for generating a test signal to be applied to the IC under test based on the edge clock signal generated by the means, and an IC test apparatus for judging pass / fail of a response signal of the IC under test to the test signal. In the IC test operation, the test
The time variation along the path that a signal travels to produce a signal.
A fluctuation amount measuring means for measuring a motion amount,
Means for measuring the edge of the test signal based on the fluctuation amount.
It is characterized in that the output timing of the clock generating means is adjusted .

According to the present invention, in order to output the test signal from the test signal generating means at a predetermined timing, the variation amount of the propagation time of the signal on the path along which the signal for generating the test signal propagates. The output timing of the edge clock signal from the test signal edge clock generation means is adjusted according to the above, so that when the external conditions such as temperature and power supply voltage change dynamically, the change of the propagation time of the path caused by the change occurs. It is possible to prevent the output timing of the test signal from shifting due to the fluctuation.

Here, the path through which the signal for generating the test signal propagates means, for example, that the pulse of the pulse generating means extracted according to the cycle data of the cycle data generating means passes through the edge clock signal It is a route until it becomes a test signal.

Further, the fluctuation amount measuring means measures the closed loop that oscillates and the oscillation cycle of the closed loop, which is formed in a circuit configuration substantially the same as the path through which the signal for generating the test signal propagates. And the output of the edge clock signal from the edge clock generating means for the test signal is corrected according to the difference between the oscillation cycle measured by the first cycle measuring means and the reference cycle prepared in advance. Do
It is preferable.

Further, in the IC test apparatus of the present invention, the judgment edge clock generating means for generating the edge clock signal by extracting the pulse of the pulse generating means according to the cycle data generated by the cycle data generating means, and the judgment Pass / fail determination means for determining pass / fail of the response signal of the IC under test according to the edge clock signal generated by the edge clock generation means for use, and the pass / fail determination during the IC test operation.
To measure the amount of time fluctuation in the path through which the signal for
The determination variation amount measuring means for determining
The measuring means, based on the variation amount, the determination edge
The output timing of the clock generator is adjusted.
May be.

By doing so, when the external conditions such as the temperature and the power supply voltage are dynamically changed, the change in the propagation time of the path through which the signal for making the pass / fail judgment propagates caused by the change causes the pass / fail. It is possible to prevent the determination timing from shifting.

Further, the signal generating apparatus of the present invention includes pulse generating means for generating a pulse at a predetermined cycle, cycle data generating means for generating cycle data of an edge clock according to a predetermined standard, and the cycle data generating means. And a signal for generating a predetermined waveform signal based on the edge clock signal generated by the edge clock generating means, the edge clock generating means for extracting the pulse of the pulse generating means according to the period data generated by a generation unit, a signal generating device comprising a, IC test operation
When the signal for generating the waveform signal propagates during
A fluctuation amount measuring means for measuring the fluctuation amount between
The quantity measuring means, based on the fluctuation amount,
The output timing of the clock generation means is adjusted .

[0084]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram of an IC test apparatus which is an embodiment of the present invention.

As shown in FIG. 1, the IC test apparatus of this embodiment has pin circuits 1 ₁ to 1 _n (hereinafter referred to as pin circuit 1) connected to pins to be tested of the IC under test 5, respectively.
(Also referred to as “)”, a source vibration 2 that generates a pulse having a predetermined cycle
And a pattern generation circuit 3 that outputs data (waveform generation data) necessary for generating a test signal at a timing specified by test clock cycle data generated by a test cycle generation circuit 11 described later, and an IC of the present embodiment. CPU4 which controls each circuit which comprises a test device centralizedly is provided.

The pin circuit 1 includes the test cycle generation circuit 11
An edge generation circuit 12, a waveform generation circuit 13, a driver 14, an analog comparator 15, a comparison determination circuit 16, a path time length measurement circuit 17, and a fluctuation amount measurement circuit 18.

The test cycle generation circuit 11 generates test clock cycle data.

The edge generation circuit 12 includes the test clock cycle data generated by the test cycle generation circuit 11, the clock signal from the original oscillator 2, and a fluctuation amount measurement circuit 18 described later.
An edge clock signal is generated on the basis of the correction rate obtained in.

The waveform generation circuit 13 includes the edge generation circuit 12
A test signal is generated based on the edge clock signal of, and the waveform generation data of the pattern generation circuit 3.

The driver 14 amplifies the test signal generated by the waveform generation circuit 13 to a predetermined voltage level, and the IC under test is tested.
5 is applied.

The analog comparator 15 is an IC to be tested.
It is determined whether or not the voltage level of the response signal from 5 is above a predetermined level.

The comparison / determination circuit 16 compares the signal output from the analog comparator 15 with the expected value data output from the pattern generation circuit 3 to determine the quality of the response signal.

The route time length measuring circuit 17 determines the propagation required for the signal to pass through the route of the circuits of the pin circuit 1 through which the signal requiring high time accuracy passes. Time (hereinafter, also referred to as route time length) is measured.

The route along which a signal requiring high time accuracy passes will be described later.

The fluctuation amount measuring circuit 18 detects a change in the path time length of the path through which the signal requiring the high time accuracy passes. Then, the correction factor for generating the test signal is calculated with a predetermined time accuracy or less.

Each circuit constituting the pin circuit 1 can be built in one LSI. In the present embodiment, an example in which the edge generation circuit 12, the waveform generation circuit 13, the comparison determination circuit 16, the path time length measurement circuit 17, and the variation amount measurement circuit 18 are incorporated in the same LSI will be described.

Further, in FIG. 1, the edge generation circuit 12 is set to 1
Although only two are provided, actually three edge clock signals are provided for inputting two edge clock signals to the waveform generation circuit 13 and one to the comparison / determination circuit 16 , respectively.

Next, the edge generating circuit 12 will be described in detail.

FIG. 2 is a schematic configuration diagram of the edge generating circuit 12.
FIG. 3 is a schematic configuration diagram of the correction arithmetic circuit 127 shown in FIG.

As shown in FIG. 2, the edge generation circuit 12 includes a data operation circuit 121, an AND circuit 122, a delay circuit 123, and a flip-flop (FF) circuit 124.
a, 124b, the coincidence detection circuit 125, and the counter 12
6 and a correction calculation circuit 127.

The data arithmetic circuit 121 generates the timing data A of the edge clock signal. The timing data A includes count data E (f) ct and delay time data E.
(F) It consists of dly.

The correction calculation circuit 127 corrects the delay time data E (f) dly generated by the data calculation circuit 121 based on the correction rate obtained by the fluctuation amount measurement circuit 18 described later. Then, the corrected delay time data E ′ (f) dl
The y and the count data E (f) ct generated by the data operation circuit 121 are output as the timing data B.

As shown in FIG. 3, the correction arithmetic circuit 127 includes a register 127a, an adder 127b, and a multiplier 1.
27c and an adder / subtractor 127d.

The correction calculation circuit 127 firstly adds the adder 12
In 7b, the value Toff stored in the register 127a is added to the delay time data E (f) dly generated by the data operation circuit 121.

Next, in the multiplier 127c, the adder 1
The correction data Am is obtained by multiplying the value obtained at 27b by the correction rate obtained at the fluctuation amount measuring circuit 18 described later.

Then, in the adder / subtractor 127d,
Delay time data E generated by the data arithmetic circuit 121
By adding the correction data Am to (f) dly, the delay time data E ′ (f) dly input to the delay circuit 123 is obtained. Then, the delay time data E ′ (f) dly and the count data E (f) ct generated by the data operation circuit 121.
And outputs the timing data B consisting of

The counter 126 counts the number of pulses output from the original oscillator 2.

The coincidence detection circuit 125 compares the count value of the counter 126 with the count data E (f) ct of the data operation circuit 121 latched by the FF circuit 124b. Then, when both match, a match signal (logical value H at the time of match) is output.

FIG. 4 is a timing chart for explaining the operation of the edge generating circuit 12 for generating the edge clock signal.

In FIG. 4, the original vibration 2 generates pulses at a constant cycle. The counter 126 counts up according to the pulse of the original vibration 2.

The test cycle generation circuit 11 generates the test clock cycle data R (f) according to the number of times the test clock cycle data is output.

Here, when the number of times the test clock cycle data is output is n, R (n) = 3 cycles of the original oscillation, when n + 1, R (n + 1) = 4 cycles of the original oscillation, and R when n + t.
The test clock cycle data R (f) is changed such that (n + t) = source vibration 3 + t cycles.

The data operation circuit 121 includes an AND circuit 12
The count data E (f) ct and the delay time data E (f) dly are output in accordance with the clock signal output from 2.

Here, the data operation circuit 121 generates the count data E (f) ct in accordance with the test clock cycle data output from the test cycle generation circuit 11 .

Here, when the clock signal from the AND circuit 122 is received, the test clock cycle data is R
In case of (n-1), E ( n ) ct = 2, in case of R (n), E (n + 1 ) ct = 3, and in case of R (n + t), E (n + 1).
+ T) ct = 3 + t, and count data E
(F) ct is changed.

[0117] The data operation circuit 1 21, and generates a delay time data E (f) dly indicating the delay time.

[0118] Here, when receiving a clock signal from the AND circuit 1 22, E (n) dly , E (n + 1) dl
y, ..., so that E (n + 1 + t) = 0.5,
Delay time data E (f) dly showing a constant delay time is generated.

[0119] FF circuit 124b in accordance with a clock signal from the AND circuit 1 22, and the count data E (f) ct generated in the data calculating circuit 121, the correction calculation circuit 12
The delay time data E ′ (f) dly corrected in 7 is latched.

Next, the operation of the edge generating circuit 12 will be described.

First, when the clock signal of the AND circuit 122 is input to the data arithmetic circuit 121, the data arithmetic circuit 121 causes the count data E (f) to follow the above procedure.
ct, delay time data E (f) dly is output.

Next, the correction operation circuit 127 outputs the delay time data E '(f) dly by correcting the delay time data E (f) dly generated by the data operation circuit 121 in accordance with the above procedure. .

The count data E (f) ct generated by the data operation circuit 121 and the delay time data E '(f) dly corrected by the correction operation circuit 127 are combined in the FF circuit 124.
The signal b is latched once by the clock signal of the AND circuit 122, and then input to the coincidence detection circuit 125 and the delay circuit 123, respectively.

Next, the coincidence detection circuit 125 is operated by the FF circuit 1
The count data E (f) ct output from 24b is compared with the count value of the counter 126. Then, when both match, a match signal (logical value H at the time of match) is output.

The coincidence signal is output by the FF circuit 124 in synchronization with the pulse of the original vibration 2 and input to the AND circuit 122. As a result, the pulse of the original vibration 2 is output from the AND circuit 122 for one clock at the timing when the match detection circuit 125 outputs the match signal.

Next, the delay circuit 123 has the AND circuit 12
The clock signal output from 2 is delayed by the time specified by the delay time data E ′ (f) dly output from the FF circuit 124b. As a result, the edge clock signal is output.

By doing so, the edge clock signal is generated in a cycle corresponding to the test clock cycle data of the test cycle generating circuit 11.

In the edge generating circuit 12 shown in FIG.
As shown in FIG. 4, when the clock signal is output from the AND circuit 122, the delay time data E ′ (f) dly output from the FF circuit 124b is switched to the next one.
The delay circuit 123 holds the delay time data E ′ (f) dly before switching until the clock signal of the AND circuit 122 passes through the delay circuit 123.

Further, as described above, in the present embodiment,
In order to input two edge clock signals to the waveform generation circuit 13 and one to the comparison / determination circuit 16 , respectively,
Three edge generation circuits 12 are provided. Each edge generation circuit 12 outputs the edge clock signals of the same cycle at different timings (phases).

Next, the waveform generating circuit 13 will be described in detail.

FIG. 5 is a schematic configuration diagram of the waveform generation circuit 13.

Here, the edge clock signals 1 and 2 represent the edge clock signals output from two of the above-mentioned three edge generating circuits 12.

The waveform generating circuit 13 is, as shown in FIG.
The waveform generation data generation circuit 131 and the delay circuit 132 for deskewing the test signal applied to the IC under test 5
a to 132d, logic circuits 133a and 133b including AND circuits and OR circuits, and flip-flops (FF)
And a circuit 134.

The waveform generation data generation circuit 131, in accordance with the waveform generation data output from the pattern generation circuit 3,
Output test signal generation data.

The delay circuits 132a and 132c adjust the output timing of the edge clock signal 1 to control the IC under test.
The skew of the test signal applied to 5 is adjusted.

The delay circuits 132b and 132d adjust the output timing of the edge clock signal 2 to control the IC under test.
The skew of the test signal applied to 5 is adjusted.

Next, the operation of the waveform generation circuit 13 will be described.

FIG. 6 is a timing chart for explaining the operation of waveform generation circuit 13 for outputting a test signal.

First, the waveform generation data generation circuit 131
The test signal generation data is output according to the waveform generation data output from the pattern generation circuit 3.

Here, the test signal generation data A shown in FIG.
Is data in which the input B and the input D of the logic circuit 133a are respectively the logical value H and the logical value L, and the input B and the input D of the logical circuit 133b are the logical value L and the logical value H, respectively, The logic circuit 133a receives the logic value L only when the edge clock signal 1 is output from the delay circuit 132a.
In response to this, the FF circuit 134 is set by the output signal (logic value L) of the logic circuit 133a and outputs the test signal (logic value H), as shown in FIG.

On the other hand, the logic circuit 133b corresponds to the delay circuit 13
The logic value L is output only when the edge clock signal 2 is output from 2d.

In response to this, the FF circuit 134 outputs the output signal (logic value L) of the logic circuit 133b as shown in FIG.
Is reset, and the output of the test signal is stopped (logical value L).

As a result, a test signal having an RZ (Return to Zero) waveform is output.

As described above, the waveform generation circuit 131 selects the edge clock signal to be passed through the logic circuits 133a and 133b based on the test signal generation data generated by the waveform generation data generation circuit 131, and the selected edge clock signal. A test signal is generated based on

The test signal generated by the waveform generating circuit 13 is amplified to a predetermined voltage level by the driver 14 and applied to the IC under test 5. Normally, a signal for controlling whether the driver is turned on or off is used for the driver 14, but it is omitted here.

Next, the comparison / determination circuit 16 will be described in detail.

FIG. 7 is a schematic block diagram of the comparison / determination circuit 16.

Here, the edge clock signal 3 is one of the three edge generating circuits 12 described above (other than the two edge generating circuits 12 outputting the edge clock signals 1 and 2 input to the waveform generating circuit 13). Edge generation circuit 1
2 shows the edge clock signal output from 2).

The comparison / determination circuit 16, as shown in FIG.
The delay circuit 161 and the flip-flop (FF) circuit 16
2 and a pass / fail comparison circuit 163.

The FF circuit 162 latches the response signal of the IC under test 5 sent via the analog comparator 15 according to the edge clock signal 3 output from the delay circuit 161.

The pass / fail judgment circuit 163 compares the level of the response signal latched by the FF circuit 162 with the expected value data sent from the pattern generation circuit 3. Thereby, the quality of the response signal is determined.

The delay circuit 161 determines the determination timing of the response signal output from the IC under test 5 by using the pin circuit 1
_It is used for adjusting skew between ₁ to 1 _n . The comparison / determination circuit 16 uses the edge clock signal 3 as the quality determination timing. Therefore, the edge clock signal is delayed by a predetermined time.

For example, when a response signal that changes from the L level to the H level at the same timing is input to each of the pin circuits 1 ₁ to 1 _n from the IC under test 5, the level change is changed at the same timing. as can be determined, to set the delay amount of the delay circuit 1 6 1.

Next, the path time length measuring circuit 17 will be described in detail.

FIG. 8 is a schematic configuration diagram of the path time length measuring circuit 17.

As described above, the route time length measuring circuit 17 measures the propagation time (route time length) required for the signal to pass through the route, through which the signal requiring high time accuracy passes. It is for doing.

Here, as a path through which a signal requiring high time accuracy passes, a path through which a signal requiring high time accuracy for applying a test signal to the IC under test 5 passes, and from the IC 5 under test There is a path through which a signal that requires a high time accuracy for latching the response signal of 1 passes.

In the present embodiment, as shown in FIG. 8, as the former, the original oscillation 2-edge generation circuit 12 (AND circuit 12
2-delay circuit 123) -waveform generation circuit 13 (delay circuit 1
32a to 132d-The path time length of the path connecting the logic circuits 133a and 133b (hereinafter referred to as path B) is measured, and as the latter, the original oscillation 2-edge generation circuit 12 (AND
A method of measuring the path time length of the path connecting the circuit 122-delay circuit 123) -comparison and determination circuit 16 (delay circuit 161) (hereinafter referred to as path C) will be described.

As shown in FIG. 8, the path time length measuring circuit 17 includes selectors 171a to 171c and a period measuring circuit 17.
2a-172c and the inverter 173 are provided.

The selector 171a controls the input of the AND circuit 122 of the edge generating circuit 12 which outputs the edge clock signal 1 based on the instruction of the CPU 4 shown in FIG.
The logic circuit 133a of the waveform generation circuit 13 based on the output of the original vibration 2
Switch to the output of.

As a result, a closed loop of the path B including the AND circuit 122 and the delay circuit 123 of the edge generating circuit 12 which outputs the edge clock signal 1 is formed.

The selector 171b generates the waveform of the input of the AND circuit 122 of the edge generating circuit 12 which outputs the edge clock signal 2 from the output of the original vibration 2 for a predetermined period based on the instruction of the CPU 4 shown in FIG. Logic circuit 13 of circuit 13
Switch to 3b output.

As a result, a closed loop of the path B including the AND circuit 122 and the delay circuit 123 of the edge generating circuit 12 which outputs the edge clock signal 2 is formed.

The selector 171c compares the input of the AND circuit 122 of the edge generating circuit 12 outputting the edge clock signal 3 from the output of the original oscillator 2 for a predetermined period based on the instruction of the CPU 4 shown in FIG. Delay circuit 16 of circuit 16
Switch to 1 output.

Thus, the closed loop of the path C is formed.

The cycle measuring circuit 172a includes a selector 171a.
The oscillation period of the closed loop of the path B formed by is measured.

The cycle measuring circuit 172b includes a selector 171b.
The oscillation period of the closed loop of the path B formed by is measured.

The cycle measuring circuit 172c is connected to the selector 171c.
The oscillation period of the closed loop of the path C formed by is measured.

For example, the path time length of the closed loop is Toff.
In the case of, the closed-loop oscillation period is Toff × 2.
Therefore, the path time length of the closed loop can be obtained from the oscillation cycle measured by the cycle measuring circuits 172a to 172c. This calculation is performed by the CPU 4.

As described above, the route time length measuring circuit 17 determines the propagation time (route time length) required for the signal to pass through the route for the route through which the signal requiring high time accuracy passes. Is intended to be measured.

However, the cycle measuring circuits 172a to 172a-1
The route time length obtained from the oscillation period measured at 72c is not the route itself but the closed loop route time length including the route.

That is, taking the path time length obtained from the oscillation period measured by the period measuring circuit 172a as an example, the waveform generating circuit 1 is provided on the route B formed by the selector 171a.
The path time length of the path connecting the third logic circuit 133a, the cycle measuring circuit 172a, and the selector 171a is additionally added.

Therefore, the cycle measuring circuits 172a to 172 are provided.
In order to minimize the difference between the route time length obtained from the oscillation period measured in c and the actual route time length of the route to be measured, the following points should be noted.

Make extra paths as short as possible. For example, in the case of the closed loop of the path B formed by the selector 171a, the logic circuit 133a− of the waveform generation circuit 13
The path connecting the cycle measuring circuit 172a and the selector 171a is made as short as possible.

Alternatively, the route time length of the extra route is calculated in advance by using a circuit simulation or the like, and C
In PU4, the route time length of the extra route is subtracted from the route time length obtained from the oscillation period measured by the period measuring circuits 172a to 172c.

In the selectors 171a to 171c, the gates are constructed so that the propagation delay times of the two inputs (F and G shown in FIG. 8) are as similar as possible. Alternatively, the wiring for connecting the gates is made equal in length.

Next, the operation of the path time length measuring circuit 17 will be described.

When the IC test apparatus of this embodiment is powered on, the CPU 4 issues a command to the path time length measuring circuit 17. In response to this, the path time length measuring circuit 17 first
As shown in FIG. 8, the edge generation circuit 1 that switches the connection of the selector 171a and outputs the edge clock signal 1
Path B including AND circuit 122 of 2 and delay circuit 123
Form a closed loop of.

At this time, the CPU 4, as shown in FIG.
The input E of the AND circuit 122 of the edge generation circuit 12 that outputs the edge clock signal 1 is the logical value H, and the waveform generation circuit 1
The input of each circuit is set so that the inputs B, C, D of the three logic circuits 133a have the logical values H, H, L, respectively. As a result, the closed loop of the path B is oscillated.

Next, the period measuring circuit 172a measures the oscillation period of the closed loop and transmits the obtained oscillation period to the CPU 4.

In response to this, the CPU 4 determines the edge clock signal 1 from the oscillation cycle obtained by the cycle measuring circuit 172a.
The path time length Toff of the path B including the AND circuit 122 and the delay circuit 123 of the edge generation circuit 12 that outputs Then, the obtained path time length Toff is stored in the register 127a of the correction operation circuit 127 of the edge generation circuit 12 which outputs the edge clock signal 1.

Next, the path length measuring circuit 17 includes the selector 17
The connection of 1a is returned to the original state, and thereafter, the connection of the selector 171b is switched to form a closed loop of the path B including the AND circuit 122 and the delay circuit 123 of the edge generation circuit 12 that outputs the edge clock signal 2.

At this time, the CPU 4, as shown in FIG.
The input E of the AND circuit 122 of the edge generation circuit 12 that outputs the edge clock signal 2 is the logical value H, and the waveform shaping circuit 1
The inputs of the three logic circuits 133b are set so that the inputs A, B, D respectively have the logical values H, L, H. As a result, the closed loop of the path B is oscillated.

Next, the period measuring circuit 172b measures the oscillation period of the closed loop and transmits the obtained oscillation period to the CPU 4.

In response to this, the CPU 4 determines the edge clock signal 2 from the oscillation period obtained by the period measuring circuit 172b.
The path time length Toff of the path B including the AND circuit 122 and the delay circuit 123 of the edge generation circuit 12 that outputs Then, the obtained path time length Toff is stored in the register 127a of the correction operation circuit 127 of the edge generation circuit 12 which outputs the edge clock signal 2.

Next, the path length measuring circuit 17 uses the selector 17
The connection of the selector 171c is switched after the connection of 1b is restored, and a closed loop of the path C including the AND circuit 122 and the delay circuit 123 of the edge generation circuit 12 that outputs the edge clock signal 3 is formed.

At this time, the CPU 4, as shown in FIG.
The input is set so that the input E of the AND circuit 122 of the edge generation circuit 12 that outputs the edge clock signal 3 has the logical value H. As a result, the closed loop of the path C is oscillated.

Next, the period measuring circuit 172c measures the oscillation period of the closed loop and transmits the obtained oscillation period to the CPU 4.

In response to this, the CPU 4 determines the edge clock signal 3 from the oscillation cycle obtained by the cycle measuring circuit 172c.
The path time length Toff of the path C including the AND circuit 122 and the delay circuit 123 of the edge generating circuit 12 that outputs Then, the obtained path time length Toff is stored in the register 127a of the correction operation circuit 127 of the edge generation circuit 12 which outputs the edge clock signal 3.

As a result, the measurement of the route time length of the route having high time accuracy is completed. Then, the test of the IC under test 5 is started.

When measuring the oscillation period in the period measuring circuits 172a to 172c, the delay amount 0 is set in the delay circuit 123 of the edge generating circuit 12 which delays the clock period of the original oscillation 2 or less, and each pin circuit is set. A value to be deskewed is set in the delay circuits 132a to 132d of the waveform generation circuit 13 that performs deskewing between 1 and 2. This setting is performed by the CPU 4.

Next, the fluctuation amount measuring circuit 18 will be described in detail.

FIG. 9 is a schematic configuration diagram of the fluctuation amount measuring circuit.

As described above, in this embodiment, three edge generation circuits 12 are provided to input two edge clock signals to the waveform generation circuit 13 and one to the comparison / determination circuit 16 respectively. ing. Accordingly, in the present embodiment, corresponding to 12 each three edge generating circuit 3
Two fluctuation amount measuring circuits 18a to 18c are provided.

As shown in FIG. 9, the fluctuation amount measuring circuits 18a to 18c are composed of the fluctuation amount detecting circuit 181 and the period measuring circuit 1.
82, a reference oscillation cycle holding register 183, and a correction factor calculation circuit 184.

The fluctuation amount detection circuit 181 has substantially the same circuit configuration as the closed loop including the path to be corrected.

That is, the fluctuation amount measuring circuit 18a includes the AND circuit 122 and the delay circuit 123 of the edge generating circuit 12 which outputs the edge clock signal 1 and which is formed by the selector 171a of the path time length measuring circuit 17. The circuit configuration is substantially the same as that of the closed loop of the path B.

Further, the variation measuring circuit 18b includes an AND circuit 122 and a delay circuit 123 of the edge generating circuit 12 which outputs the edge clock signal 2 and which is formed by the selector 171b of the path time length measuring circuit 17. The circuit configuration is substantially the same as that of the closed loop of the path B.

In the case of the fluctuation amount measuring circuit 18c,
Although not shown in FIG. 9, the AND circuit 122 of the edge generation circuit 12 that outputs the edge clock signal 3 formed by the selector 171c of the path time length measurement circuit 17
The circuit configuration is substantially the same as the closed loop of the path C including the delay circuit 123.

As described above, the fluctuation amount detection circuit 181 has substantially the same circuit configuration as the closed loop including the path to be corrected, so that the variation caused by a change in the external condition of the pin circuit 1 such as temperature and power supply voltage. It is possible to reproduce the variation of the route time length of the route.

The period measuring circuit 182 is composed of the n frequency dividing circuit 182.
It has a, an AND circuit 182b, and a counter 182c. The period measuring circuit 182 is a fluctuation amount detecting circuit 181.
The oscillating pulse is divided by n by the n divider 182a, and the divided signal is input to the AND 182b as a window signal. Then, while the frequency-divided signal is at the H level, the counter 182c counts the number of pulses of the original vibration 2 to measure the oscillation cycle of the fluctuation amount detection circuit 181.

For example, if the n frequency dividing circuit 182a divides by 32 and the pulse period of the original vibration 2 is 5 ns,
If the count value of the counter 182c is 128, the oscillation cycle of the fluctuation amount detection circuit 181 is 20 ns (128/3
2 division x 5 ns).

[0203] Here, in the case to increase the speed of periodic measurements, the period measuring circuit 1 7 2 provided plurality, may be used interleaving the like.

Although the circuit configuration of the period measuring circuits 172a to 172c of the path time length measuring circuit 17 has not been described, it can be realized by the same configuration as the period measuring circuit 182 of the fluctuation amount measuring circuit 18.

The reference oscillation cycle holding register 183 is used for the cycle measurement circuits 172a to 172c of the path time length measurement circuit 17.
Stores the closed-loop oscillation period including the path to be corrected, which was measured in.

That is, in the case of the fluctuation amount measuring circuit 18a, the AND circuit 12 of the edge generating circuit 12 which outputs the edge clock signal 1 measured by the period measuring circuit 172a.
2 and the closed-loop oscillation cycle of the path B including the delay circuit 123 are stored.

In the case of the fluctuation amount measuring circuit 18b, the edge clock signal 2 measured by the period measuring circuit 172b is measured.
The closed-loop oscillation cycle of the path B including the AND circuit 122 and the delay circuit 123 of the edge generation circuit 12 that outputs

In the case of the fluctuation amount measuring circuit 18c,
The closed-loop oscillation cycle of the path C including the AND circuit 122 and the delay circuit 123 of the edge generation circuit 12 that outputs the edge clock signal 3 measured by the cycle measurement circuit 172c is stored.

The correction factor calculation circuit 184 calculates the correction factor. Here, when the oscillation cycle stored in the reference oscillation cycle holding register 183 is Ts and the oscillation cycle of the fluctuation amount detection circuit 181 measured by the cycle measurement circuit 182 is Tv,
The correction factor is as follows.

Correction rate = (Ts-Tv) / Ts The correction rate calculated by the correction rate calculation circuit 184 is the variation amount measuring circuit 18a through which the correction rate calculation circuit 184 is provided.
Correction operation circuit 1 of edge generation circuit 12 corresponding to 18c
27 is input.

That is, when the correction factor calculation circuit 184 is provided in the fluctuation amount measurement circuit 18a, it is input to the correction calculation circuit 127 of the edge generation circuit 12 which outputs the edge clock signal 1.

If the correction factor calculation circuit 184 is provided in the fluctuation amount measurement circuit 18b, it is input to the correction calculation circuit 127 of the edge generation circuit 12 which outputs the edge clock signal 2.

When the correction factor calculation circuit 184 is provided in the fluctuation amount measurement circuit 18c, it is input to the correction calculation circuit 127 of the edge generation circuit 12 which outputs the edge clock signal 3. Next, the fluctuation amount measuring circuit 18a-
The operation of 18c will be described.

The fluctuation amount measuring circuits 18a to 18c are always operating during the test of the IC under test 5 after the measurement of the route time length by the route time length measuring circuit 17 is completed.

[0215] measure the oscillation period of the variation detection circuit 181 by the period measuring circuit 182, the oscillation period measured, on the basis of the oscillation period stored in the reference oscillation period holding register 183, the fluctuation amount detection circuit 181 A correction factor is calculated according to the variation amount of the route time length.

As described above, in the present embodiment, the path time length measuring circuit 17 measures the closed-loop oscillation period of the path through which the signal having high time accuracy passes before the test of the IC under test 5 is started. ing.

During the test of the IC5 under test,
The fluctuation amount measuring circuit 18 sequentially detects the oscillation cycle of the fluctuation amount detecting circuit 181 formed with the same circuit configuration as the closed loop, and the detected oscillation cycle and the closed loop measured by the path time length measuring circuit 17 Based on the oscillation cycle of
A correction factor for correcting the variation in the closed loop path time length is calculated.

Then, based on the calculated correction rate,
By setting the delay time of the delay circuit 123 of the edge generation circuit 12 by the correction calculation circuit 127 of the edge generation circuit 12, the output timing of the edge clock signal output from the edge generation circuit 12 is adjusted.

FIG. 10 shows the closed-loop oscillation period of the path (path B or path C described above) through which a signal with high time accuracy, measured by the path time length measuring circuit 17, passes.
Variation amount detection circuit 1 having substantially the same circuit configuration as the closed loop
FIG. 9 is a diagram for explaining the relationship between the oscillation cycle of 81 and the output timing of the edge clock signal output from the edge generation circuit 12.

For example, when the oscillation period measured by the fluctuation amount measuring circuit 18 is the same as the oscillation period measured by the path time length measuring circuit 17, the correction factor calculated by the fluctuation amount measuring circuit 18 is zero.

Therefore, in the edge generation circuit 12, the timing data A (count data E (f) ct, delay time data E generated by the data operation circuit 121 is generated.
(F) dly) is the same as the timing data B (count data E (f) ct, delay time data E ′ (f) dly) output from the correction calculation circuit 127.

Therefore, as shown in FIG. 10A, the output timing of the edge clock signal output from the edge generation circuit 12 is the same as the timing specified by the timing data A generated by the data operation circuit 121. become.

On the other hand, when the oscillation period measured by the fluctuation amount measuring circuit 18 is longer than the oscillation period measured by the path time length measuring circuit 17, the correction factor calculated by the fluctuation amount measuring circuit 18 becomes a negative value.

Therefore, in the edge generation circuit 12, the timing data B (count data E (f) ct, delay time data E ′ output from the correction calculation circuit 127 is output.
(F) dly) is shorter than the timing data A (count data E (f) ct, delay time data E (f) dly) generated by the data operation circuit 121.

Therefore, as shown in FIG. 10B, the output timing of the edge clock signal output from the edge generation circuit 12 is earlier than the timing specified by the timing data A generated by the data operation circuit 121. (In FIG. 10B, T _{ERR is} faster).

If the oscillation period measured by the fluctuation amount measuring circuit 18 is shorter than the oscillation period measured by the path time length measuring circuit 17, the edge generating circuit 12 outputs the opposite of the case shown in FIG. 10B. The output timing of the output edge clock signal is later than the timing specified by the timing data A generated by the data arithmetic circuit 121.

As described above, according to the present embodiment, when the route time length of the route through which a signal having a high time accuracy passes changes, the output timing of the edge clock signal is advanced, and When the path time length fluctuates toward the shorter side, the output timing of the edge clock signal is delayed.

By doing so, the test signal can be generated at the deskewed time before the test, and the skew of the test signal generated from each pin circuit can be reduced.

Further, it is possible to reduce the skew of the determination timing of the response signal from the IC under test 5.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the gist thereof.

For example, in the above embodiment, the I
Prior to the C5 test, the path time length measuring circuit 17 measures the closed-loop oscillation cycle of the path through which a signal having high time accuracy passes.

However, the present invention is not limited to this, and the oscillation cycle of the path may be measured in advance by using LSI chip simulation. By doing so, it becomes unnecessary to provide the path time length measuring circuit 17.

Further, in the present embodiment, as a path for measuring the oscillation period by the path time length measuring circuit 17, as shown in FIG. 8, the original oscillation 2-edge generation circuit 12 (AND circuit 122
-Delay circuit 123) -Waveform generation circuit 13 (delay circuit 13
2a to 132d-path B connecting the logic circuits 133a and 133b) and the original oscillation 2-edge generation circuit 12 (AND circuit 1)
22-delay circuit 123) -the path C connecting the comparison / determination circuit 16 (delay circuit 161) has been described.

However, the present invention is not limited to this. The path for measuring the oscillation period by the path time length measuring circuit 17 is a signal that requires high time accuracy in order to apply a test signal to the IC under test 5 or to latch a response signal from the IC under test 5. Any route may be used.

FIG. 11 is a diagram showing an example of a path for measuring the oscillation period by the path time length measuring circuit 17 when each of the pin circuits 1 ₁ to 1 _n is composed of one LSI.

Here, 21a and 21b are input pins and 22
a and 22b are output pins, 23a and 23b are input buffers, and 24a and 24b are output buffers.

With the configuration shown in FIG. 11, a closed loop formed by switching the selectors 171a and 171b has an input pin 21b-input buffer 23b-edge generation circuit 12-waveform generation 13-output buffer 24b.
-It becomes a closed loop of the path connecting between the output pins 22b.

[0238] Thus, by measuring the oscillation period of the closed loop, it is possible to predict the oscillation period of the closed loop path connecting between the input pin 21a~ output pin 22 a.

Similarly to FIG. 11, FIG. 12 also shows the pin circuit 1 ₁
In case of constituting to 1 _n respectively in one LSI, a diagram showing an example of a path to measure the oscillation period in the path length of time measuring circuit 17.

Here, the selectors 171a and 171b are set to L.
It is provided outside the SI. In the configuration shown in FIG.
The closed loop formed by switching the selectors 171a and 171b is the input pin 21a-the input buffer 23a-
Edge generation circuit 12-waveform generation 13-output buffer 24
It becomes a closed loop of a path connecting the a-output pin 22a.

Therefore, by measuring the closed-loop oscillation cycle, the closed-loop oscillation cycle of the path connecting the input pin 21a and the output pin 22a can be predicted.

Further, in the present embodiment, the waveform generation circuit 13
Is provided with delay circuits 132a to 132d for adjusting the skew of the test signal applied to the IC under test 5, and the comparison and judgment circuit 16 is provided with a delay circuit 161 for adjusting the skew of the judgment timing of the response signal output from the IC under test 5. It is provided.

However, as shown in FIG. 13, the delay circuit for skew adjustment need not be provided in the waveform generation circuit 13a and the comparison / determination circuit 16a.

FIG. 14 is a waveform generation circuit 13 shown in FIG.
3A is a schematic configuration diagram of a correction arithmetic circuit used in the edge generation circuit 12 applied to a and the comparison determination circuit 16a.

The correction calculation circuit 227 shown in FIG.
The difference from the correction arithmetic circuit 127 shown in is that an adder 227a, a selector 227b, a register 227c, and
227d is provided.

The registers 227c and 227d are connected to the I.
The skew adjustment time of the test signal applied to C5, that is, the delay time set in the delay circuits 132a to 132d of the waveform generation circuit 13 in the above embodiment is stored.

The operation of the correction arithmetic circuit 227 shown in FIG. 14 will be described.

First, before starting the test, the register 22
7c and 227d are set to the skew adjustment time of the test signal applied to the IC under test 5, that is, the delay times set in the delay circuits 132a to 132d of the waveform generation circuit 13 in the above embodiment. This setting is shown in Figure 1.
CPU4 of.

Next, during the test, the selector 227b
Is used to select the register 227c or the register 227d. Then, the adder 227a adds the value stored in the register to the delay time data E (f) dly generated by the data operation circuit 121.

For example, when the register 227c is selected by the selector 227b by the switching data from the CPU 4, if the value stored in the register 227c is 0.3, the delay generated by the data operation circuit 121 is generated. 0.3 is added to the time data E (f) dly.

The subsequent processing is the same as that of the correction arithmetic circuit 127 shown in FIG.

By adding the value stored in the register by the adder 227a to the delay time data E (f) dly, the delay time data E (f) dly exceeds one cycle of the original vibration 2. In this case, the count data E (f) ct generated by the data operation circuit 121 is incremented by one, and one cycle of the original vibration 2 is subtracted from the delay time data E (f) dly. By repeating this processing, the delay time data E (f) dly is made to fall within the range of one cycle of the original vibration 2.

According to the correction operation circuit 227 shown in FIG. 14, by adding the skew adjustment time to the timing data generated by the data operation circuit 121, the skews provided in the waveform generation circuit 13 and the comparison / determination circuit 16 are skewed. The delay circuit for adjustment becomes unnecessary.

As a result, the route time length of the route through which the signal having high time accuracy passes can be shortened.

[0255]

As described above, according to the present invention,
When the external conditions such as temperature and power supply voltage change, adjust the output timing of the edge clock signal according to the fluctuation of the propagation time of the path through which the signal with high time accuracy passes, which occurs due to the change. Therefore, the time accuracy of the output timing of the test signal applied to the IC under test can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of an IC test apparatus according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of an edge generation circuit shown in FIG.

FIG. 3 is a schematic configuration diagram of a correction arithmetic circuit shown in FIG.

FIG. 4 is a timing diagram illustrating an operation of the edge generating circuit shown in FIG. 2 for generating an edge clock signal.

5 is a schematic configuration diagram of the waveform generation circuit shown in FIG.

FIG. 6 is a timing chart for explaining an operation of outputting a test signal by the waveform generation circuit shown in FIG.

FIG. 7 is a schematic configuration diagram of a comparison / determination circuit shown in FIG.

FIG. 8 is a schematic configuration diagram of the path time length measurement circuit shown in FIG. 1.

9 is a schematic configuration diagram of the fluctuation amount measuring circuit shown in FIG.

FIG. 10 is a diagram for explaining the relationship between the closed-loop oscillation period measured by the path time length measurement circuit, the oscillation period of the fluctuation amount detection circuit, and the output timing of the edge clock signal output from the edge generation circuit. is there.

FIG. 11 is a diagram showing an example of a path for measuring an oscillation cycle by a path time length measuring circuit when each of the pin circuits shown in FIG. 1 is configured by one LSI.

FIG. 12 is a diagram showing an example of a path for measuring an oscillation cycle by a path time length measuring circuit when each of the pin circuits shown in FIG. 1 is configured by one LSI.

FIG. 13 is a diagram for explaining a modified example of the embodiment shown in FIG.

14 is a schematic configuration diagram of a correction operation circuit of an edge generation circuit used in the modification example shown in FIG.

FIG. 15 is a schematic configuration diagram of a conventional IC test apparatus.

16 is a schematic configuration diagram of the edge generation circuit shown in FIG.

17 is a schematic configuration diagram of the waveform generation circuit and the comparison determination circuit shown in FIG.

FIG. 18 is a timing chart for explaining the operation of the edge generation circuit shown in FIG. 16 for generating an edge clock signal.

FIG. 19 is a timing chart for explaining the operation of the waveform generation circuit shown in FIG. 17 for outputting a test signal.

20 is a timing diagram for explaining skew adjustment between the pin circuits in the IC test apparatus shown in FIG.

[Explanation of symbols]

1 ₁ to 1 _n pin circuit 2 original vibration 3 pattern generation circuit 4 CPU 5 IC under test 11 test cycle generation circuit 12 edge generation circuit 13 waveform generation circuit 14 driver 15 analog comparator 16 comparison judgment circuit 17 path time length measurement circuit 18 fluctuation Quantity measuring circuit 21a, 21b Input pin 22a, 22b Output pin 23a, 23b Input buffer 24a, 24b Output buffer 121 Data operation circuit 122, 182b AND circuit 123, 132a to 132d, 161 Delay circuit 124a, 124b, 134, 162 Flip-flop Circuit 125 Matching circuit 126, 182c Counter 127, 227 Correction operation circuit 127a, 2257c, 227d Register 127b, 227a Adder 127c Multiplier 127d Addition / operation unit 131 Waveform generation data generation circuit 133a 133b logic circuit 163 quality determination circuit 171a~171c, 227b selector 172a~172c, 182 period measuring circuit 173 inverter 181 variation detection circuit 182a n divider 183 reference oscillation period holding register 184 correction factor calculating circuit

Continuation of front page (56) Reference JP-A-2-198375 (JP, A) JP-A-8-226957 (JP, A) JP-A-4-190175 (JP, A) JP-A-8-292242 (JP , A) JP 8-62308 (JP, A) JP 7-98363 (JP, A) JP 6-77789 (JP, A) JP 6-43220 (JP, A) JP 4-184276 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01R 31/28 G01R 31/3183 G01R 31/319 G01R 35/00

Claims (4)

(57) [Claims] 1. A pulse generation means for generating a pulse at a predetermined cycle, a cycle data generation means for generating cycle data of an edge clock according to a predetermined standard, and a cycle for a test signal generated by the cycle data generation means. A test signal edge clock generating means for extracting the pulse of the pulse generating means according to the data and generating an edge clock signal for the test signal, and a judgment signal generated by the periodic data generating means.
Of the pulse generating means according to the periodic data for the signal
To generate the edge clock signal for the decision signal
Determination signal edge clock generation means, test signal generation means for generating a test signal to be applied to the IC under test based on the test signal edge clock signal generated by the test signal edge clock generation means, and the determination Signal edge
Edge clock for judgment signal generated by lock generation means
The quality of the response signal of the IC under test is judged based on the signal.
An IC test device for judging whether a response signal to the test signal of the IC under test is good or bad, the test signal being measured prior to the start of the IC test.
The propagation time in the first path through which the signal for
Approximately the same time as the first path measured during the IC test operation
Propagation time in the first fluctuation amount detection circuit formed by the road structure
And the first path and the second path during the IC test operation.
Measures the fluctuation amount according to the difference in the propagation time of the fluctuation detection circuit.
And a test signal fluctuation amount measuring means for calculating a first correction factor by setting the test signal fluctuation amount measuring means .
Of based on the correction factor to adjust the output timing of the test signal edge clock generating means, further, the good measured prior to starting the IC testing
Propagation on the second path through which the signal for making a rejection decision propagates
Time and the second path measured during the IC test operation,
In the second fluctuation amount detection circuit formed with almost the same circuit configuration
The propagation time and the second path during the IC test operation.
And the second fluctuation amount detection circuit
Fluctuation for judgment signal that measures the momentum and calculates the second correction factor
An amount measuring means, the determination signal fluctuation amount measuring means,
Based on the second correction factor, the edge signal for the determination signal
Characterized by adjusting the output timing of the lock generation means
IC test equipment to. 2. A method according to claim 1, wherein the test signal variation amount measuring means includes a first variation detecting circuit which is formed substantially the same circuit configuration as the first path, the first variation detector It has a first period measuring means for measuring an oscillation period of the circuit, and a first correction factor according to a difference between the oscillation period measured by the first period measuring means and a first reference period prepared in advance. And corrects the output of the edge clock signal from the test signal edge clock generation means, and further, the determination signal variation amount measurement means is the second
A second fluctuation amount detection circuit formed with a circuit configuration that is almost the same as the path.
And the oscillation cycle of the second fluctuation amount detection circuit
With a second period measuring means, in the second period measuring means
Between the measured oscillation period and the second reference period prepared in advance
The second correction factor is calculated according to the difference, and the edge clock
The output of the signal from the edge clock generating means for the judgment signal
An IC test apparatus characterized by correcting force. 3. The oscillating means for oscillating by closing the first path before starting the test of the IC under test according to claim 2, and the oscillation cycle of the first path oscillated by the oscillating means. The first to measure
And a first reference period is an oscillation period measured by the first reference period measuring unit, and the first reference period is further measured before the test of the IC under test is started. Oscillating means for oscillating by closing the second path, and a second reference cycle measuring means for measuring the oscillation cycle of the second path oscillated by the oscillating means, the second reference cycle is The IC test apparatus is characterized in that the oscillation cycle is measured by the second reference cycle measuring means. 4. I according to any one of claims 1 to 3.
C test apparatus comprising the test signal edge clock generation means and the determination
An IC test apparatus characterized in that the signal edge clock generating means is composed of a CMOS.