JP3478005B2 - Method for etching nitride-based compound semiconductor and method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for etching a nitride-based compound semiconductor and a method for manufacturing a semiconductor device, and in particular, it is applied to manufacturing a semiconductor device using a nitride-based III-V group compound semiconductor such as GaN. And is suitable.

[0002]

2. Description of the Related Art GaN-based semiconductors have great potential as materials for not only light-emitting devices but also electron transit devices. That is, the saturated electron velocity of GaN is about 2.5 × 1.
It is 0 ⁷ cm / s, which is larger than that of Si, GaAs, and SiC, and the breakdown electric field is about 5 × 10 ⁶ V / cm, which is the second largest after diamond. For this reason, G
It has been expected that an aN-based semiconductor has great potential as a material for a semiconductor element for high frequency and high power.

However, in the case of making an element using a GaN-based semiconductor, it is not possible to apply the method of forming a conductive layer by impurity diffusion and ion implantation of impurities. It is very different from the semiconductor device of.

That is, for example, the conventional G shown in FIG.
In the aAs MESFET, an undoped GaAs layer 202 is grown on a semi-insulating GaAs substrate 201, n-type impurities are selectively ion-implanted into the undoped GaAs layer 202, and then activation annealing is performed. Forming an n-type channel layer 203, an n ⁺ -type source region 204 and a drain region 205, forming a gate electrode 205 on the n-type channel layer 203, and a source electrode 207 on the source region 204 and the drain region 205, respectively. And a drain electrode 208 is formed. According to this GaAs MESFET, the carrier concentration of the source region 204 and the drain region 205 can be made sufficiently high practically, so that the source electrode 207 and the drain electrode 208 are respectively brought into contact with the source region 204 and the drain region 205 with low contact resistance. Ohmic contact can be made.

However, when a GaN-based semiconductor is used, it is impossible to realize an MESFET having the same structure as the GaAs MESFET as shown in FIG. This is because the impurities ion-implanted into the GaN-based semiconductor are not activated by thermal annealing, so that it is not possible to form a source region and a drain region in which the carrier concentration is practically high, and therefore the source electrode and the drain electrode are not formed. It is not possible to make ohmic contact with the source region and the drain region with low contact resistance.

On the other hand, as a GaAs MESFET,
Some have a so-called recess gate structure as shown in FIG. 21, parts that are the same as or correspond to those in FIG. 20 are assigned the same reference numerals. This GaAs ME
In the SFET, the n-type channel layer 203 is shallowed by so-called recess etching, and the source region 2 is equivalently formed.
04 and the drain region 205 are left.

However, when a GaN-based semiconductor is used, it is impossible to realize a MESFET having the same structure as the GaAs MESFET as shown in FIG. This is because an effective wet etching solution has not yet been developed for GaN-based semiconductors, and dry etching methods such as reactive ion etching (RIE) methods do not physically remove GaN-based semiconductors. This is possible, but it is accompanied by damage during etching, and the damage cannot be removed by thermal annealing.

[0008]

SUMMARY OF THE INVENTION As described above, GaN
In the case of making an element using a GaAs-based semiconductor, it is usually used in an element using a GaAs-based semiconductor, which is called impurity diffusion for forming a source region and a drain region having a high carrier concentration, ion implantation, or recess etching by the RIE method. The method cannot be used. Therefore, GaN
An electron transit device using a spheroidal semiconductor has a high contact resistance between the source electrode and the drain electrode, so that the original performance of the device using a GaN-based semiconductor cannot be exhibited.

On the other hand, a semiconductor laser using a GaN-based semiconductor is being actively researched, but a so-called buried heterostructure (B) is used.
The manufacturing process of the semiconductor laser of H) has not been proposed yet. In the manufacture of this buried heterostructure semiconductor laser, after growing a plurality of semiconductor layers on a substrate, these semiconductor layers are etched into stripe shapes, and the semiconductor layers are regrown at the portions removed by the etching. However, if a dry etching method such as the RIE method is used for this etching, a large damage occurs in the semiconductor layer, and this damage is caused by the temperature at the time of re-growing the semiconductor layer for embedding thereafter. This is because the laser characteristics are not recovered and the laser characteristics are impaired.

Therefore, an object of the present invention is to etch a nitride compound semiconductor such as GaN without damage and with good controllability, and a method for etching the nitride compound semiconductor. It is to provide a method of manufacturing a semiconductor device using the.

[0011]

In order to achieve the above object, the method for etching a nitride-based compound semiconductor according to the first invention of the present invention comprises a first method comprising at least one of hydrogen gas and inert gas. the nitride-based compound semiconductor by using a mixed gas or Ranaru etching gas and characterized in that so as to vapor-phase etching of the compounds of the gas and halogen gas and halogen and carbon with a second gas comprising a gas To do. According to the second invention of the present invention
The method for etching a compound semiconductor is hydrogen gas and
And a first gas containing at least one of an inert gas
That the nitride-based compound semiconductor using an etching gas comprising a mixed gas of a second gas comprising Graphics and gas of a compound with a halogen and-carbon was such that vapor-phase etching
It is a feature.

In the first and second aspects of the present invention, typically, the surface of the nitride-based compound semiconductor in a portion other than the portion to be etched is covered with an insulating film, and the nitride-based compound semiconductor is used as a mask. Etching a compound semiconductor.

According to a third aspect of the present invention, in a method of manufacturing a semiconductor device using a nitride-based compound semiconductor, the surface of the nitride-based compound semiconductor in a portion other than a portion to be etched is covered with an insulating film, A first mask comprising at least one of hydrogen gas and an inert gas using the mask as a mask.
Selectively vapor-phase etching the nitride-based compound semiconductor by using an etching gas composed of a mixed gas of a gas containing the above gas and a halogen gas and a second gas containing the compound of a halogen and carbon, and an insulating film. As a mask, a step of selectively growing and burying a compound semiconductor in a portion of the nitride-based compound semiconductor that has been selectively vapor-phase etched is provided. Fourth aspect of the present invention
Akira is the manufacture of semiconductor devices using nitride compound semiconductors
In the method, nitriding of parts other than the part to be etched
A second gas consisting of a first gas consisting of at least one of hydrogen gas and an inert gas and a gas of a compound of halogen and carbon, which covers the surface of the physical compound semiconductor with an insulating film and uses the insulating film as a mask. A step of selectively vapor-etching a nitride-based compound semiconductor using an etching gas composed of a mixed gas of
Have the burying with the <br/> compound semiconductor selectively vapor-phase etching portions of the system compound semiconductor selectively grown
It is characterized by doing.

In the present invention, the halogen gas or halogen compound gas used as the second gas may be basically any gas as long as it separates halogen at the etching temperature. Specifically, the halogen gas is chlorine (Cl ₂ ) gas, bromine (Br ₃ ) gas, fluorine (F ₃ ) gas, or the like. The halogen compound gas is a compound gas of halogen and hydrogen (a kind of hydride gas), a compound gas of halogen and carbon, or the like. The former compound gas of halogen and hydrogen is, for example, hydrogen chloride (HCl) gas, and the specific compound gas of halogen and carbon is, for example, CCl ₃ F ₃ .

In the present invention, the combination of the first gas and the second gas can be basically selected arbitrarily. For example, the first gas is nitrogen gas and the second gas is Is hydrogen chloride gas. In another example, the first gas is nitrogen gas and the second gas is chlorine gas.
In yet another example, the first gas is hydrogen gas and the second gas is
The gas of is chlorine gas.

In the present invention, typically, the nitride-based compound semiconductor is a nitride-based III-V group compound semiconductor composed of N and at least one group III element selected from the group consisting of Al, Ga and In. Is. Some specific examples of the nitride-based III-V group compound semiconductor are GaN, AlGaN, and GaInN.

In the present invention, the etching is carried out at a temperature within a range where the necessary etching rate is obtained and the crystal of the nitride compound semiconductor as the object to be etched is not broken or the crystallinity is not deteriorated. Particularly, when the etching target is a nitride-based III-V group compound semiconductor,
The etching is typically performed at a temperature of 400 ° C. or higher and 800 ° C. or lower, and preferably 500 ° C. or higher and 700 ° C. or lower.

In the present invention, the insulating film used as a mask for selective etching and selective growth is, for example,
It is a silicon oxide film or a silicon nitride film.

In the present invention, the compound semiconductor embedded in the selectively etched portion of the nitride-based compound semiconductor is, for example, a nitride-based compound semiconductor of the nitride-based compound I.
In the case of a II-V group compound semiconductor, arsenic III-V
It is a group III compound semiconductor or a phosphorus-based III-V group compound semiconductor. In addition, a metal organic chemical vapor deposition (MOCVD) method is typically used for growing the compound semiconductor.

In the method of etching a nitride-based compound semiconductor according to the present invention having the above-described structure, since the gas-phase thermochemical etching is performed, the nitride-based compound semiconductor is not damaged by the etching. Further, since the etching rate is mainly controlled by the temperature, the controllability of etching is good.

According to the method for manufacturing a semiconductor device of the present invention having the above-described structure, the etching of the nitride compound semiconductor is performed in the vapor phase, so this etching is performed in the reaction furnace of the vapor phase growth apparatus. be able to. Then, after performing selective etching of the nitride-based compound semiconductor in the reaction furnace of the vapor phase growth apparatus, subsequently, in this reaction furnace, the compound semiconductor is selectively selected on the clean surface of the selectively etched portion. Can be grown and embedded. Further, since the insulating film used as the selective etching mask is used as it is as the selective growth mask, the compound semiconductor can be embedded in a self-aligned manner in the portion removed by the selective etching.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding parts are designated by the same reference numerals.

In the following embodiments, a structure in which a layer made of a nitride-based III-V group compound semiconductor such as GaN, AlGaN, and GaInN is laminated on a c-plane sapphire substrate is used. First, these nitride-based materials are used. A general method for growing a III-V compound semiconductor by a metal organic chemical vapor deposition (MOCVD) method will be described.

As a source gas for growing the nitride III-V compound semiconductor, trimethylgallium (TMG) as a Ga source, trimethylaluminum (TMA) as an Al source, trimethylindium (TMIn) as an In source, Ammonia (N
H ₃ ) and silane (S as a dopant gas for n-type impurities)
iH ₄ ) is used. And, as is well known,
First, on a c-plane sapphire substrate at low temperature, AlN or Ga
After growing the buffer layer made of N, the growth temperature is raised to around 1000 ° C. while flowing NH ₃ gas to grow GaN, AlGaN, etc. on the buffer layer. Here, in the case of growing a nitride-based III-V group compound semiconductor containing In such as GaInN, the growth temperature is 700.
It is also well known that the temperature is lowered to 800 ° C. and the atmosphere gas is nitrogen (N ₂ ).

Next, the measurement result of the temperature dependence of the etching rate of GaN will be described. A sample for measuring the temperature dependence is prepared as follows. First, a low-temperature growth buffer layer made of AlN or GaN is grown on a c-plane sapphire substrate, and then a GaN layer having a thickness of 3 μm is grown on the buffer layer. Next, this Ga
A mask made of a SiO ₂ film having a stripe shape is formed on the N layer. Next, this c-plane sapphire substrate is MO
It is introduced into the reaction furnace of the CVD device. Next, after raising the substrate temperature to 700 ° C. in a normal pressure N ₂ gas atmosphere, HCl gas is introduced into the reaction furnace to a partial pressure of 0.01 atm. Then, after keeping that state for 20 minutes, the substrate temperature was lowered in an N ₂ gas atmosphere.

When the height of the step on the surface of the GaN layer subjected to the above-mentioned treatment was measured, it was about 1 μm. That is, the GaN layer was etched by about 1 μm.

Next, when the same etching was carried out using Cl ₂ gas instead of HCl gas, no significant difference was observed in the etching amount, but the morphology of the etched surface deteriorated slightly.

Next, the GaN layer was etched at various temperatures using an etching gas prepared by introducing HCl gas into the N ₂ gas atmosphere, and the etching rate was measured. The result is shown in FIG. As shown in FIG. 1, the etching rate shows an Arrhenius-type dependence, which indicates that the surface reaction is dominant in this etching. Further, according to the measurement result of the etching rate, when the etching temperature is 400 ° C., the etching rate is 1 nm.
/ Min, the etching rate is substantially 0, but it can be seen that the etching rate increases as the etching temperature increases.

Here, it is considered that the etching reaction using HCl gas is 3GaN + 3HCl → 3GaCl + NH ₃ + N ₂ , and the etching reaction using Cl ₂ gas is 2GaN + Cl ₂ → 2GaCl + N ₂ . All of these etchings are performed thermochemically.

Next, 0.01 atmosphere of Cl ₂ gas was introduced into H ₂ gas at atmospheric pressure, and GaN was formed at 700 ° C. for 20 minutes.
The layers were etched. At this time, the etching amount is 1
It was about μm, and no surface roughness was observed. This etching reaction is considered to be GaN + Cl ₂ + 2H ₂ → GaCl + NH ₄ Cl. It is considered that hydrogen promotes the reaction in this etching reaction.

Next, G according to the first embodiment of the present invention
A method of manufacturing the aN MESFET will be described.

In the first embodiment, first, as shown in FIG. 2, an undoped GaN layer 2 and an n-type GaN layer 2 are formed on a c-plane sapphire substrate 1 via a buffer layer (not shown) made of AlN or GaN. MO the GaN channel layer 3
Sequentially grow by the CVD method. Undoped GaN layer 2
Has a thickness of, for example, 2 μm. The carrier concentration of the n-type GaN channel layer 3 is, for example, 4 × 10 ¹⁷ cm ⁻³ , and the thickness thereof is, for example, 160 nm.

Next, for example, a 100 nm thick SiO ₂ film is formed on the entire surface of the n-type GaN channel layer 3 by, for example, the CVD method.
After forming the film, the SiO ₂ film is patterned into a stripe shape by lithography and etching to form a SiO ₂ mask 4. The SiO ₂ mask 4 has a width of, for example, 3 μm and a length of, for example, 300 μm. Note that, for example, Si ₂ H ₆ is used as a reaction gas when the SiO ₂ film is formed by the CVD method, and wet etching using a hydrofluoric acid-based etching solution or a fluorine-based etching gas is used for etching the SiO ₂ film. The RIE used is used.

Next, in the reaction furnace of the MOCVD apparatus, the SiO ₂ mask 4 is used as an etching mask to form the n-type GaN channel layer 3 at 700 ° C., for example, at 200 n.
Vapor phase etching is selectively performed by m. In this vapor phase etching, for example, N ₂ gas containing 1% of HCl gas is used as an etching gas. By this vapor phase etching, as shown in FIG. 3, the upper layers of the n-type GaN channel layer 3 and the undoped GaN layer 2 are patterned into a stripe shape. In this vapor phase etching,
Since the etching is carried out thermochemically and the etching rate is well controlled by temperature, the controllability of etching is good. Further, unlike the case where the etching is performed by using the RIE method, the etching surface is not damaged or the etching residue is not generated.

Next, the substrate temperature is once lowered, and H in the reaction furnace is lowered.
After sufficiently purging Cl gas, the substrate temperature is raised to 950 ° C. while introducing H ₂ gas and NH ₃ gas into the reaction furnace. Next, as a Ga raw material, TMG is supplied into the reaction furnace at a flow rate of, for example, about 10 μmol / min, and the SiO ₂ mask 4 is used as a growth mask, as shown in FIG.
The n ⁺ -type GaN layer 5 is selectively grown by the VD method, and the portion removed by the above vapor phase etching is filled. The carrier concentration of the n ⁺ -type GaN layer 5 is, for example, 5 × 10 ^18.
The cm ^-3 and the thickness are, for example, 0.3 μm. Here, one side of the n-type GaN channel layer 3 (for example, the left side in FIG. 4)
N ⁺ -type GaN layer 5 constitutes the source region, the other side (for example, in FIG. 4 right) n ⁺ -type GaN layer 5 constituting the drain region of the. In this case, in the same reactor,
N on a clean surface formed by the vapor phase etching described above.
^{Since the +} type GaN layer 5 is grown, a good quality n ⁺ type G
The aN layer 5 can be grown. In addition, n-type GaN
Since the SiO ₂ mask 4 used in the etching of the channel layer 3 is used directly in the growth mask for n ⁺ -type GaN layer 5, the n ⁺ -type GaN layer with respect to n-type GaN channel layer 35
Can grow in a self-aligned manner.

Next, after the c-plane sapphire substrate 1 is taken out of the reaction furnace, as shown in FIG. 5, a predetermined portion of the n ⁺ -type GaN layer 5 is undoped using a resist pattern (not shown) as a mask, for example. The element isolation region 6 is formed by selectively implanting He, for example, with the energy reaching the GaN layer 2. After that, the resist pattern used as the mask for this ion implantation is removed.

Next, a resist pattern (not shown) having a predetermined shape for forming the source electrode and the drain electrode is formed by lithography, and then, for example, a Ti / Al film is formed on the entire surface by, for example, a vacuum evaporation method. Next, the resist pattern is removed together with the Ti / Al film formed thereon (lift-off). Thus, one side of the n ⁺ -type GaN layer 5 and the other side of the n ⁺ -type GaN layer respectively on the 5 source electrode 7 and the drain electrode 8 of n-type GaN channel layer 3 is formed. After that, in order to reduce the contact resistance of the source electrode 7 and the drain electrode 8, for example, 8
Heat treatment (flash annealing) under conditions of 00 ° C and 30 seconds
I do.

Next, an opening 4a is formed in a predetermined portion of the SiO ₂ mask 4 on the n-type GaN channel layer 3 by lithography and etching. For the etching of the SiO ₂ mask 4, for example, wet etching using a hydrofluoric acid-based etching solution or RIE method using a fluorine-based etching gas is used. Next, after forming, for example, a Ti / W film on the entire surface, the resist pattern is removed together with the Ti / W film formed thereon. As a result, the gate electrode 9 is formed in Schottky contact with the n-type GaN channel layer 3 through the opening 4a.

From the above, the desired GaN MESF
ET is manufactured. This GaN MESFET is shown in FIG.
The energy band diagram of is shown. In FIG. 6, E
_F is the Fermi level, E _c is the energy at the bottom of the conduction band,
E _v represents the energy at the top of the valence band (same below).

As described above, according to the first embodiment, the n-type GaN channel layer 3 and the undoped G are formed by using the SiO ₂ mask 4 in the reaction furnace of the MOCVD apparatus.
After selectively etching the aN layer 2 in the vapor phase, subsequently, an n ⁺ -type GaN layer 5 is selectively grown by using the SiO ₂ mask 4 on the portion removed by this etching, and these n ⁺ -type By using the GaN layer 5 as a source region and a drain region, forming the source electrode 7 and the drain electrode 8 on the source region and the drain region, respectively, and forming the gate electrode 9 on the n-type GaN channel layer 3, A GaN MESFET can be manufactured. Further, the carrier concentration is 4 × 10 ¹⁷ cm ⁻³
The contact resistance when the source electrode 7 and the drain electrode 8 are brought into contact with the n-type GaN channel layer 3 of 10 ^-4 Ω
Although it is as high as cm ² , in the first embodiment,
Since the n ⁺ -type GaN layer 5 having a high carrier concentration of 5 × 10 ¹⁸ cm ⁻³ is grown and the source electrode 7 and the drain electrode 8 are brought into contact with the n ⁺ -type GaN layer 5, the source electrode 7 and the drain electrode 8 contact resistance is 3 ×
It can be remarkably reduced to about 10 ⁻⁶ Ωcm ² .
Furthermore, since the n ⁺ -type GaN layer 5 as the source region can be formed close to the gate electrode 9, the source resistance can be significantly reduced.

As described above, the characteristics of the n-type GaN channel layer 3 can be fully exhibited, and a high-speed, high-power, high-performance GaN MESFET can be realized.

Next, G according to the second embodiment of the present invention
aN / GaInN Pseudomorphic High Electron Mobility Transistor
A method of manufacturing HEMT will be described.

In the second embodiment, first, as shown in FIG. 7, an undoped GaN layer 2 and a channel layer are formed on a c-plane sapphire substrate 1 via a buffer layer (not shown) made of AlN or GaN. 10 are sequentially grown by the MOCVD method. The thickness of the undoped GaN layer 2 is 800 nm, for example.

In this case, as shown in FIG. 8, the channel layer 10 includes an n ⁺ -type GaN layer 101, an undoped GaInN layer.
Layer 102, n ⁺ -type GaN layer 103 and undoped Al
It is composed of the GaN layer 104. Here, the n ⁺ -type GaN layer 10
The carrier concentration of 1 is, for example, 2 × 10 ¹⁸ cm ⁻³ , and the thickness is, for example, 10 nm. In addition, the undoped GaInN layer 1
For example, the In composition ratio of 02 is 0.2 and the thickness is 15 n.
m. The carrier concentration of the n ⁺ -type GaN layer 103 is, for example, 2 × 10 ¹⁸ cm ⁻³ , and the thickness thereof is, for example, 10 nm. Further, the Al composition ratio of the undoped AlGaN layer 104 is, for example, 0.5, and the thickness thereof is, for example, 30 nm.

Next, as shown in FIG. 9, as in the first embodiment, a stripe-shaped SiO ₂ mask 4 is formed on the channel layer 10, and this SiO ₂ mask 4 is used as an etching mask. The upper layer portion of the channel layer 10 and the undoped GaN layer 2 is selectively vapor-phase etched at 700 ° C. by 200 nm, for example. By this vapor phase etching, the upper layer portion of the channel layer 10 and the undoped GaN layer 2 is patterned into a stripe shape.

Next, as in the first embodiment, MOCVD is performed using the SiO ₂ mask 4 as a growth mask.
The n ⁺ -type GaInN layer 11 is selectively grown by, for example, 750 ° C. by a method to fill the portion removed by the vapor phase etching described above. The In composition of the n ⁺ type GaInN layer 11 is, for example, 0.2, and the carrier concentration is, for example, 1 × 10 ¹⁹ c.
m ⁻³ and the thickness are, for example, 15 nm. Here, the n ⁺ -type Ga on one side of the channel layer 10 (for example, the left side in FIG. 9) is used.
The InN layer 11 constitutes a source region, and the n ⁺ -type GaInN layer 11 on the other side (for example, the right side in FIG. 9) constitutes a drain region.

Next, after the c-plane sapphire substrate 1 is taken out of the reaction furnace, as shown in FIG. 10, for example, using a resist pattern (not shown) as a mask, n ⁺ type GaInN is used.
Element isolation regions 6 are formed by selectively ion-implanting, for example, He into the predetermined portion of the layer 11 with energy reaching the undoped GaN layer 2. After that, the resist pattern used as the mask for this ion implantation is removed.

Next, an opening 4a is formed in the SiO ₂ mask 4 on the channel layer 10 by lithography and etching. Next, after forming a resist pattern (not shown) having a predetermined shape for forming the gate electrode, the source electrode and the drain electrode by lithography, for example, a Ti / Al / Pt film is formed on the entire surface by, for example, a vacuum evaporation method.
Next, a resist pattern is formed on the Ti / A
It is removed together with the l / Pt film. As a result, as shown in FIG. 10, the n ⁺ -type GaI on one side of the channel layer 10 is formed.
A source electrode 7 and a drain electrode 8 are formed on the nN layer 11 and the n ⁺ -type GaInN layer 11 on the other side, respectively, and a gate electrode 9 is formed on the channel layer 10. After that, in order to reduce the contact resistance between the source electrode 7 and the drain electrode 8, heat treatment (flash annealing) is performed under the conditions of, for example, 800 ° C. and 30 seconds.

From the above, the desired GaN / GaIn
An N-pseudostructure HEMT is manufactured. This Ga is shown in FIG.
The energy band diagram of N / GaInN pseudo structure HEMT is shown.

This GaN / GaInN pseudo structure H
In the EMT, since the gate electrode 9 has a so-called MIS structure in which the gate electrode 9 is directly in contact with the uppermost undoped AlGaN layer 104 of the channel layer 10, the gate electrode 9 does not need to be in Schottky contact with the channel layer 10. Can be formed simultaneously with the source electrode 7 and the drain electrode 8.

This GaN / GaInN pseudo structure HEMT
In the channel layer 10, undoped GaI
The nN layer 102 serves as a channel layer in which carriers actually travel. In this case, the undoped GaInN layer 102
N ⁺ type GaN layer 101 and n ⁺ type GaN layer 1 above and below
A so-called modulation-doped structure in which electrons are supplied to the undoped GaInN layer 102 from 03.

As described above, according to the second embodiment, the channel layer 10 and the undoped GaN layer 2 are formed by using the SiO ₂ mask 4 in the reaction furnace of the MOCVD apparatus.
The after selectively etching in a gas phase, and subsequently, these n ⁺ -type buried by selectively growing an n ⁺ -type GaInN layer 11 by using a SiO ₂ mask 4 to the removed portion by etching The GaInN layer 11 is used as a source region and a drain region, the source electrode 7 and the drain electrode 8 are formed on the source region and the drain region, and the undoped AlGaN layer 104 is formed.
By forming the gate electrode 9 on the GaN / Ga
An InN pseudostructure HEMT can be manufactured. Further, in the second embodiment, the carrier concentration is 1
× 10 ¹⁹ cm ^-3 and grown high n ⁺ -type GaInN layer 11, since the n ⁺ -type GaInN layer 11 is contact with the source electrode 7 and the drain electrode 8, the contact of the source electrode 7 and drain electrode 8 resistance Can be made sufficiently small. Further, n ⁺ type G as a source region
Since the aInN layer 11 can be formed close to the gate electrode 9, the source resistance can be significantly reduced.

As described above, the undoped GaInN102 is used as the channel layer in which carriers travel, at high speed,
A high-power, high-performance GaN / GaInN pseudostructure HEMT can be realized. This GaN / GaInN pseudo structure HEMT can be manufactured only by the method according to the second embodiment. That is, since it is impossible to make ohmic contact between the source electrode 7 and the drain electrode 8 via the undoped AlGaN layer 104 of the channel layer 10, the undoped AlGa in the contact portion of the source electrode 7 and the drain electrode 8 is not possible.
The N layer 104 needs to be removed by etching, but in the etching by the normal RIE method, the n underneath is removed at that time.
^{This is because the +} -type GaN layer 103 and the like are damaged and the carriers disappear, and good ohmic contact cannot be obtained.

Next explained is a method of manufacturing a GaN MESFET having a recess gate structure according to the third embodiment of the invention.

In the third embodiment, first, as shown in FIG. 12, an undoped GaN layer 2 and an n-type GaN layer 2 are formed on a c-plane sapphire substrate 1 via a buffer layer (not shown) made of AlN or GaN. GaN channel layer 3 and n
^{The +} type GaInN layer 11 is sequentially grown by the MOCVD method. The thickness of the undoped GaN layer 2 is, for example, 2 μm. The carrier concentration of the n-type GaN channel layer 3 is, for example, 4 × 10 ¹⁷ cm ⁻³ , and the thickness thereof is, for example, 160 nm. Further, the In composition ratio of the n ⁺ -type GaInN layer 11 is, for example, 0.5, the carrier concentration is, for example, 1 × 10 ¹⁹ cm ⁻³ ,
The thickness is 100 nm, for example.

Next, as shown in FIG. 13, an SiO ₂ mask 4 having a stripe-shaped opening 4a is formed on the n ⁺ -type GaInN layer 11 in the same manner as in the first embodiment, and then this SiO is formed. _{2 Using the} mask 4 as an etching mask, the n ⁺ -type GaInN layer 11 is formed at 650 ° C., 2
Gas phase etching is selectively performed under the condition of 0 minutes to expose the n-type GaN channel layer 3. In this vapor phase etching, N ₂ gas mixed with 1% of HCl gas is used as an etching gas. By this vapor phase etching, n ⁺ type G
Stripe-shaped openings 11a are formed in the aInN layer 11. In this vapor phase etching, n ⁺ type GaIn
The underlying n-type GaN channel layer 3 of the N layer 11 is hardly etched, and a flat surface appears. In addition, n ⁺ type G
The higher the In composition ratio of the aInN layer 11, the higher the etching selection ratio of the n ⁺ -type GaInN layer 11 to the n-type GaN channel layer 3.

Next, after the c-plane sapphire substrate 1 is taken out of the reaction furnace, as shown in FIG. 14, for example, using a resist pattern (not shown) as a mask, n ⁺ type GaInN is used.
Element isolation regions 6 are formed by selectively ion-implanting, for example, He into the predetermined portion of the layer 11 with energy reaching the undoped GaN layer 2. After that, the resist pattern used as the mask for this ion implantation is removed.

Next, openings 4b and 4c are formed in the SiO ₂ mask 4 by lithography and etching. Next, after forming a resist pattern (not shown) having a predetermined shape for forming the gate electrode, the source electrode and the drain electrode by lithography, a Ti / W film, for example, is formed on the entire surface by, for example, a vacuum evaporation method. Next, the resist pattern is removed together with the Ti / W film formed thereon. As a result, the n ⁺ type G on one side of the gate electrode 9 is formed.
aInN layer 11 and n ⁺ -type GaInN layer 1 on the other side
1 and a source electrode 7 and a drain electrode 8 are formed on the first substrate 1 through openings 4b and 4c, respectively.
A gate electrode 9 is formed on the channel layer 3 through the opening 4a. After that, in order to reduce the contact resistance between the source electrode 7 and the drain electrode 8, heat treatment (flash annealing) is performed under the conditions of, for example, 800 ° C. and 30 seconds.

As described above, the intended GaN MESFET having the recess gate structure is manufactured.

As described above, according to the third embodiment, the undoped GaN layer 2, the n-type GaN channel layer 3 and the n ⁺ -type GaInN layer 11 are sequentially grown by the MOCVD method, and then the SiO ₂ mask 4 is formed. Using n ⁺ type GaI
A source region and a drain region are formed by etching the nN layer 11, a source electrode 7 and a drain electrode 8 are formed on these source region and drain region, respectively, and a gate electrode 9 is formed on the n-type GaN channel layer 3. By forming the GaN MESFET, a GaN MESFET having a recess gate structure can be manufactured. In addition, in the third embodiment, the carrier concentration is 1
Since the source electrode 7 and the drain electrode 8 are brought into contact with the n ⁺ -type GaInN layer 11 having a high x 10 ¹⁹ cm ⁻³ , the contact resistance between the source electrode 7 and the drain electrode 8 can be made sufficiently small. Further, since the n ⁺ type GaInN layer 11 as the source region can be formed close to the gate electrode 9, the source resistance can be significantly reduced.

As described above, the characteristics of the n-type GaN channel layer 3 can be fully exhibited, and a high-speed, high-power, high-performance recess gate structure GaN MESFET can be realized.

Next, a GaN / GaInN pseudo structure reverse HEM having a recess gate structure according to the fourth embodiment of the present invention.
A method of manufacturing T will be described.

As shown in FIG. 15, the method for manufacturing a GaN / GaInN pseudo structure reverse HEMT having a recess gate structure according to the fourth embodiment is such that an undoped layer is formed on a c-plane sapphire substrate 1 via a buffer layer (not shown). GaN layer 2,
Undoped AlGaN layer 104, n ⁺ type GaN layer 10
1, undoped GaInN layer 102, n ⁺ type GaN layer 1
03 and the n ⁺ -type GaInN layer 11 are sequentially grown, and the manufacturing method of the GaN MESFET having the recess gate structure according to the third embodiment is the same. Here, the thickness of the undoped GaN layer 2 is, for example, 800 nm,
The Al composition ratio of the undoped AlGaN layer 104 is, for example, 0.15, the thickness is, for example, 200 nm, and the n ⁺ -type GaN layer 1 is used.
The carrier concentration of 01 is, for example, 2 × 10 ¹⁸ cm ⁻³ , the thickness is, for example, 10 nm, and In of the undoped GaInN layer 102 is In.
The composition ratio is 0.2, the thickness is 15 nm, and the carrier concentration of the n ⁺ -type GaN layer 103 is 4 × 10 ¹⁷ cm, for example.
^-3 , the thickness is, for example, 50 nm, the In composition ratio of the n ⁺ -type GaInN layer 11 is, for example, 0.5, and the carrier concentration is, for example, 1 ×.
10 ¹⁹ cm ⁻³ , and the thickness is 100 nm, for example.

According to the fourth embodiment, it is possible to realize a high-speed, high-power, high-performance recess gate structure GaN / GaInN pseudo-structure inverse HEMT.

Next explained is a method of manufacturing a semiconductor laser having a buried hetero structure (BH) according to the fifth embodiment of the invention.

In the fifth embodiment, first, as shown in FIG. 16, MOCVD is performed on an n-type SiC substrate 21.
The n ⁺ -type GaN layer 22, the n-type AlGaN cladding layer 23, the active layer 24, the p-type AlGaN cladding layer 25, and the p-type GaN cap layer 26 are sequentially grown by the method. Here, the active layer 24 has n layers above and below the undoped GaInN layer.
The p-type GaN layer and the p-type GaN layer have a sandwiched structure. In this case, the carrier concentration of the n ⁺ -type GaN layer 22 is, for example, 5 × 10 ¹⁸ cm ⁻³ , and the thickness thereof is, for example, 3 μm. n
The Al composition ratio of the type AlGaN layer 23 is, for example, 0.15, the carrier concentration is, for example, 5 × 10 ¹⁷ cm ⁻³ , and the thickness is, for example, 5
00 nm. In addition, in the active layer 24, n-type Ga
The carrier concentration of the N layer is, for example, 1 × 10 ¹⁷ cm ⁻³ , the thickness is, for example, 100 nm, the In composition ratio of the undoped GaInN layer is, for example, 0.2, the thickness is, for example, 50 nm, and p-type GaN is used.
The carrier concentration of the layer is, for example, 1 × 10 ¹⁷ cm ⁻³ , and the thickness is, for example, 100 nm. p-type AlGaN cladding layer 25
Has an Al composition ratio of 0.15, a carrier concentration of 1 × 10 ¹⁷ cm ⁻³ , and a thickness of 500 nm, for example. p
Type GaN layer 26 has a carrier concentration of, for example, 3 × 10 ¹⁷ cm
^-3 , and the thickness is, for example, 500 nm.

Next, in the same manner as in the first embodiment, a stripe-shaped SiO ₂ mask 4 having a width of, for example, 5 μm is formed on the p-type GaN layer 26. Next, this Si
Using the O ₂ mask, vapor phase etching is performed to a depth of 1.4 μm in the same manner as in the first embodiment.
As a result, as shown in FIG. 17, the n ⁺ -type GaN layer 2
2, the n-type AlGaN cladding layer 23, the active layer 24, the p-type AlGaN layer 25, and the p-type GaN cap layer 26 are patterned into a stripe shape.

Next, as shown in FIG. 18, p-type A was formed by MOCVD using the SiO ₂ mask 4 as a growth mask.
p ^- type Al up to almost the same height as the lGaN cladding layer 25
After selectively growing the GaN layer 27, the p-type GaN layer 28 is subsequently grown to the same height as the p-type GaN cap layer 26.
Grow selectively. Here, the p ⁻ -type AlGaN layer 2
7 has an Al composition ratio of 0.2, a carrier concentration of 1 × 10 ¹⁶ cm ⁻³ , and a thickness of 900 nm, for example. The carrier concentration of the p-type GaN layer 28 is, for example, 3 × 10.
^{It is 17} cm ⁻³ and the thickness is, for example, 500 nm.

Next, the SiO ₂ mask 4 is removed by etching, for example, by a wet etching method. Next, FIG.
, The p-type GaN cap layer 26 and the p-type G
A p-side electrode 29 such as a Ni / Au electrode is formed on the surface of the aN layer 28, and an n-side electrode 30 such as a Ti / Al electrode is formed on the back surface of the n-type SiC substrate 21. As described above, the intended semiconductor laser having a buried hetero structure is manufactured.

As described above, according to the fifth embodiment, a buried heterostructure semiconductor laser using a GaN-based semiconductor can be realized by the selective etching and selective growth similar to those of the first embodiment. it can. This buried heterostructure semiconductor laser has the characteristics of a conventional index-guided semiconductor laser. Further, since the p-side electrode 29 is a full-surface electrode, its contact resistance can be reduced.

The embodiments of the present invention have been specifically described above, but the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, the numerical values given in the above embodiments are merely examples, and different numerical values may be used if necessary.

For example, a GaInN layer doped with an n-type impurity such as Si may be used instead of the undoped GaInN layer 102 of the channel layer 10 in the second embodiment described above. In addition, the undoped GaN layer 2 in the above-described first to fourth embodiments may become n-type depending on the growth conditions, and the insulating property may be deteriorated. Mg, which is a p-type impurity, is added to the bottom or the whole of the GaN layer 2 by, for example, 10 ¹⁶
You may make it dope to the density ^| concentration of cm ^<-3 >.

[0074]

As described above, according to the method for etching a nitride-based compound semiconductor according to the present invention, since the etching is performed thermochemically in the vapor phase, the nitride-based compound semiconductor such as GaN is damaged. It is possible to perform etching with good controllability and without causing.

Further, according to the method for manufacturing a semiconductor device of the present invention, since etching can be performed in the reaction furnace of the vapor phase growth apparatus, the nitride-based compound semiconductor in the reaction furnace of the vapor phase growth apparatus can be etched. After performing the selective etching, subsequently, in this reaction furnace, the compound semiconductor can be selectively grown and embedded in the clean surface of the selectively etched portion. Further, since the insulating film used as the selective etching mask is used as it is as the selective growth mask, the compound semiconductor can be embedded in a self-aligned manner in the portion removed by the selective etching. As a result, a high-performance semiconductor device using a nitride compound semiconductor can be manufactured with a high yield.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing temperature dependence of an etching rate of a GaN layer.

FIG. 2 is a GaN ME according to a first embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the SFET.

FIG. 3 is a GaN ME according to a first embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the SFET.

FIG. 4 is a GaN ME according to the first embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the SFET.

FIG. 5 is a GaN ME according to the first embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the SFET.

FIG. 6 is a GaN ME according to the first embodiment of the present invention.
It is an energy band figure of SFET.

FIG. 7 GaN / Ga according to a second embodiment of the present invention.
FIG. 6 is a cross-sectional view for explaining the method of manufacturing the InN pseudo structure HEMT.

FIG. 8 is a GaN / Ga according to a second embodiment of the present invention.
It is a partially expanded sectional view which shows the detail of the structure of the channel layer of InN pseudo structure HEMT.

FIG. 9 is a GaN / Ga according to a second embodiment of the present invention.
FIG. 6 is a cross-sectional view for explaining the method of manufacturing the InN pseudo structure HEMT.

FIG. 10 is a GaN / G according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the aInN pseudo structure HEMT.

FIG. 11 is a GaN / G according to a second embodiment of the present invention.
It is an energy band diagram of aInN pseudo structure HEMT.

FIG. 12 is a cross-sectional view illustrating the method of manufacturing the GaN MESFET having the recess gate structure according to the third embodiment of the present invention.

FIG. 13 is a cross-sectional view illustrating the method of manufacturing the GaN MESFET having the recess gate structure according to the third embodiment of the present invention.

FIG. 14 is a cross-sectional view illustrating the method of manufacturing the GaN MESFET having the recess gate structure according to the third embodiment of the present invention.

FIG. 15 is a cross-sectional view illustrating the method of manufacturing the GaN / GaInN pseudo structure HEMT having the recess gate structure according to the fourth embodiment of the present invention.

FIG. 16 is a sectional view for illustrating the method for manufacturing the semiconductor laser having the buried hetero structure according to the fifth embodiment of the present invention.

FIG. 17 is a sectional view for illustrating the method for manufacturing the buried hetero structure semiconductor laser according to the fifth embodiment of the present invention.

FIG. 18 is a sectional view for illustrating the method for manufacturing the buried hetero structure semiconductor laser according to the fifth embodiment of the present invention.

FIG. 19 is a cross-sectional view illustrating the method of manufacturing the GaN pseudo-match HEMT having the recess gate structure according to the fifth embodiment of the present invention.

FIG. 20 is a cross-sectional view showing a conventional GaAs MESFET.

FIG. 21: GaAs MES having a conventional recess gate structure
It is sectional drawing which shows FET.

[Explanation of symbols]

1 ... c-plane sapphire substrate, 2 ... undoped Ga
N layer, 3 ... N-type GaN channel layer, 4 ... SiO
₂ mask, 5 ... n ⁺ type GaN layer, 6 ... element isolation region, 7 ... source electrode, 8 ... drain electrode, 9
... Gate electrode, 10 ... Channel layer, 101, 1
03 ... n ⁺ type GaN layer, 102 ... undoped G
aInN layer, 104 ... Undoped AlGaN layer, 1
1 ... n ⁺ type GaInN layer, 21 ... n type SiC substrate, 23 ... n type AlGaN layer, 24 ... active layer,
25 ... p-type AlGaN layer, 27 ... p ^- type AlG
aN layer, 28 ... p-type GaN layer, 29 ... p-side electrode, 30 ... n-side electrode

Continuation of front page (56) Reference JP-A-7-254733 (JP, A) JP-A-2-291125 (JP, A) JP-A-8-46291 (JP, A) JP-A-7-86183 (JP , A) JP-A-9-45670 (JP, A) Takuo Sugano, Semiconductor dry etching technology, Japan, Sangyo Tosho, October 6, 1992, first edition, P229-233 (58) Fields investigated (Int.Cl . ^7, DB name) H01L 21/302 201 H01L 21/338 H01L 29/41 H01L 29/778 H01L 29/812

Claims (21)

(57) [Claims] 1. A hydrogen gas and mixed gas or Ranaru etching gas of the second gas comprising a first gas and a halogen gas and a halogen gas of a compound with carbon composed of at least one of the inert gas A method for etching a nitride-based compound semiconductor, characterized in that the nitride-based compound semiconductor is vapor-phase-etched by using. 2. A small amount of hydrogen gas and inert gas
That the nitride-based compound semiconductor using an etching gas comprising a mixed gas of a second gas comprising a first gas and a halogen gas of a compound with carbon made of one Kutomo was such that vapor-phase etching Characteristic nitride compounds
Semiconductor etching method. 3. The partial pressure of the second gas is several Torr to normal.
According to claim 1 or 2 nitride-based compound semiconductor etching method according you being a pressure. 4. The nitride compound at a temperature of 400 ° C. or higher.
According to claim 1 or 2 nitride compound semiconductor etching method according to the object semiconductor, characterized in that as gas-phase etching grayed. 5. The partial pressure of the second gas is several Torr to normal.
3. The method for etching a nitride-based compound semiconductor according to claim 1, wherein the nitride-based compound semiconductor is vapor-phase etched at a temperature of 400 ° C. or higher . 6. The above-mentioned portion other than the portion to be etched
6. The nitride-based compound semiconductor is covered with an insulating film, and the nitride-based compound semiconductor is selectively vapor-phase etched using the insulating film as a mask. Item 7. A method for etching a nitride-based compound semiconductor according to the item. 7. The temperature above 400 ° C. and below 800 ° C.
Any one nitride-based compound semiconductor method of etching as claimed in claim 1-5, characterized in that there was Unishi by performing vapor phase etching. 8. The above at a temperature of 500 ° C. to 700 ° C.
Any one nitride-based compound semiconductor method of etching as claimed in claim 1-5, characterized in that there was Unishi by performing vapor phase etching. 9. The nitride compound semiconductor is Al or Ga.
At least one I selected Ri by the group and consisting of In
2. A group II element and N are included.
6. The method for etching a nitride compound semiconductor according to any one of 5 above. 10. A semiconductor using a nitride-based compound semiconductor
In the method of manufacturing a device, the nitride-based compound in the portion other than the portion to be etched
The surface of the semiconductor is covered with an insulating film, and the insulating film is used as a mask to form a second gas containing a first gas containing at least one of hydrogen gas and an inert gas, a halogen gas, and a gas containing a compound of halogen and carbon. A step of selectively vapor-phase etching the nitride-based compound semiconductor using an etching gas composed of a mixed gas with a gas, and using the insulating film as a mask, the nitride-based compound semiconductor
And a step of selectively growing and burying a compound semiconductor in the selectively vapor-phase-etched portion of
A method for manufacturing a characteristic semiconductor device. 11. A semiconductor using a nitride compound semiconductor.
In the method of manufacturing a device, the nitride-based compound in the portion other than the portion to be etched
By covering the surface of the semiconductor with an insulating film and using the insulating film as a mask, a first gas containing at least one of hydrogen gas and an inert gas and a second gas containing a compound gas of halogen and carbon are formed. A step of selectively vapor-phase etching the nitride compound semiconductor using an etching gas composed of a mixed gas; and using the insulating film as a mask, the nitride compound semiconductor
And a step of selectively growing and burying a compound semiconductor in the selectively vapor-phase-etched portion of
A method for manufacturing a characteristic semiconductor device. 12. The partial pressure of the second gas is from several Torr to
The method for manufacturing a semiconductor device according to claim 10, wherein the method is a normal pressure . 13. The nitride system conversion at a temperature of 400 ° C. or higher.
Method for producing a compound semiconductor device according to claim 10 or 11 wherein it has to be gas phase-etched ring. 14. The partial pressure of the second gas is from several Torr to
Normal is pressure, a method of manufacturing a semiconductor device according to claim 10 or 11, wherein the temperature on 400 ° C. or more and the nitride-based compound semiconductor so as to vapor-phase etching. 15. The temperature above 400 ° C. and below 800 ° C.
15. The method for manufacturing a semiconductor device according to claim 10, wherein vapor phase etching is performed . 16. The temperature is above 500 ° C. and below 700 ° C.
15. The method for manufacturing a semiconductor device according to claim 10, wherein vapor phase etching is performed . 17. The nitride-based compound semiconductor is Al or G
2. At least one Group III element selected from the group consisting of a and In, and N.
The method of manufacturing a semiconductor device according to any one of 0 to 14. 18. The embedded compound semiconductor is small.
The method of manufacturing a semiconductor device according to any one of claims 10-14, characterized in that the Kutomo Ga and N is including nitride compound semiconductor. 19. The embedded compound semiconductor is arsenic.
The method of manufacturing a semiconductor device according to any one of claims 10-14, characterized in that the system III-V compound semiconductors. 20. The embedded compound semiconductor is phosphorus.
The method of manufacturing a semiconductor device according to any one of claims 10-14 to system III-V compound semiconductor der wherein Rukoto. 21. The above-mentioned filling by a metal organic chemical vapor deposition method.
The method for manufacturing a semiconductor device according to claim 10, wherein a compound semiconductor to be embedded is grown .