JP3481060B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having multi-layered metal wiring and a method of manufacturing the same, and more particularly to a semiconductor device having multi-layered wiring in which upper and lower metal wiring layers are connected via a flattened interlayer insulating film. The present invention relates to a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, the wiring portion of a semiconductor device has become multi-layered due to miniaturization. In a multilayer wiring structure, flattening of an interlayer insulating film is an important technical issue in order to realize a finer line and space of wiring and a diameter of a connection hole.

In recent years, CMP (Chemical Mecha
Nical Polishing (Chemical Mechanical Polishing) technology is often used, and its flatness is further improved. With the improvement of the flatness, the depth of the connection hole connecting the wirings, that is, the film thickness of the interlayer insulating film causes a large difference between the places where the connection hole is formed, and sometimes exceeds the maximum. like this,
When forming a contact hole by dry etching in a place where the film thickness of the interlayer insulating film is different, it is necessary to perform etching under the condition matched with the thick interlayer insulating film. At this time,
The contact hole arranged in a place where the film thickness is thin is subjected to extreme over-etching, and causes large etching damage to the underlying wiring.

This situation will be described with reference to FIG. This problem occurs when the fine connection holes 105 and 108 and the large-area bonding pad portion 109 are simultaneously formed. That is, the first-layer metal wiring 103 is formed on the first-layer interlayer insulating film 101, and the metal wiring 103 is electrically connected to the underlying substrate through the connection hole 102 of the interlayer insulating film 101. ing. A second-layer interlayer insulating film 104 is formed on the metal wiring 103, and a small-sized second connection hole 105 and a large-sized bonding pad portion 109 are formed.
At the same time. Further, on the upper layer, a third-layer interlayer insulating film 107 is formed via a second-layer metal wiring layer 106, and a small-sized third connection hole 108 and a large-sized bonding pad portion 109 are simultaneously opened. Make a hole.

In such a forming process, the second interlayer insulating film 104 and the third interlayer insulating film 107 are
Conventional coating film SOG (Spin On Glas) that does not use CMP
s: Spin-on-glass) When formed using an etch-back process, the surface of the interlayer insulating film falls in the large-sized bonding pad part, so the film of the interlayer insulating film in the fine hole part and the bonding pad part There was no significant difference in thickness. Therefore, each connection hole 105, 1
The damage due to over-etching on the underlying metal wiring when etching 08 was not a problem. However, when the planarization of each interlayer insulating film is further performed using CMP, the following problems have occurred.

The first fine connection holes 10 are formed in the first-layer interlayer insulating film 101 planarized by heat treatment reflow and in the second-layer interlayer insulating film 104 planarized by CMP, respectively.
2 and the second fine connection hole 105 are formed, the second layer metal wiring layer 106 and the third-layer interlayer insulating film 107 flattened by CMP are formed, and then the third fine connection hole 108 and the bonding are performed. When the opening 109 of the pad portion is simultaneously opened by etching, the second fine metal interconnection layer 108 causes significant etching damage due to overetching in the second metal wiring layer 106. The cause of this is the fine connection part 1.
This is because the thickness a of the interlayer insulating film 107 of No. 08 is significantly smaller than the thickness b of the interlayer insulating film 107 of the pad portion, so that the third fine connection portion 108 undergoes extreme over-etching.

Various methods have been proposed in order to solve the problem due to the difference in the film thickness of the interlayer insulating film. (1) In the first method, a second wiring layer is formed on a first connection hole opened to electrically connect to the first metal wiring layer, and the first wiring hole is formed. Regarding a method for forming a third wiring layer on a second connection hole on a second wiring layer, in the case of arranging a second connection hole on a lower first connection hole First, a first silicon oxide-based interlayer film is formed so as to fill the recess of the second wiring layer formed in the first connection hole and the space portion between the wirings, and is etched back. At this time, the space between the wirings and the recess of the second wiring layer formed in the first connection hole are filled with the silicon oxide film, and a part of the surface of the second wiring layer is exposed. . After that, a silicon nitride film is formed over the entire surface, and a silicon oxide film is further stacked to form a second interlayer film. When the second connection hole is arranged so as to overlap the first connection hole, the silicon nitride film acts as an etching stopper to enable etching with a small aspect ratio. Further, this silicon nitride film is etched to expose a part of the surface of the second wiring layer in the connection hole to form a third wiring layer (see Japanese Patent Laid-Open No. 3-245531). According to this method, the interlayer film thickness on the wiring layer in the connection hole becomes equal in all cases, and the location dependence of overetching at the time of etching the second connection hole is eliminated.

(2) In the second method, when a fine connection hole for connecting the silicon substrate and the metal wiring layer is formed on the gate electrode of the miniaturized polysilicon, a gap between the wirings or a wiring is formed due to misalignment. In order to prevent a short circuit between the substrates, an interlayer insulating film in which insulating films having different etching selectivity are laminated is used (Japanese Patent Laid-Open No. 3-78227, Japanese Patent Laid-Open No. 3-78227).
-187220, JP-A-5-243520, JP-A-6-151352, JP-A-7-221
194). The technology is SAC (Self Align C
In this technique, a laminated film of a silicon oxide film and a silicon nitride film is used as a material having etching selectivity as an interlayer insulating film between the silicon substrate and the first-layer metal wiring.

(3) A third method is to dispose an etching stopper such as a silicon nitride film having a different etching selectivity on the first-layer interlayer insulating film formed on a silicon substrate during contact hole etching. No etching damage to the underlying silicon substrate of JP-A-62-185375, JP-A-2-
239625, JP 4-30572 A, JP 4-317357 A, JP 5-13434 A).

On the other hand, as an example using the CMP technique, a laminated film of a silicon nitride film and a silicon oxide film is used as an interlayer insulating film between wirings, and a silicon nitride film is used as the CMP of the interlayer insulating film.
A method of using it as a polishing stopper for polishing has been proposed (JP-A-5-226334).

[0011]

According to the first method,
Since only a part of the surface of the wiring layer in the second connection hole can be exposed, the contact area with the wiring in the upper layer is reduced and the contact resistance is increased. As a result, the current density increases at that portion, and electromigration of the connection hole occurs, causing a problem in reliability.

The SAC technique of the second method and the third method are
This is a method of using a laminated film of a silicon oxide film and a silicon nitride film as an interlayer insulating film between a silicon substrate and a first-layer metal wiring, and does not relate to an interlayer insulating film between metal wirings which is the object of the present invention. Absent.

A method of using a silicon nitride film as a polishing stopper in the CMP technique is to form a large-area connecting hole and a fine connecting hole such as a bonding pad formed in an interlayer insulating film between metal wirings flattened by CMP. It does not solve the problem of etching caused by the difference in film thickness of the interlayer insulating film between the two. This method is poor in reproducibility because the characteristics of the polishing stop by the silicon nitride film are greatly affected by the density and area of the patterned wiring. Further, when a silicon nitride film is used as a polishing stopper for CMP in a multi-layered wiring which is the subject of the present invention, not only does it not work effectively with a connection hole having a large area such as a bonding pad, The problem of damage to the underlying metal wiring during etching of contact holes cannot be solved at all. It is an object of the present invention to solve overetching caused by a difference in film thickness of a planarized interlayer insulating film, which occurs between a fine connection hole and a large opening such as a bonding pad when forming a multilayer wiring. It is a thing.

[0014]

The semiconductor device of the present invention comprises:
A flattened first-layer interlayer insulating film is formed on a semiconductor substrate on which a semiconductor element is formed, and is electrically connected through a first connection hole through the first-layer interlayer insulating film. A first metal wiring layer is formed, a flattened second-layer interlayer insulating film is formed on the first metal wiring layer, and an electrical connection is made in the second connection hole through the second-layer interlayer insulating film. A second metal wiring layer to be connected is formed, and a flattened third metal wiring layer is formed on the second metal wiring layer.
An interlayer insulating film of a layer is formed, and a metal wiring layer of a third layer is formed, which is electrically connected through a connection hole through the interlayer insulating film, or an interlayer insulating film and a metal wiring layer are further laminated. In a semiconductor device in which multi-layer wiring is formed, an interlayer insulating film of a third layer or an upper layer is an insulating film having a three-layer structure, and the insulating film of the first layer and the insulating film of the second layer are formed. The film has etching characteristics different from each other with respect to the same etching agent, and both insulating films are formed to have a uniform film thickness irrespective of a place , and the second insulating film and the third insulating film are formed. Means that the etching characteristics with respect to the same etching agent are different from each other, and the surface of the third insulating film is flattened.

A specific example of the three-layer insulating film is as follows.
The insulating films of the first layer and the third layer are silicon oxide films,
The second insulating film may be a silicon nitride film. In a semiconductor device to which the present invention is applied, for example, a connection hole formed in an insulating film having a three-layer structure includes a fine connection hole and a bonding pad portion.

According to the manufacturing method of the present invention, a flattened first-layer interlayer insulating film is formed on a semiconductor substrate on which a semiconductor element is formed, and the first interlayer insulating film is interposed. Forming a first layer metal wiring layer electrically connected through the connection hole, forming a flattened second layer interlayer insulating film thereon, and forming a second layer interlayer insulating film. A second metal wiring layer electrically connected through the second connection hole is formed, and a flattened third interlayer insulating film is formed on the second metal wiring layer to form the interlayer insulating film. A method of manufacturing a semiconductor device, which includes the step of forming a third metal wiring layer electrically connected through a connection hole via the step of forming a third layer metal wiring layer or further laminating an interlayer insulating film and a metal wiring layer to form a multilayer wiring. The third or upper interlayer insulating film is an insulating film having a three-layer structure, and the first insulating film and the second insulating film are Have different etching characteristics with respect to the same etching agent in dry etching, and both insulating films are formed to have a uniform film thickness regardless of location, and the third insulating film is the second insulating film. For the film, dry etching having different etching characteristics with respect to the same etching agent is selected, and the surface of the third-layer insulating film is flattened. The etching conditions are set so that the etch rate of the second insulating film is higher than the etch rate of the second insulating film, and when the second insulating film is etched, the second insulating film is etched. Etching conditions are set so that the etching rate of the insulating film is higher than the etching rate of the first insulating film.

The manufacturing method of the present invention is more effectively applied to the case where the insulating film having a three-layer structure has a surface flatness of 0.3 μm or less during etching. The three-layer insulating film having such surface flatness can be flattened by using, for example, the CMP method for the flattening. Three
A preferred example of the insulating film having a layered structure is that a silicon oxide film is used as the first and third insulating films and a silicon nitride film is used as the second insulating film.

The thickness of the third insulating film varies remarkably depending on the location. When the third-layer insulating film is etched, the second-layer insulating film needs to have a certain thickness because excessive etching is applied to the second-layer insulating film in shallow holes. When a silicon nitride film is used as the second-layer insulating film, cracks may occur if a thick silicon nitride film is formed on the metal wiring. Therefore, by forming a silicon oxide film as the first insulating film between the second insulating film and the metal wiring, it is possible to prevent the occurrence of cracks.

[0019]

EXAMPLE Next, one example will be described with reference to FIG. (A) The base 200 is, for example, a semiconductor element formed on a silicon substrate. A first interlayer insulating film 201 is formed on the base 200. The interlayer insulating film 201 is TEOS
CVD using (Tetraethylorthosilicate) and O ₃ as raw materials
Formed by BPSG (Borophosphosilicate gl)
ass) film and an upper NSG (SiO ₂ ) film having a thickness of 800 nm which is flattened by heat treatment reflow.
Is a first-layer interlayer insulating film. The inter-layer insulation film 201 is formed by dry etching with a first hole diameter of 0.35 μm.
The fine connection hole 202 is opened.

An aluminum-based metal layer is formed on the interlayer insulating film 201, and a first metal wiring layer is formed by laminating a TiN film on the surface of the aluminum metal layer. The first metal wiring layer is formed by photolithography and etching. Form 203. The width of the wiring portion of the metal wiring 203 is 0.4 μm, and the bonding pad portion 210 is patterned into a size of 100 μm square.

A 2.0 μm thick NSG film is deposited on the metal wiring 203 by a plasma CVD method using TEOS as a raw material, and a 0.7 μm thick film is polished by a CMP method to a thickness of 1.
A second interlayer insulating film 204 of 3 μm is formed. As a result of measuring the surface flatness at this time, it was 0.3 μm.

A resist pattern is formed on the interlayer insulating film 204 by photolithography, and C is used as a mask.
The second fine connection hole 20 having a diameter of 0.4 μm is formed by etching by magnetron RIE using F type gas.
5 and an opening 210 of a bonding pad portion of 80 μm square
And are formed at the same time.

(B) A second metal wiring layer 206 is formed and patterned by photolithography and etching. The metal wiring layer 206 is the first metal wiring layer 203.
Is a wiring layer connected to, and the width of the wiring part is 0.4μ.
m in the bonding pad 210
It is patterned into 00 μm square. The metal wiring layer 206 is Al
It is a metal wiring of a system and has a TiN film laminated on the surface. In the bonding pad portion 210, the first metal wiring layer 203 and the second metal wiring layer 206 are
They are in contact with each other on the entire μm square, and the contact resistance is small.

An interlayer insulating film having a three-layer structure is formed as a third interlayer insulating film 207 on the metal wiring layer 206. The first layer film 207a of the interlayer insulating film 207 has a thickness of 300 n formed by the plasma CVD method using TEOS as a raw material.
m NSG film. Since this NSG film 207a has excellent step coverage characteristics in the connection hole of the pad portion 210, the thickness of the NSG film 207a is 0.4 μm on the second metal wiring layer 206 and on the bottom of the pad portion 210. Layer 206
Equal to above.

A thickness of 100 nm was formed on the NSG film 207a by a plasma CVD method using SiH ₄ and NH ₃ gas as raw materials.
Of silicon nitride film 207b is deposited. Like the NSG film, the silicon nitride film 207b also has excellent step coverage characteristics in the connection hole of the pad portion 210. Therefore, the thickness of the silicon nitride film 207b is 0.4 μm on the second metal wiring layer 206 and the pad portion. 210 is equal to the bottom metal wiring layer 206.

Further, on the silicon nitride film 207b,
The thickness is 1.6 μm by the same method as the NSG film 207a.
Of NSG film 207a is deposited. After the interlayer insulating film 207 having a three-layer structure is formed in this way, NMP is performed by CMP.
Only the SG film 207c is polished by 0.5 μm. The surface property of the interlayer insulating film 207 thus formed is 0.3 μm.
It was within.

(C) In this state, ordinary photolithography is performed to form a resist pattern 208 having an opening with a hole diameter of 0.4 μm and a large-sized opening for the pad portion on the bonding pad portion 210. The NSG film 20 is formed by etching the three-layered interlayer insulating film 207 using the resist pattern 208 as a mask.
7a and 207c and the silicon nitride film 207b have different etching characteristics with respect to an etching agent for dry etching. Therefore, in the etching of the interlayer insulating film 207, the etching conditions are set so that the silicon nitride film 207b has a smaller etching rate than the NSG film 207c when the uppermost NSG film 207c is etched. When the silicon film 207b is etched, the NSG film 207a therebelow is the silicon nitride film 2
The etching conditions are set so that the etching rate becomes smaller than 07b.

In etching the interlayer insulating film 207, first the NSG is used with the resist pattern 208 as a mask.
The film 207c is etched. At this time, the inter-layer insulating film of the bonding pad part 210 is formed into the third fine connection hole 209.
Since the film thickness is thicker than that of the portion, the etching time is set according to the interlayer film thickness of the bonding pad portion 210. The etching conditions are set so that the silicon nitride film 207b has an etching rate smaller than that of the NSG film 207c. Therefore, the etching rate is slower in both the fine connection hole 209 portion and the bonding pad portion 210 portion. It uniformly stops on the silicon film 207b. In this way, the second connection hole 209 and part of the bonding pad portion 210 are formed.

(D) Next, the silicon nitride film 207b is etched under etching conditions that increase the etching rate of the silicon nitride film and decrease the etching rate of the silicon oxide film. At this time, the etching is uniformly stopped on the silicon oxide film 207a having a slow etching rate in both the fine connection hole 209 portion and the bonding pad portion 210 portion.

(E) Further, the etching conditions are changed again to increase the etching rate of the silicon oxide film, and the silicon oxide film 207a is etched up to the second metal wiring layer 206. At this time, the silicon oxide film 207a is formed on the bonding pad portion 210 even at the fine connection hole 209.
Since the same is applied to the portions, the same over-etching is appropriately performed regardless of the location, and the conventional over-etching inside the fine connection hole does not cause damage to the underlying metal layer. In this way, the openings of the fine connection holes 209 and the bonding pad portion 210 are completed.

Thereafter, an aluminum-based metal wiring layer and a third metal wiring layer in which a TiN film is laminated on the surface of the aluminum-based metal wiring layer are formed, patterned by photolithography and etching, and then formed by the third fine connection holes 209. A wiring pattern having a width of 0.4 μm connected to the metal wiring 205 of the second layer and a metal wiring layer 211 of the bonding pad pattern of the third layer patterned in 100 μm square by the bonding pad portion 210 are formed. To do. At this time, in the bonding pad section 210, the second-layer metal wiring layer 206 and the third-layer metal wiring layer 211 are in contact with each other over the entire surface of 80 μm square,
Contact resistance is low.

In this way, the semiconductor device is completed. FIG. 2E also shows a cross-sectional view of the semiconductor device of one embodiment. Next, Table 1 shows a comparison of various characteristics in the connection holes between the semiconductor device manufactured by the method of the embodiment and the semiconductor device formed by the conventional interlayer film structure shown in FIG.

[0033]

[Table 1]

The characteristics compared are the actual finished diameter, shape, and contact resistance of the contact hole with respect to the mask size of the fine contact hole. The actual finished diameter of the connection hole with respect to the mask size is 0.60 μm in the past, but 0.45 μm in the present invention.
It was m. The reason why the conventional method is larger is that in the conventional method, excessive over-etching is added to the fine connection hole to increase the size. Further, in the shape, in the conventional method, the deposit is present in the opening and the shape is transformed into a crown shape, whereas in the present invention, the shape is smooth. This is also considered to be because the TiN on the underlying metal wiring is etched due to excessive overetching in the related art, and the reaction product with Al under the TiN is sputtered and adhered to the sidewall of the connection hole. The hole contact resistance is also higher than before. The reason for this is overetching. In the embodiment, the present invention is applied to the third-layer interlayer insulating film of the three-layer wiring structure, but it can be similarly applied to the third-layer or more interlayer insulating film in the multilayer wiring structure of three or more layers.

[0035]

According to the present invention, the third or upper interlayer insulating film is a three-layer insulating film, and the first insulating film and the second insulating film are dry-etched. Etching characteristics for the same etching agent of are different from each other, and both insulating films are formed to have a uniform film thickness regardless of location,
As the third-layer insulating film, one having a different etching characteristic with respect to the same etching agent in dry etching as that of the second-layer insulating film is selected, and the surface of the third-layer insulating film is flattened. When etching the insulating film of the second layer, the etching conditions are set so that the etching rate of the insulating film of the third layer is higher than the etching rate of the insulating film of the second layer. During the etching of the insulating film, the etching conditions are set so that the etching rate of the second insulating film is higher than the etching rate of the first insulating film. When the insulating film of the second layer is etched, the etch rate of the insulating film of the second layer is lower, and the etching stops at the insulating film of the second layer. At this time, since the interlayer film thickness under the contact hole (the total film thickness of the first and second insulating films) becomes equal regardless of the location, the underlying metal wiring is not etched in the subsequent etching of the contact hole. The difference in damage is reduced. Even if the interlayer insulating film that forms the connection hole includes the fine connection hole and the bonding pad portion, the etching condition can be matched to the bonding pad portion, so that the bonding pad portion with a large area can provide a wide wiring between the upper layer and the lower layer. Areas can be connected, the contact resistance is reduced, and the operation of the semiconductor chip can be stabilized. When the flatness of the surface of the interlayer insulating film forming the connection hole is 0.3 μm or less, the margin of photolithography is improved and the variation in the hole diameter of the connection hole is reduced. Further, the variation of the hall resistance is also reduced, the variation between the modules is reduced when the circuit is operated, and the stable circuit operation can be guaranteed. By using the CMP technique for flattening the interlayer insulating film for flattening the surface, a semiconductor device can be easily formed with good reproducibility, and thus mass productivity is excellent. If the first and third insulating films of the three-layer structure insulating film are silicon oxide films and the second insulating film is a silicon nitride film, the etching selectivity of each insulating film can be controlled. It is easy, good selectivity can be obtained, and the margin of the connection hole forming process is widened.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a step of forming a fine connection hole and a bonding pad portion.

FIG. 2 is a process sectional view showing an embodiment of the method of the present invention.

[Explanation of symbols]

200 Base substrate 201 First layer interlayer insulating film 202 First fine connection hole 203 First metal wiring layer 204 Second layer interlayer insulating film 205 Second fine connection hole 206 Second metal wiring layer 207 Third interlayer insulating film 207a, 207c Silicon oxide film 207b Silicon nitride film 209 Third fine connection hole 210 Bonding pad section 211 Third metal wiring layer

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kaichi Ueno 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Co., Ltd. (72) Takahiko Kuroda 1-3-6 Nakamagome, Ota-ku, Tokyo (56) Reference JP-A-8-204012 (JP, A) JP-A-2-239625 (JP, A) JP-A-6-334047 (JP, A) JP-A-7-130737 (JP, A) JP 63-257229 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3205 H01L 21/3123 H01L 21/768 H01L 21/28-21 / 288 H01L 29/40-29/51

Claims (7)

(57) [Claims] 1. A flattened first-layer interlayer insulating film is formed on a semiconductor substrate on which a semiconductor element is formed, and an electrical connection is made in a first connection hole through the first-layer interlayer insulating film. A first metal wiring layer to be electrically connected is formed, a flattened second interlayer insulating film is formed on the first metal wiring layer, and the second interlayer insulating film is formed through the second interlayer insulating film. A second metal wiring layer electrically connected through the connection hole is formed, and a flattened third-layer interlayer insulating film is formed on the second metal wiring layer. In a semiconductor device in which a third metal wiring layer to be electrically connected is formed, or a multilayer wiring is formed by further laminating an interlayer insulating film and a metal wiring layer, the third or upper layer is formed. The interlayer insulating film is an insulating film having a three-layer structure, and the first insulating film and the second insulating film are the same. Are those etching characteristics different from each other with respect to the etching agent, and both the insulating film is formed in a uniform thickness regardless of location, and the second insulating film and the third layer insulating film the same etching A semiconductor device in which the etching characteristics with respect to the agent are different from each other, and the surface of the third insulating film is flattened. 2. A first layer and a third layer of the three-layer insulating film.
The semiconductor device according to claim 1, wherein the second insulating film is a silicon oxide film, and the second insulating film is a silicon nitride film. 3. The semiconductor device according to claim 1, wherein the connection hole formed in the insulating film having the three-layer structure includes a fine connection hole and a bonding pad portion. 4. A first planarized interlayer insulating film is formed on a semiconductor substrate having a semiconductor element formed thereon, and the first interlayer insulating film is formed.
A first-layer metal wiring layer electrically connected to the first connection hole via the first-layer interlayer insulating film is formed, and a flattened second-layer interlayer insulating film is formed thereon. A second electrically connected via the second connection hole through the second-layer interlayer insulating film.
A metal wiring layer of the third layer is formed, and a flattened third layer interlayer insulating film is further formed thereon, and the third layer is electrically connected through a connection hole through the interlayer insulating film. In a method of manufacturing a semiconductor device, which includes a step of forming a metal wiring layer or further laminating an interlayer insulating film and a metal wiring layer to form a multilayer wiring, a third layer or an upper interlayer insulating film is a three-layered insulating film. The first insulating film and the second insulating film have different etching characteristics with respect to the same etching agent in dry etching, and both insulating films are uniform regardless of location. The third-layer insulating film is formed to have a different film thickness, and the second-layer insulating film has different etching characteristics with respect to the same dry etching agent, and the surface of the third-layer insulating film is selected. Is flattened and the third insulating film is etched At the time of etching, the etching conditions are set so that the etching rate of the third-layer insulating film is higher than that of the second-layer insulating film. In the method of manufacturing a semiconductor device, the etching conditions are set so that the etching rate of the second insulating film is higher than the etching rate of the first insulating film. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the insulating film having the three-layer structure has a surface flatness of 0.3 μm or less during etching. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the insulating film having the three-layer structure uses a CMP method for planarizing the insulating film. 7. A first layer and a third layer of the insulating film having a three-layer structure.
The method for manufacturing a semiconductor device according to claim 4, wherein a silicon oxide film is used as the second insulating film, and a silicon nitride film is used as the second insulating film.