JP3482020B2 - Sense amplifier circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier circuit of a semiconductor memory device.

[0002]

2. Description of the Related Art Recently, as a demand for a semiconductor memory device, there has been an increasing demand for faster operation and lower power consumption. By the way, the sense amplifier circuit section that amplifies a small potential difference between two bit lines and reads data at high speed is a part that consumes power, and is an indispensable circuit section for realizing low power consumption.

A conventional sense amplifier circuit will be briefly described below with reference to the drawings. FIG. 11 is a circuit diagram of a conventional sense amplifier circuit, and FIG. 12 is an operation timing chart of the conventional sense amplifier circuit.

In FIG. 11, reference numeral 901 denotes a sense amplifier, and 9
02 is a bit line precharge circuit, 903 is a sense amplifier control circuit, Qp901, Qp902 and Qp911 are P channel type MOS transistors, and Qn901 to Qn9.
04 and Qn911 to Qn913 are N-channel type MOS
Transistor, VDD is power supply voltage, VSS is ground voltage,
INV91 is a negation circuit, SAE91, SAC91 and B
P is a control signal, BL0 and / BL0 are bit lines, SA
P, SAN and N901 are node names.

First, the circuit configuration will be described. The sense amplifier 901 is a differential sense amplifier and amplifies the potential difference between the two bit lines BL0 and / BL0. In the circuit configuration of the sense amplifier, the bit line BL0 is connected to the drain of the P-channel MOS transistor Qp901, the gate of the P-channel MOS transistor Qp902, the drain of the N-channel MOS transistor Qn901 and the gate of the N-channel MOS transistor Qn902. The bit line / BL0 is connected to the drain of the P-channel MOS transistor Qp902, the gate of the P-channel MOS transistor Qp901, the drain of the N-channel MOS transistor Qn902 and the gate of the N-channel MOS transistor Qn901, and the power supply voltage side of the sense amplifier. Is connected to the source of the P-channel type MOS transistor Qp901 and the source of the P-channel type MOS transistor Qp902, and is connected to the sense amplifier. The source and the N-channel type MOS transistor of the SAN which is a drive signal node of the ground voltage side of the flop is N-channel type MOS transistor Qn901 Qn902
Connected to the source.

The bit line precharge circuit 902 precharges the two bit lines BL0 and / BL0 to the ground voltage VSS. The control signal BP is connected to the gates of the N-channel MOS transistors Qn903 and Qn904, and the N-channel MOS transistor Qn9 is connected.
03 and Qn904 are connected to the ground voltage VSS, the drain of the N-channel MOS transistor Qn903 is connected to the bit line BL0, and the N-channel MON
The drain of the S transistor Qn904 is the bit line / BL
It is connected to 0. When the control signal BP has a logic voltage "H", the bit lines BL0 and / BL0 are precharged to the ground voltage, and when the control signal BP has a logic voltage "L", the bit lines BL0 and / BL0 are in a floating state.

The sense amplifier control circuit 903 controls the sense amplifier 901. The control signal SAE91 is connected to the gate of the N-channel MOS transistor Qn911 and the input of the NOT circuit INV91,
C91 is connected to the gates of N-channel MOS transistors Qn912 and Qn913, and the node SAN is N
Channel type MOS transistors Qn911 and Qn91
2, the node N901 is connected to the output of the NOT circuit INV91 and the gate of the P-channel MOS transistor Qp911, and the node SAP is connected to the drain of the P-channel MOS transistor Qp911 and N.
It is connected to the drain of the channel type MOS transistor Qn913, the power supply voltage VDD is connected to the source of the P channel type MOS transistor Qp911, and the ground voltage VSS.
Are N-channel MOS transistors Qn911 and Qn9
12 and Qn913 connected to each source.

Next, the operation will be described. FIG. 12 is a timing chart thereof. In the initial state, the control signal SAE91 is the logical voltage "L", the control signal SAC91 is the logical voltage "H", and the control signal BP is the logical voltage "H". At this time, the node SAP has the logical voltage “L”, the node SAN has the logical voltage “L”, and the bit lines BL0 and / BL0.
Are precharged to the logic voltage "L".

Next, the control signal SAC91 is set to the logical voltage "L" and the control signal BP is set to the logical voltage "L". At this time, the node SAP, the node SAN, and the bit lines BL0 and / BL0 are all in a floating state. At this time, for example, data is read to the bit lines BL0 and / BL0 connected to the memory cell. The control signal SAE91 is set to the logic voltage "H" in order to amplify the data read to the bit line by the sense amplifier. At this time, the node SAP becomes the logic voltage "H" and the node SAN becomes the logic voltage "L". Since the node SAP has the logic voltage “H” and the node SAN has the logic voltage “L”, the bit line B
The data of L0 and / BL0 are amplified and become the potential levels of the power supply voltage VDD and the ground voltage VSS, respectively.

After the data is amplified and read in this way, the control signal SAE91 is set to the logic voltage "L" in order to restore the initial state. At this time, the node SAP, the node SAN, and the bit lines BL0 and / BL0 are all in a floating state. After that, the control signal SAC91 is set to the logic voltage "H", and the control signal BP is set to the logic voltage "H". At this time, the node SAP is at the logical voltage "L", the node SAN is at the logical voltage "L", and the bit lines BL0 and / BL0.
Is precharged to the logic voltage "L" and returns to the initial state. Through the above operation, the read operation of the differential sense amplifier is performed.

[0011]

In such a conventional sense amplifier circuit, the power supply node S of the differential type sense amplifier is used.
Since the logic voltage is “L” when the AP is not operating and the logic voltage is “H” when the AP is operating, there is a problem that the electric charges consumed in the node SAP are wasted and the power consumption increases.

Further, if the sense amplifier operates at the same time when the data is read out to the bit line, there is a problem that malfunction may occur and the sense amplifier may operate at high speed.

In view of the above point, the present invention has a first object to further reduce power consumption, and prevents malfunction even if a sense amplifier operates at the same time when data is read to a bit line. The second purpose is to do so, and the third purpose is to further speed up the operation of the sense amplifier.

[0014]

In order to achieve the above-mentioned object, the present invention provides a node SA P when the sense amplifier is not operating.
The set to a potential different from the potential of the initial state of the bit line, eliminating the waste of electric charge is charged and discharged to the node SAP, is that reducing power consumption of the sense amplifier circuit.

Specifically, the means for solving the problems according to the first aspect of the present invention is to provide a sense amplifier circuit with first and second bit lines, first and second P-channel MOS transistors, and first and second. A sense amplifier circuit configured by an N-channel MOS transistor, wherein the first bit line includes a drain of the first P-channel MOS transistor, a drain of the first N-channel MOS transistor, and a drain of the first N-channel MOS transistor. And the second N-channel MOS transistor is connected to the gate of the second P-channel MOS transistor, and the second bit line is connected to the gate of the second N-channel MOS transistor. Drain, drain of the second N-channel MOS transistor, gate of the first P-channel MOS transistor and front The first N-channel MOS transistor of the gate - are respectively connected to the preparative, the first N
The source of the channel type MOS transistor and the second N
The source of the channel-type MOS transistor is connected, the source of the first P-channel type MOS transistor is connected to the source of the second P-channel type MOS transistor, and the sense amplifier circuit does not operate. State, the first and second P-channel MOS transistors are
The source voltage of the transistor is the first and second bits.
The first and second P-channel MOS transistors are connected to the line voltage.
Than the voltage higher by the absolute value of the threshold voltage of the transistor
It is configured to have a low voltage.

The invention of claim 2 is in the structure of claim 1.
When the sense amplifier circuit is inactive,
First and second P-channel MOS transistor saws
Scan nodes, Ru der which the structure is floating.

[0017]

According to the present invention, when the sense amplifier is not operating, the voltage of the bit line and the first and second P of the sense amplifier are set.
Difference voltage from the source voltage of channel type MOS transistor
Is always the threshold of P-channel MOS transistor
Since less than the voltage, which that no waste of electric charge is charged and discharged to the node SAP.

According to the second aspect , when the sense amplifier is in the inoperative state, the source nodes of the first and second P-channel type MOS transistors are in the floating state.
It

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the sense amplifier circuit of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of the sense amplifier circuit of the first embodiment, and FIG. 2 is an operation timing chart of the sense amplifier circuit of the first embodiment.

(First Embodiment) In FIG. 1, 101 is a sense amplifier, 102 is a bit line precharge circuit, 103 is a sense amplifier control circuit,
Qp101 is a first P-channel MOS transistor,
Qp102 is a second P-channel MOS transistor,
Qp111 is a P-channel MOS transistor, Qn1
01 is the first N-channel MOS transistor, Qn1
02 is a second N-channel MOS transistor, Qn1
03, Qn104 and Qn111 to Qn113 are N-channel MOS transistors, VDD is a power supply voltage, VSS
Is ground voltage, INV11 is negative circuit, SAE11, SA
C11 and BP are control signals, BL0 is the first bit line,
/ BL0 is the second bit line, SAP, SAN and N10
Reference numeral 1 is a node name, and VSAP and VSAN are constant voltage nodes.

First, the circuit configuration will be described. The sense amplifier 101 is a differential type sense amplifier, which amplifies a potential difference between two bit lines BL0 (first bit line) and / BL0 (second bit line), and has the same configuration as the conventional example. Since it exists, the description is omitted. The bit line precharge circuit 102 has the same configuration as that of the conventional example, and therefore its explanation is omitted.

In the circuit configuration of the sense amplifier control circuit 103, the control signal SAE11 is input to the gate of the N channel type MOS transistor Qn111 and the NOT circuit INV11, and the node SAN is the first N channel type MOS transistor Qn101 of the sense amplifier circuit section. Source of the second
Connected to the source of the N-channel MOS transistor Qn102, the drain of the N-channel MOS transistor Qn111 and the drain of the N-channel MOS transistor Qn112, and the control signal SAC11 is supplied to the gate of the N-channel MOS transistor Qn112 and the N-channel MOS transistor Qn113. The node N101 is connected to the gate of
The node SAP is connected to the gate of the channel-type MOS transistor Qp111, and the node SAP is the first P of the sense amplifier 101.
The power supply voltage VDD is connected to the source of the channel-type MOS transistor Qp101, the source of the second P-channel-type MOS transistor Qp102, the drain of the P-channel-type MOS transistor Qp111, and the drain of the N-channel-type MOS transistor Qn112.
The ground voltage VSS is connected to the source of the OS transistor Qp111, and the N-channel MOS transistor Qn11
1, the constant voltage node VSAP is connected to the source of the N-channel type MOS transistor Qn112, and the constant voltage node VSAN is connected to the source of the N-channel type MOS transistor Qn113.

Next, the operation will be described with reference to FIG. The constant voltage node VSAP changes from the potential level of the ground voltage VSS to the threshold value of the P-channel MOS transistor.
Less than potential higher by voltage (Vtp (absolute value | Vtp |) )
It has set the level of the constant voltage node VSAN is set at the threshold voltage (Vtn) potential higher levels of N-channel MOS transistor from the potential level of the ground voltage VSS.

In the initial state, the control signal SAE11 is the logical voltage "L", the control signal SAC11 is the logical voltage "H", and the control signal BP is the logical voltage "H". At this time, the node SAP is a potential of a constant voltage node VSAP ( a level lower than a potential higher than the potential level of the ground voltage VSS by the threshold voltage (Vtp) of the P-channel MOS transistor), and the node SAN is a constant voltage node VSAN. The potential is (potential level higher than the potential level of the ground voltage VSS by the threshold voltage (Vtn) of the N-channel MOS transistor), and the first bit line BL0 and the second bit line / BL0 are at the logical voltage "L". It is precharged to ".

Next, the control signal SAC11 is set to the logical voltage "L" and the control signal BP is set to the logical voltage "L". At this time, the node SAP, the node SAN, and the first bit line BL
0 and the second bit line / BL0 are all in a floating state.

Next, for example, the first connected to the memory cell
Data is read to the bit line BL0 and the second bit line / BL0. The data read to the first bit line BL0 and the second bit line / BL0 is applied to the sense amplifier 1
In order to amplify by 01, the control signal SAE11 is set to the logic voltage "H". At this time, the node SAP becomes the logic voltage "H" and the node SAN becomes the logic voltage "L". Since the node SAP becomes the logical voltage “H” and the node SAN becomes the logical voltage “L”, the data of the first bit line BL0 and the second bit line / BL0 is amplified, and the power supply voltage VDD and the ground voltage VSS are respectively supplied. Potential level.

After the data is amplified in this way, the control signal SAE11 is set to the logic voltage "L" in order to restore the initial state.
And At this time, the node SAP, the node SAN, the first
The bit line BL0 and the second bit line / BL0 are all in the floating state. After that, the control signal SAC11
Is a logical voltage "H", and the control signal BP is a logical voltage "H". At this time, the node SAP is at the potential of the constant voltage node VSAP, the node SAN is at the potential of the constant voltage node VSAN, and the first bit line BL0 and the second bit line / BL0.
Is precharged to the logic voltage "L" and returns to the initial state.
Through the above operation, the read operation of the differential sense amplifier is performed.

In the sense amplifier circuit of the first embodiment, when the sense amplifier 101 is not operating, the potential of the node SAP is
Potential of the input lines BL0 and / BL0 in the initial state, that is,
The P-channel MOS transistor is connected to the ground voltage VSS.
The threshold voltage (Vt of the transistors Qp101 and Qp102)
p (absolute value | Vtp |)) is lower than the potential higher than
The feature is that the bell is set . Node SAP
From the potential level of the ground voltage VSS to the P-channel MOS
Transistor threshold voltage (Vtp (absolute value | Vtp
|) ) Is set to a level lower than the higher potential, because the node SAP during the operation of the sense amplifier is set to the power supply voltage VD.
This is because the electric charge of the node SAP is not wastefully charged and discharged in order to perform the low power consumption operation. The same applies to the node SAN.

Next, as another case of setting the potential of the node SAN in the first embodiment, the N-channel MOS transistors Qn101 and Qn are connected to the constant voltage node VSAN from the read voltage of the data to the bit lines BL0 and / BL0 .
there is a method of setting only the potential level lower n102 of the threshold voltage (Vtn). The reason is that bit line BL0 and
This is to prevent both the first N-channel type MOS transistor Qn101 and the second N-channel type MOS transistor Qn102 from being turned on when data is read to / BL0 . Bit line BL0 and /
This is because if the sense amplifier operates at the same time when the data is read to BL0 , it may malfunction.

(First Configuration Example) Next, a first configuration example of the sense amplifier circuit according to the present invention will be described with reference to the drawings. FIG. 3 relates to the present invention .
Circuit diagram of a sense amplifier circuit of the first configuration example, FIG. 4 is present to
3 is an operation timing chart of the sense amplifier circuit of the first configuration example related to the invention .

In FIG. 3, 201 is a sense amplifier, 2
02 is a bit line precharge circuit, 203 is a sense amplifier control circuit, Qp201 is a first P-channel MOS transistor, Qp202 is a second P-channel MOS transistor, Qp211 and Qp212 are P-channel MOS transistors, and Qn201 is a first P-channel MOS transistor. No. 1 P-channel MOS transistor, Qn202 is a second P-channel MOS transistor, Qn203 to Qn212 are N-channel MOS transistors, VDD is a power supply voltage, VSS
Is ground voltage, INV21 is negative circuit, SAE21 and B
P is a control signal, BL0 is a first bit line, / BL0 is a second bit line, and SAP, SAN and N201 are node names.

First, the circuit configuration will be described. The sense amplifier 201 is a differential type sense amplifier, which amplifies a potential difference between two bit lines BL0 (first bit line) and / BL0 (second bit line), and has the same configuration as the conventional example. Since it exists, the description is omitted. The bit line precharge circuit 202 has the same configuration as that of the conventional example, and therefore its explanation is omitted.

In the circuit configuration of the sense amplifier control circuit 203, the control signal SAE21 is input to the gate of the N-channel type MOS transistor Qn212, the input of the NOT circuit INV21 and the gate of the P-channel type MOS transistor Qp212, and the node SAN is the N-channel type. The node S is connected to the drain of the MOS transistor Qn212 and the drain of the P-channel type MOS transistor Qp212.
AP is the drain of the P-channel MOS transistor Qp211 and the N-channel MOS transistor Qn211.
Of the P-channel type MOS transistor Qp211 and the source of the P-channel type MOS transistor Qp212.
The ground voltage VSS is an N-channel type MOS transistor Qn
211 source and N-channel MOS transistor Q
It is connected to the source of n211.

Next, the operation will be described with reference to FIG. In the initial state, the control signal SAE21 is at the logical voltage "L" and the control signal BP is at the logical voltage "H". At this time, the node SAP is precharged to the logic voltage "L", the node SAN is precharged to the logic voltage "H", and the first bit line BL0 and the second bit line / BL0 are precharged to the logic voltage "L".

Next, the control signal BP is set to the logic voltage "L". At this time, the first bit line BL0 and the second bit line / BL0 are in a floating state. Next, for example, the first bit line BL0 and the second bit line BL0 connected to the memory cell
Data is read to the bit line / BL0.

Next, in order to amplify the data read to the bit line by the sense amplifier 201, the control signal SAE2
1 is a logical voltage "H". At this time, the node SAP becomes the logic voltage "H" and the node SAN becomes the logic voltage "L". Since the node SAP has the logic voltage “H” and the node SAN has the logic voltage “L”, the first bit line BL0
The data on the second bit line / BL0 is amplified and becomes the potential levels of the power supply voltage VDD and the ground voltage VSS, respectively.

After the data is amplified in this way, the control signal SAE21 is set to the logic voltage "L" in order to return to the initial state.
And At this time, the node SAP is at the logic voltage "L", the node SAN is at the logic voltage "H", and the first bit line BL0 and the second bit line / BL0 are all in the floating state. After that, the control signal BP is set to the logic voltage “H”.
At this time, the first bit line BL0 and the second bit line /
BL0 is precharged to the logic voltage "L" and returns to the initial state. Through the above operation, the read operation of the differential sense amplifier is performed.

In the sense amplifier circuit of the first configuration example according to the present invention , when the sense amplifier is not operating, the node SAP is set to the logic voltage "L" and the node SAN is set to the logic voltage "H", so that the data is read to the bit line. When it is output, the sense amplifier 201 does not operate at all, thus preventing malfunction.

[0039] will be described with reference to the drawings a second embodiment of a sense amplifier circuit (second embodiment) the present invention. Figure 5 is a circuit diagram of a sense amplifier circuit of the second embodiment, FIG. 6 is a timing chart showing the operation of the sense amplifier circuit of the second embodiment.

In FIG. 5, 301 is a sense amplifier, 3
02 is a bit line precharge circuit, 303 is a sense amplifier control circuit, Qp301 is a first P-channel MOS transistor, Qp302 is a second P-channel MOS transistor, Qp311 is a P-channel MOS transistor, and Qn301 is a first P-channel MOS transistor. N-channel type MOS transistor, Qn302 is second N-channel type MOS transistor, Qn303, Qn304 and Qn311 are N-channel type MOS transistor, VDD is power supply voltage, VSS
Is ground voltage, INV31 is negative circuit, SAE31 and B
P is a control signal, BL0 is a first bit line, / BL0 is a second bit line, and SAP, SAN and N301 are node names.

First, the circuit configuration will be described. The sense amplifier 301 is a differential sense amplifier, which amplifies the potential difference between the two bit lines BL0 (first bit line) and / BL0 (second bit line), and has the same configuration as the conventional example. Since it exists, the description is omitted. The bit line precharge circuit 302 also has the same configuration as that of the conventional example, and therefore its explanation is omitted.

In the circuit configuration of the sense amplifier control circuit 303, the control signal SAE31 is connected to the gate of the N-channel type MOS transistor Qn311 and the input of the NOT circuit INV31, and the node SAN is connected to the drain of the N-channel type MOS transistor Qn311. Node N30
1 is the output of the NOT circuit INV31 and the P-channel type MOS
It is connected to the gate of the transistor Qp311, and the node S
AP is connected to the drain of the P-channel MOS transistor Qp311, and the power supply voltage VDD is P-channel MO.
The ground voltage VSS is connected to the source of the S-transistor Qp311, and the ground voltage VSS is N-channel MOS transistor Qn311.
Connected to the source.

Next, the operation will be described with reference to FIG. In the initial state, the control signal SAE31 is at the logical voltage "L" and the control signal BP is at the logical voltage "H". At this time, the nodes SAP and SAN are in a floating state, and the first bit line BL0 and the second bit line /
BL0 is precharged to the logic voltage "L".

Next, the control signal BP is set to the logic voltage "L". At this time, the first bit line BL0 and the second bit line / BL0 are in a floating state. Next, for example, the first bit line BL0 and the second bit line BL0 connected to the memory cell
Data is read to the bit line / BL0. In order to amplify the data read to the first bit line BL0 and the second bit line / BL0 by the sense amplifier, the control signal SAE31 is set to the logical voltage "H". At this time, the node SAP becomes the logic voltage "H" and the node SAN becomes the logic voltage "L". By setting the node SAP to the logic voltage “H” and the node SAN to the logic voltage “L”, the data of the first bit line BL0 and the second bit line / BL0 is amplified, and the power supply voltage VDD and the ground voltage are respectively supplied. The potential level becomes VSS.

After the data is amplified in this way, the control signal SAE31 is set to the logic voltage "L" in order to restore the initial state.
And At this time, the node SAP, the node SAN, the first
The bit line BL0 and the second bit line / BL0 are all in the floating state. After that, the control signal BP is set to the logic voltage “H”. At this time, the first bit line BL0 and the second bit line / BL0 are precharged to the logic voltage "L" and returned to the initial state. Through the above operation, the read operation of the differential sense amplifier is performed.

In the sense amplifier circuit of the second embodiment, the node SAP and the node S are operated when the sense amplifier 301 is not operating.
AN is brought into a floating state, and especially at the node SAP, a voltage lower than a potential higher than the potential level of the ground voltage VSS by the threshold voltage (Vtp (absolute value | Vtp |) ) of the ground voltage VSS after the previous read operation. As compared with the case where the node SAP is set to the ground voltage VSS, it is possible to perform low power consumption operation without wasting and discharging the electric charge of the node SAP. The circuit configuration of the sense amplifier control circuit 303 can be realized with a very simple circuit configuration.

(Second Configuration Example) Next, a second configuration example of the sense amplifier circuit according to the present invention will be described with reference to the drawings. FIG. 7 relates to the present invention .
Circuit diagram of a sense amplifier circuit of the second configuration example, FIG. 8 is present to
7 is an operation timing chart of the sense amplifier circuit of the second configuration example related to the invention .

In FIG. 7, 401 and 411 are sense amplifiers, Qp401 and Qp411 are first P-channel MOS transistors, Qp402 and Qp412 are second P-channel MOS transistors, Qp403 and Qp413 are P-channel MOS transistors, Qn4
01 and Qn411 are first N-channel MOS transistors, Qn402 and Qn412 are second N-channel MOS transistors, Qn403 and Qn413 are third N-channel MOS transistors, and Qn404 and Qn414 are fourth N-channel MOS transistors. Transistor,
Qn405, Qn406, Qn415 and Qn416 are N-channel MOS transistors, VDD is a power supply voltage,
VSS is the ground voltage, INV40 to INV42 are negative circuits, SAE41, SAE42, CG0 and CG1 are control signals, BL0 is the first bit line, / BL0 is the second bit line, DL is the first data line, / DL Is the second data line, SAP40, SAP41, SAN40, SAN41
And N400 to N402 are node names.

First, the circuit configuration will be described. Since the sense amplifiers 401 and 411 have exactly the same configuration as the conventional example, the description thereof will be omitted. The configuration of the sense amplifier control circuit will be described. Sense amplifier 401 and sense amplifier 4
Since the control circuit configuration of 11 is the same, the sense amplifier 40
The control circuit configuration of No. 1 will be described. Sense amplifier 40
The node SAP40 of 1 is connected to the power supply voltage VDD through the P-channel type MOS transistor Qp403, and the node SAP40 is connected to the P-channel type MOS transistor Qp4.
03 and the output of the NOT circuit INV42, and the control signal SAE42 is connected to the input of the NOT circuit INV42. A third N-channel MOS transistor Q is connected in parallel between the node SAN40 and the ground voltage VSS.
n403 and fourth N-channel MOS transistor Q
n404 is connected. Third N-channel MOS
The gate of the transistor Qn403 has a control signal SAE41.
And the node N400 is connected to the fourth N-channel MO
Gate of S-transistor Qn404 and NOT circuit INV4
0, the control signal CG0 is applied to the gate of the N-channel type MOS transistor Qn405, the gate of the N-channel type MOS transistor Qn406 and the NOT circuit I.
The first bit line BL0 is connected to the input of NV40, and the first bit line BL0 is connected to the first data line DL by an N-channel MOS transistor Q.
The second bit line / BL0 is connected to the second data line / DL via the N-channel MOS transistor Qn406.

Next, the operation will be described with reference to FIG. In FIG. 8, a period P41 is a data reading period to the bit line, a period P42 is a data reading period to the data line, a period P43 is a data writing period to the bit line,
A period P44 is a data read period of the bit line data to the data line, which is different from the period 42.

In the initial state, the control signal SAE41 is a logic voltage "L", the control signal SAE42 is a logic voltage "L",
The control signal CG0 is the logical voltage "L", and the control signal CG1 is the logical voltage "L". At this time, the node SAP40, the node SAP41, the node SAN40, and the node SAN4
1 is all in a floating state. In the data read period P41 to the bit line, data is read to the bit line connected to the memory cell, for example.

Next, the control signal SAE41 is set to the logic voltage "H" and the control signal SAE42 is set to the logic voltage "H".
At this time, the node SAP40 and the node SAP41 are at the logic voltage “H”, the node SAN40 and the node SAN41.
Becomes a logical voltage "L", the sense amplifier 401 and the sense amplifier 402 operate, and the potentials of the bit lines are amplified.

Next, a data read period P for the data line
At 42, the first bit line BL0 and the second bit line /
The data of BL0 is transferred to the first data line DL and the second data line, respectively.
The control signal CG0 is set to the logic voltage "H" in order to read the data line / DL.

Next, in the data writing period P43, the control signal SAE41 is set to the logical voltage "L", and the external data is written from the data line to the bit line. Here, by setting the control signal SAE41 to the logical voltage "L", the node SAN40 is brought into a floating state and the sense amplifier 401 is brought into a non-latching state, so that it becomes easy to write data to the bit line. On the other hand, since the node N401 of the sense amplifier 402 is in the complete latch state with the logic voltage "H", the data of the bit lines BL1 and / BL1 is in the complete latch state, and there is no malfunction due to noise or the like.

Next, in the data read period P44 for the data lines of different bit line data, the control signal CG0 is set to the logic voltage "L" and then the control signal CG1 is set to the logic voltage "H". As a result, the bit lines BL1 and / BL
The data of 1 is read to the first data line DL and the second data line / DL, respectively.

In the sense amplifier circuit of the second configuration example according to the present invention, at the time of writing data, only the sense amplifier of the bit line to which the data is written is brought into the non-latching state, and the other sense amplifiers are brought into the completely latched state, thereby performing the writing. It is possible to prevent malfunction of bit lines other than the bit line.

(Third Configuration Example) A third configuration example of the sense amplifier circuit according to the present invention will be described with reference to the drawings. FIG. 9 shows the
3 circuit diagram of a sense amplifier circuit configuration example, FIG. 10 is the present invention
6 is an operation timing chart of the sense amplifier circuit of the third configuration example relating to FIG.

In FIG. 9, 501 is a sense amplifier and Q
p501 is the first P-channel MOS transistor, Q
p502 is a second P-channel MOS transistor, Q
p513 is a third P-channel MOS transistor, Q
n501 is a first N-channel MOS transistor, Q
n502 is a second N-channel MOS transistor, Q
n513 is a third N-channel MOS transistor, Q
n514 is one of the fourth N-channel MOS transistors, Qn515 is one of the fifth N-channel MOS transistors, and Qn517 is the other fourth N-channel MOS transistor.
S transistor, Qn518 is the other fifth N-channel MOS transistor, VDD is power supply voltage, VSS is ground voltage, INV51 is negative circuit, SAE51 and SAE
52 is a control signal, BL0 is a first bit line, / BL0 is a second bit line, SAP, SAN and N500 to N50.
2 is a node name.

First, the circuit configuration will be described. The sense amplifier 501 has the same configuration as that of the conventional example, and therefore its description is omitted. The configuration of the sense amplifier control circuit will be described. A third P-channel MOS transistor Qp513 is connected between the node SAP and the power supply voltage VDD, and an N-channel MO transistor is connected between the node SAP and the node N500.
The S transistor Qn518 is connected to the node N500.
N-channel MOS transistor Qn517 is connected between the power supply voltage VDD and the power supply voltage VDD, and the node N502 is connected to the third P
The control signal SA is connected to the gate of the channel type MOS transistor Qp513 and the output of the NOT circuit INV51.
E52 is connected to the input of the NOT circuit INV51, and the gate of the N-channel MOS transistor Qn517 and the fourth
The first bit line BL0 is connected to the gate of the N-channel type MOS transistor Qn514 of
The second bit line / BL0 is connected to the gate of the S transistor Qn518 and the gate of the fifth N-channel MOS transistor Qn515, and the node SAN and the ground voltage V
A third N-channel MOS transistor Q is connected to SS.
n513 is connected, and the fourth N-channel MOS transistor Qn51 is connected between the node SAN and the node N501.
4 is connected, a fifth N-channel MOS transistor Qn515 is connected between the node N501 and the ground voltage VSS, and a third N-channel MOS transistor Qn is connected.
The gate of 513 is connected to the control signal SAE51.

Next, the operation will be described with reference to FIG. In the initial state, the control signal SAE51 is at the logical voltage "L", the control signal SAE52 is at the logical voltage "L", and the first bit line BL0 and the second bit line / BL0 are at the logical voltage "L". At this time, the node SAP and the node SA
N is in a floating state.

Next, for example, the first memory cell connected to the memory cell
The data is read to the bit line BL0 and the second bit line / BL0. At this time, the fourth N-channel MOS
Transistor Qn514, fifth N-channel MOS transistor Qn515, N-channel MOS transistor Qn517 and N-channel MOS transistor Qn
518 turns on, the node SAP becomes the logic voltage “H”, the node SAN becomes the logic voltage “L”, and the sense amplifier 501
Works. At this time, the first bit line BL0 and the second bit line BL0
When the bit line / BL0 of the above is slightly amplified, the fifth N-channel type MOS transistor Qn515, N-channel type MO
The S transistor Qn518 turns off, and the sense amplifier 50
1 does not work. Therefore, by setting the control signal SAE51 to the logic voltage "H" and the control signal SAE52 to the logic voltage "H", the node SAP becomes the logic voltage "H", the node SAN becomes the logic voltage "L", and the sense amplifier 501
Operates and the first bit line BL0 and the second bit line /
The potential of BL0 is the power supply voltage VDD and the ground voltage V, respectively.
It is amplified to SS.

After the data is amplified in this way, in order to return to the initial state, the control signal SAE51 and the control signal SA
E52 is set to the logical voltage "L", and the first bit line BL0 and the second bit line / BL0 are also set to the logical voltage "L" to be in the initial state. Through the above operation, the read operation of the differential sense amplifier is performed.

In the sense amplifier circuit of the third configuration example relating to the present invention , the first bit line BL0 and the second bit line /
When data is read to BL0, the sense amplifier 501 operates, so that the potential of the bit line can be amplified at high speed.

[0064]

According to the sense amplifier circuit of the first aspect of the present invention, when the sense amplifier is not operating, the node SAP
And the potential difference between the bit line and the initial state of the bit line is always sensed.
First and second P-channel MOS transistor of amplifier
The threshold voltage of the sense amplifier circuit is less than the threshold voltage of the sense amplifier.

According to the sense amplifier circuit of the second aspect of the invention, when the sense amplifier is in a non-operating state, the source nodes of the first and second P-channel type MOS transistors are in a floating state, so that malfunction occurs. the power consumption of the sense amplifier is Ru Hakare without incurring.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a sense amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the sense amplifier circuit according to the first embodiment.

FIG. 3 is a circuit diagram of a sense amplifier circuit according to a first configuration example of the present invention.

FIG. 4 is an operation timing chart of the sense amplifier circuit according to the first configuration example of the present invention .

FIG. 5 is a circuit diagram of a sense amplifier circuit according to a second embodiment of the present invention.

FIG. 6 is an operation timing chart of the sense amplifier circuit according to the second embodiment.

FIG. 7 is a circuit diagram of a sense amplifier circuit of a second configuration example according to the present invention.

FIG. 8 is an operation timing chart of the sense amplifier circuit according to the second configuration example of the present invention .

FIG. 9 is a circuit diagram of a sense amplifier circuit according to a third configuration example of the present invention.

FIG. 10 is an operation timing chart of the sense amplifier circuit according to the third configuration example of the present invention .

FIG. 11 is a circuit diagram of a conventional sense amplifier circuit.

FIG. 12 is an operation timing chart of a conventional sense amplifier circuit.

[Explanation of symbols]

101, 201, 301, 401, 501 Sense amplifiers 102, 202, 302 Bit line precharge circuits 103, 203, 303 Sense amplifier control circuits Qp101, Qp201, Qp301, Qp401, Q
p411, Qp501 First P-channel type MOS transistors Qp102, Qp202, Qp302, Qp402, Q
p412, Qp502 second P-channel MOS transistor Qp513 third P-channel MOS transistor Qp111, Qp211, Qp212, Qp311, Q
p403, Qp413 P-channel MOS transistors Qn101, Qn201, Qn301, Qn401, Q
n411, Qn501 First N-channel MOS transistors Qn102, Qn202, Qn302, Qn402, Q
n412, Qn502 Second N-channel MOS transistors Qn403, Qn413, Qn513 Third N-channel MOS transistors Qn404, Qn414, Qn514, Qn517 Fourth N-channel MOS transistors Qn515, Qn518 Fifth N-channel MOS transistor Qn103, Qn104, Qn111 to Qn113, Q
n203, Qn204, Qn211, Qn212, Qn
303, Qn304, Qn311, Qn405, Qn4
06, Qn415, Qn416 N-channel MOS transistor VDD power supply voltage VSS Ground voltage INV11, INV21, INV31, INV40 to I
NV42, INV51 NOT circuit VSAP, VSAN constant voltage nodes SAE11, SAE21, SAE31, SAE41, S
AE42, SAE51, SAE52, SAC11, B
P, CG0, CG1 Control signals BL0, BL1 First bit line / BL0, / BL1 Second bit line DL First data line / DL Second data line SAP, SAN, SAP40, SAP41, SAN4
0, SAN41, N101, N201, N301, N4
00-N402, N500-N502 Node name P41-P44 Period

Front page continued (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 11/419 G11C 11/409 H01L 21/8242 H01L 27/10 481 H01L 27/108

Claims (2)

(57) [Claims] 1. First and second bit lines, first and second bit lines
P-channel type MOS transistor and first and second
Cell constituted by the N-channel type MOS transistor
And a first P-channel MOS transistor.
Drain of transistor, first N-channel type MO
The drain of the S transistor, the second P-channel type M
The second bit line is connected to the gate of the OS transistor and the gate of the second N-channel MOS transistor, respectively, and the second bit line is connected to the second P-channel MOS transistor.
The drain of the transistor, the second N-channel MO
The drain of the S transistor, the first P-channel type M
The source of the first N-channel MOS transistor and the source of the second N-channel MOS transistor are respectively connected to the gate of the OS transistor and the gate of the first N-channel MOS transistor. Doo is connected, the and the first source of P-channel type MOS transistor and the source of the second P-channel type MOS transistor is connected, when the sense amplifier circuit is in the non-operating state, the 1 and
Source voltage of second P-channel MOS transistor
Is the voltage applied to the first and second bit lines to the first and second
Threshold voltage of second P-channel MOS transistor
Sense amplifier circuitry, wherein the lower it is than a voltage higher absolute value of the. 2. The sense amplifier circuit is in a non-operating state.
First, the first and second P-channel MOS transistors
Node static sources of the sense amplifier circuits according to claim 1, wherein this <br/> and is floating.