JP3482841B2 - Signal generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generator that generates a signal, and more particularly to a signal generator that includes a plurality of shift registers.

[0002]

2. Description of the Related Art FIG. 21 is a diagram showing a conventional signal generator described in "Fundamentals of MOS Integrated Circuits" (edited by Hara, edited by Modern Science Co., Ltd.). It is a figure which shows the signal generation circuit comprised by connecting two stages of shift registers in series. In the figure, 1, 2,
Reference numerals 3 and 4 are transfer gate switches. 5,
Reference numerals 6, 7, and 8 are inverters.

The output stage of the transfer gate switch 1 and the input stage of the inverter 5 are connected. The output stage of the inverter 5 and the input stage of the transfer gate switch 2 are connected. The output stage of the transfer gate switch 2 and the input stage of the inverter 6 are connected.

The output stage of the inverter 6 and the input stage of the transfer gate switch 3 are connected. The output stage of the transfer gate switch 3 and the input stage of the inverter 7 are connected. The output stage of the inverter 7 and the input stage of the transfer gate switch 4 are connected. The output stage of the transfer gate switch 4 and the input stage of the inverter 8 are connected.

The signal generator shown in the figure has transfer gate switches and inverters alternately connected in series. The transfer gate switches 1 and 2 and the inverters 5 and 6 form one shift register (here, the first-stage shift register). The transfer gate switches 3 and 4 and the inverters 7 and 8 form one shift register (here, the second stage shift register). By thus connecting the shift registers in series, a shift register group can be constructed. Here, a case where two shift registers are connected in series will be described as an example.

The signal generator shown in the figure receives a start signal from the transfer gate switch, outputs the output signal of the output stage of the inverter 6 (or the output signal of the shift register of the first stage) Q1, and outputs from the inverter 8. The output signal (or the output signal of the shift register of the second stage) Q2 in the output stage of (2) is taken out.

The transfer gate switch is, for example, a p-channel which is the first switching element.
And two clock signals whose phase differences are opposite to each other are input to the gates of the MOS transistor and the gate of the n-channel MOS transistor which is the second switching element. It is a circuit that transfers an input signal to an output stage when these clock signals satisfy a predetermined relationship. An inverter is a circuit that inverts an input signal and outputs it. In the figure, Vd is a DC voltage applied to the inverter. In the illustrated shift register, the signal input through the transfer gate switch accumulates as electric charge in the input capacitance of the inverter and holds a predetermined constant clock time potential. A shift register having such a structure is called a dynamic type.

The shift register is a circuit that outputs a signal (start signal) input to the transfer gate switch (that is, the transfer gate switch 1) in the preceding stage of the first-stage shift register after shifting for a predetermined time.
The transfer gate switches 1 to 4 shown in the figure use two clock signals having opposite phases as input signals and enter a normal state when the level difference between these clock signals is larger than a predetermined value. The switching circuit is in a non-conducting normal state when the level difference is smaller than a predetermined value.

The signal generator shown in the figure is the gate of the p-channel MOS transistor of the transfer gate switch (that is, the transfer gate switch 1) in the previous stage of the odd-numbered stage (here, the first stage) shift register, and the first stage. N-channe of the transfer gate switch (that is, transfer gate switch 2) in the latter stage of the shift register of
The gate of the MOS transistor of l, p- of the transfer gate switch (that is, the transfer gate switch 3) in the previous stage of the even-numbered stage (here, the second stage)
The clock signal Nclk that is the first clock signal is input to the gate of the MOS transistor of channel, the gate of the n-channel MOS transistor of the transfer gate switch (that is, the transfer gate switch 4) at the rear stage of the second-stage shift register. It

On the other hand, the transfer gate switch 1
n-channel MOS transistor gate, transfer gate switch 2 p-channel MOS transistor gate, transfer gate switch 3 n-channel gate
A clock signal Clk, which is a second clock signal having a phase opposite to the first clock signal, is input to the gate of the MOS transistor and the gate of the p-channel MOS transistor of the transfer gate switch 4.

FIG. 22 is a diagram showing an example of the clock signal Nclk, clock signal Clk, start signal, output signal Q1, and output signal Q2 input to the signal generator shown in FIG. In the figure, the horizontal axis represents time t, and the vertical axis represents the signal level at that time. Here, the clock signals Clk and Nclk have the same signal frequency, are synchronized, and have mutually opposite phases. Also, the pulse width of the start signal is the clock signal Clk or N.
It shall be equal to the length of the signal corresponding to one cycle of clk. Further, the time when the start signal changes from LO to HI is t = t1.

When t1 <t ≦ t2, the pulse width of the start signal is input at the same frequency as the clock signal frequency input to the truss gate switch. At t1, the transfer gate switches 1 and 3 are turned on and the transfer gate switches 2 and 4 are turned off, so that the output of the inverter 5 becomes LO, but both Q1 and Q2 remain LO.
When t2 <t ≦ t3, the transfer gate switch 1,
3 is OFF, transfer gate switches 2 and 4 are O
Since it becomes N, the output of the inverter 5 is held at LO,
Q1 becomes HI. In addition, Q2 remains LO.

When t3 <t ≦ t4, the transfer gate switches 1 and 3 are turned on and the transfer gate switches 2 and 4 are turned off. Therefore, the output of the inverter 5 is HI.
However, Q1 is held at HI. Further, the output of the inverter 7 becomes LO and Q2 becomes LO. t4 <t ≦
At t5, the transfer gate switches 1 and 3 are OF
Since the F and transfer gate switches 2 and 4 are turned on, the output of the inverter 5 is held at HI, and Q1 is at L
It becomes O. Further, the output of the inverter 7 is held as LO, and Q2 becomes HI. When t5 <t ≦ t6, the transfer gate switches 1 and 3 are turned on and the transfer gate switches 2 and 4 are turned off, so that the output of the inverter 5 is held at HI and Q1 becomes LO. Further, the output of the inverter 7 becomes HI, but Q2 is held at HI.

When the shift registers are connected in series in two or more stages, the control signal propagates to the output of the shift register as in the above case.

[0015]

When the signals Q1 and Q2 generated from the signal generator are used as switching signals, the operating frequency of the circuit to which the switching signals are supplied is shortened by shortening the pulse width of the switching signals. Is required to increase. In the conventional signal generator, the pulse widths of the output signals Q1 and Q2 depend on the frequencies of the clock signals Nclk and Clk (or the length of the clock signal per cycle). Therefore, when a clock signal with a low frequency is used, the pulse width output from the signal generator also increases accordingly, so that the output signals Q1, Q
When 2 is used as the switching signal, there is a problem that the switching operation becomes long. When the number of fan-outs of the signal generator is large, the gate control signal is blunted to cause a delay and the limit operating frequency is lowered. Further, even if the fan-out number normally operates normally, a delay occurs due to a process error or a low-performance device is used, the operating frequency is reduced, and the device does not operate stably. Conventionally, in order to solve these problems, a plurality of signal generators are provided in a chip or the number of chips is increased to reduce the number of stages of the signal generators per chip. However, with these methods, there were problems such as a synchronization shift between a plurality of signal generators due to problems with wiring and an increase in cost due to an increase in the number of chips.

The present invention has been made to solve the above-mentioned problems, and obtains a signal generator in which the pulse width of the output signal is short even if the frequency of the clock signal input to the signal generator is lowered. The purpose is to Further, it is possible to obtain a signal generator that can obtain a desired performance even with a low-performance device that could not be used conventionally by increasing the operating frequency without providing a plurality of signal generators or increasing the number of chips. It is an object.

[0017]

SUMMARY OF THE INVENTION The signal generator according to the invention is composed of an upstream and downstream of the transfer gate switch and two inverters having a first switching element and second switching element, the transformer
A first shift register group in which a plurality of shift registers in which a far gate switch and the inverter are alternately connected in series are connected in series, a front stage and a rear stage having a first switching element and a second switching element composed tiger <br/> Nsu fur gate switch and two inverters
The transfer gate switch and the inverter
A shift register in which the over data are alternately connected in series, double
Several shift-connected second shift register groups, output signals of the k-th (k: natural number) shift register of the first shift register group, and k of the second shift register group.
A first logical product calculating means for calculating a logical product of the output signal of the shift register of the first stage, the output signal of the shift register of the (k + 1) th stage (k: natural number) of the first shift register group, and the first signal The second shift register group is provided with a second logical product calculating means for calculating a logical product of the second shift register group and the output signal of the k-th shift register, and the first shift register group and the second shift register group.
A first switching element of a transfer gate switch in the front stage of the shift register of the first shift register group, and a transfer gate switch in the rear stage of the shift register of the first shift register group. Second switching element, the second switching element of the transfer gate switch in the front stage of the shift register of the second shift register group, and the first switching gate of the transfer gate switch in the rear stage of the shift register of the second shift register group. The first clock signal is input to the switching element, the second switching element of the transfer gate switch in the front stage of the shift register of the first shift register group, and the transfer gate of the rear stage of the shift register in the first shift register group Switch number Switching element, the first switching element of the transfer gate switch of the previous stage of the shift register of the second shift register group, the second
The second switching element of the transfer gate switch in the subsequent stage of the shift register of the first shift register group.
The second clock signal having a phase opposite to that of the second clock signal is inputted.

In the signal generator according to the present invention, the first logical product calculating means calculates the logical product of the output signal of the shift register of the first shift register group and the first clock signal, and the second logical product. The product calculating means is configured to calculate the logical product of the output signal of the shift register of the second shift register group and the second clock signal.

[0019] The present invention signal generator according to the prior having a first switching element and second switching element
It is composed of a stage and the subsequent stage of the transfer gate switch and two b <br/> inverter, the transfer gate Sui
Shift register in which a plurality of shift registers and the above inverters are alternately connected in series, a shift register group in which a plurality of shift registers are connected in series, an output signal of the shift register in an odd number stage of the shift register group, and a first shift register group First logical product calculating means for calculating a logical product with a clock signal, an output signal of an even-numbered shift register of the shift register group, and a logic of a second clock signal having a phase opposite to that of the first clock signal. Second to calculate the product
A first switching element of the transfer gate switch in the front stage of the odd-numbered shift register of the shift register group, and a second switching element of the rear stage of the odd-numbered shift register of the shift register group. Switching element, a second switching element of the transfer gate switch in the front stage of the even-numbered shift register of the shift register group, and a first switching element of the transfer gate switch in the rear stage of the even-numbered shift register of the shift register group. A second switching element of the transfer gate switch in the front stage of the odd-numbered shift register in the shift register group, the second switching element of the shift register group in the rear stage, and the transfer gate switch in the rear stage of the odd-numbered shift register of the shift register group A first switching element, a first switching element of a transfer gate switch in a preceding stage of the even-numbered shift register of the shift register group, and a second switching of a transfer gate switch of a subsequent stage in the even-numbered shift register of the shift register group. The device is characterized in that the second clock signal is input to the element.

[0020] The present invention signal generator according to the prior having a first switching element and second switching element
It is composed of a stage and the subsequent stage of the transfer gate switch and two b <br/> inverter, the transfer gate Sui
Schiff the pitch and the inverter are connected in series alternately <br/> Torejisuta, and one transfer gate switch and a shift register group and two inverters connected alternately serially connected elements connected in series to the series A first logical product calculating means for calculating a logical product of an output signal of the shift register of the shift register group and a first clock signal, an output signal of a serial connection element of the shift register group and the first clock signal And a second switching element of the transfer gate switch in the preceding stage of the shift register of the shift register group, which comprises a second AND operation means for calculating a logical product with a second clock signal of opposite phase. Second switching element of the transfer gate switch in the latter stage of the group shift register and the shift register group The first clock signal is input to the second switching element of the transfer gate switch of the series connection element, and the second switching element of the transfer gate switch in the preceding stage of the shift register of the shift register group and the shift of the shift register group The second clock signal is input to the first switching element of the transfer gate switch in the latter stage of the register and the first switching element of the transfer gate switch of the series connection element of the shift register group. To do.

[0021] The present invention signal generator according to the prior having a first switching element and second switching element
It is composed of a stage and the subsequent stage of the transfer gate switch and two b <br/> inverter, the transfer gate Sui
Shift register in which a plurality of shift registers in which the switch and the inverter are alternately connected in series are connected in series, an output signal of the shift register in the shift register group, and a first clock signal. A logical product of the output signal of the shift register used in the first logical product calculating means and a second clock signal having a phase opposite to that of the first clock signal. A second switching element of a transfer gate switch in a front stage of the shift register of the shift register group, and a second transfer gate switch of a rear stage of the shift register in the shift register group. The first clock signal is input to the switching element of the transfer gates of The second switching element of the pitch, the second to the first switching element of the transfer gate switch in the subsequent stage of the shift register in the shift register group
It is characterized in that it is configured to input the clock signal of.

[0022] The present invention signal generator according to the prior having a first switching element and second switching element
It is composed of a stage and the subsequent stage of the transfer gate switch and two b <br/> inverter, the transfer gate Sui
Switch group in which a plurality of shift registers in which the switch and the inverter are alternately connected in series are connected in series, a first switching element, and a second switching element. upstream and downstream transfer gate switch and is composed of two inverters, the Trang
A plurality of shift registers in which the far gate switch and the inverter are alternately connected in series are connected in series, and the output signals of the second shift register group and the odd-numbered shift registers of the first shift register group are provided. First AND operation means for calculating the logical product of the output signal of the odd-numbered shift registers of the second shift register group and the first clock signal, and the output of the even-numbered shift registers of the first shift register group A second logical product calculating means for calculating a logical product of the signal, the output signal of the even-numbered shift register of the second shift register group, and the second clock signal, and the first shift register group and the first shift register group. The second shift register group is connected in parallel, and the first transfer gate switch is provided before the odd-numbered shift register of the first shift register group.
Switching element, a second switching element of a transfer gate switch in a rear stage of the odd-numbered shift register of the first shift register group, a second switching element of a transfer gate switch in a front stage of the even-numbered shift register of the first shift register group, A second switching element, a first switching element of a transfer gate switch at a rear stage of the even-numbered shift register of the first shift register group, and a transfer gate of a front stage of the odd-numbered shift register of the second shift register group; A second switching element of the switch, a first switching element of the transfer gate switch in a subsequent stage of the odd-numbered shift register of the second shift register group, and a front stage of the even-numbered shift register of the second shift register group. Transfer gate switch First switching element, the second
Of the even number of shift registers of the first shift register group, the first clock signal is input to the second switching element of the switch, and the transfer gate of the first stage of the odd shift registers of the first shift register group is input. A second switching element of the switch, a first switching element of a transfer gate switch in a rear stage of the odd-numbered shift register of the first shift register group, and a front stage of a shift register of an even-numbered stage in the first shift register group. A first switching element of the transfer gate switch, a second switching element of a transfer gate switch in a subsequent stage of the even-numbered shift register of the first shift register group, and an odd-numbered shift register of the second shift register group. Previous transfer gate switch First switching element, the second
Second switching element of the transfer gate switch in the rear stage of the odd-numbered shift register group of the shift register group, and the second switching element of the transfer gate switch in the front stage of the even-numbered shift register of the second shift register group, It is characterized in that the second clock signal is inputted to the first switching element of the transfer gate switch at the subsequent stage of the even-numbered shift register of the second shift register group.

[0023] The present invention signal generator according to the prior having a first switching element and second switching element
It is composed of a stage and the subsequent stage of the transfer gate switch and two b <br/> inverter, the transfer gate Sui
Pitch and shift <br/> Torejisuta and the inverter are connected alternately in series, and the first of the one transfer gate switch and two inverters connected in series a series connection element connected alternately in series Shift register group, first
Two transfer gate switches in the front stage and in the rear stage , each including the switching element of
The transfer gate is composed of the inverter and
Switch and the inverter and is <br/> shift registers connected in series alternately, and one of the transfer gate switch and a second shift, connecting the two inverters alternately series-connected elements connected in series to the series, Registers,
A first logical product calculating means for calculating a logical product of the output signal of the shift register of the first shift register group, the output signal of the serial connection element of the second shift register group, and the first clock signal; A second logical product calculating means for calculating a logical product of the output signal of the series connection element of the shift register group, the output signal of the shift register of the second shift register group, and the second clock signal is provided, and the first logical product calculating means is provided. A shift register group and the second shift register group are connected in parallel, a first switching element of a transfer gate switch in a preceding stage of the shift register of the first shift register group, and a shift of the first shift register group. The second switching element of the transfer gate switch in the latter stage of the register and the transfer gate switch of the series connection element of the first shift register group. The first switching element of the pitch,
The second switching element of the transfer gate switch in the front stage of the shift register in the second shift register group, the first switching element of the transfer gate switch in the rear stage of the shift register in the second shift register group, and the second A second switching element of the transfer gate switch in the preceding stage of the shift register of the first shift register group, in which the first clock signal is input to the second switching element of the transfer gate switch of the series connection element of the shift register group, A first switching element of a transfer gate switch in a subsequent stage of the shift register of the first shift register group, a second switching element of a transfer gate switch of series-connected elements of the first shift register group, and the second shift Register group A first switching element of the transfer gate switch in the front stage of the shift register, a second switching element of the transfer gate switch in the rear stage of the shift register of the second shift register group, and a series connection element of the second shift register group. It is characterized in that the second clock signal is inputted to the first switching element of the transfer gate switch.

The signal generator according to the invention is characterized in that it has a series connection element and transformer fur gate switch.

The signal generator according to the present invention is characterized in that the shift register is a static type shift register.

[0026]

DETAILED DESCRIPTION OF THE INVENTION

Embodiment 1. FIG. 1 is a diagram showing a configuration of a signal shift circuit of the signal generator according to the first embodiment. In the figure, the same reference numerals as those in the related art are the same or equivalent. In the figure, 9, 10, 11, 12 are transfer gate switches, and 13, 14, 15, 16 are inverters. The output stage of the transfer gate switch 9 and the input stage of the inverter 13 are connected.
The output stage of the inverter 13 and the input stage of the transfer gate switch 10 are connected. The output stage of the transfer gate switch 10 and the input stage of the inverter 14 are connected. The output stage of the inverter 14 and the input stage of the transfer gate switch 11 are connected.

The output stage of the transfer gate switch 11 and the input stage of the inverter 15 are connected. Output stage of inverter 15 and transfer gate switch 1
2 input stages are connected. The output stage of the transfer gate switch 12 and the input stage of the inverter 16 are connected.

The transfer gate switches 9 and 10 and the inverters 13 and 14 form one shift register (here, the first-stage shift register). The transfer gate switches 11 and 12 and the inverters 15 and 16 form one shift register (here, the second-stage shift register). In other words, (4m-
One shift register (that is, the m-th shift register) is configured by the transfer gate switches of the 3rd and (4m-1) th stages and the inverters of the (4m-2) th and (4m) th stages. (M: natural number).

In the signal generator shown in the figure, a first shift register group in which a shift register in which a transfer gate switch and an inverter are alternately connected are connected in series, and a shift register in which a transfer gate switch and an inverter are alternately connected are connected in series. And a second shift register group connected to. The first shift register group and the second shift register group are connected in parallel. here,
The first shift register group has two shift registers connected in series, and the second shift register group has two shift registers.
An example of connecting in series will be described.

In the first shift register group, transfer gate switches are arranged in odd stages. The clock signal input to the transfer gate switch of each shift register of the first shift register group is the same as the conventional one. In addition, inverters are arranged in even-numbered stages of the first shift register group. An output signal is taken out from the inverter located at the 4mth stage of the first shift register group.

In the second shift register group, transfer gate switches are arranged in odd stages. The p-chan that is the first switching element of the transfer gate switch (here, the transfer gate switches 9 and 11) in the preceding stage of each shift register of the second shift register group.
n-chan which is the second switching element of the transfer gate switch (here, transfer gate switches 10 and 12) at the gate of the MOS transistor of the nel.
The clock signal Clk, which is the second clock signal, is input to the gate of the MOS transistor of the nel.

Further, the gate of the n-channel MOS transistor which is the second switching element of the transfer gate switch (here, transfer gate switches 9 and 11) at the front stage of each shift register of the second shift register group, and the rear stage Transfer gate switches (here, transfer gate switches 10 and 12)
The clock signal Nclk, which is the first clock signal, is input to the gate of the p-channel MOS transistor that is the first switching element.

Further, an inverter is arranged in an even number stage of the second shift register group. An output signal is taken out from the output terminal of the inverter located at the 4mth stage of the second shift register group.

FIG. 2 is a circuit diagram showing an example of the configuration of the first AND operation means and the second AND operation means of the signal generator. In the figure, the output signal (or the output signal of the first-stage shift register) Q1 from the inverter 6 located in the fourth stage of the first shift register group and the inverter 14 located in the fourth stage of the second shift register group Output signal (or 1
The AND circuit (FIG. 2A) corresponding to the first AND operation means for calculating the logical product with the output signal Q1 ′ of the shift register of the first stage and the eighth stage of the first shift register group. The output signal (or the output signal of the second-stage shift register) Q2 from the positioned inverter 8 and the output signal Q of the inverter 14 positioned at the fourth stage of the second shift register group
2 shows an AND circuit (FIG. 2 (b)) corresponding to a second logical product calculating means for calculating a logical product with 1 '.

FIG. 3 is a diagram showing an example of output signals of the signal generator shown in FIGS. In FIG. 3, the output signal Q1 and the output signal Q1 ′ and the output signal Q2 and the output signal Q1 ′ have different phases by half a wavelength of the clock signal Clk (or Nclk).

The operation of the signal generator shown in the figure will be described. At t = t1, the start signal is the clock signal Cl
It is assumed that the input frequency is half that of k (or Nclk) (that is, the pulse width of the start signal corresponds to one cycle of the clock signal). At t1 <t ≦ t2,
Since the transfer gate switches 1 and 10 are turned on and the transfer gate switches 2 and 9 are turned off, the output of the inverter 5 is LO and the output of the inverter 13 is HI.
Is. At this time, Q1 becomes LO, Q1 ′ becomes LO, and Q2 becomes LO.

When t2 <t ≦ t3, the transfer gate switches 1 and 10 are turned off and the transfer gate switches 2 and 9 are turned on, so that the output of the inverter 5 is held at LO and the output of the inverter 13 is at LO. Q1 becomes HI and Q1 ′ becomes LO. t3 <t ≦ t4
Transfer gate switches 1 and 10 are O
Since N and the transfer gate switches 2 and 9 are turned off, the output of the inverter 5 is held at HI and the output of the inverter 13 is held at LO. At this time, Q1 is HI, Q1 '
Becomes HI and Q2 becomes LO.

When t4 <t ≦ t5, the transfer gate switches 1 and 10 are turned off and the transfer gate switches 2 and 9 are turned on, so that the output of the inverter 5 is held at HI and the output of the inverter 13 is at HI. At this time, Q1 is LO, Q1 'is HI, and Q2 is HI.
Becomes When t5 <t ≦ t6, the transfer gate switches 1 and 10 are turned on and the transfer gate switches 2 and 9 are turned off, so that the output of the inverter 5 is held at HI and the output of the inverter 13 is held at HI. At this time, Q1 becomes LO, Q1 ′ becomes LO, and Q2 becomes HI.
When t6 <t, Q1, Q1 ', and Q2 are LO.

Therefore, Q1 'becomes a signal with a phase delay corresponding to half the wavelength of the clock signal in Q1. Also this signal Q
2 is 1 of the clock signal Clk (or Nclk) with respect to Q1
Since the signal has a phase delay corresponding to the period, Q1 'is Q
It is important that the signal also has a fast half-wave phase.

The output signal when the logical product of the output signal Q1 'and the output signal Q1 is calculated is Out1 in FIG.
The output signal when the logical product of the output signal Q1 'and the output signal Q2 is calculated is Out2 in FIG. As a result, the pulse width of the output signals Out1 and Out2 can be half the pulse width of the start signal, that is, half the cycle of the clock signal. Therefore, when the output signals Out1 and Out2 are used as the switching signals, the switching operation of the circuit used as the switching signal can be speeded up. In the first embodiment, the start signal has a length corresponding to one cycle of the clock signal Clk (or Nclk), but it is not limited to this length, and it may be between 1 cycle and 1.5 cycles of the Clk of the clock signal. The same effect can be obtained if the length is equivalent. In this case Q1, Q2
Is a length corresponding to one cycle of the clock signal, Out1, O
ut2 has a length corresponding to a half cycle of the clock signal.

When the shift register has N stages, the logical product of the output of the k-th shift register of the first shift register group and the output of the k-th shift register of the second shift register group is calculated. The calculated value (that is, the output of the first AND operation unit), the output of the (k + 1) th shift register of the first shift register group, and the kth shift register of the second shift register group It may be configured to take out the logical product with the output of (i.e., equivalent to the output of the second logical product calculating means). (However, N is a natural number k is a natural number and k = 1, 2, ..., (N
Satisfying -1))

FIG. 4A is a diagram showing an example of an output waveform when a start signal having a frequency of 6 (MHz) is input to the signal generator having the conventional structure, and particularly, the first shift register group. FIG. 3 is a diagram showing a sum of output signals of shift registers of respective stages (that is, a sum of output signals Q1, Q2, Q3, ...) while connecting a plurality of shift registers in series. FIG. 4B is a diagram showing an example of an output waveform when a start signal of 3 (MHz) is input to the signal generation circuit of the first embodiment, and particularly the first shift register group includes a plurality of shift registers. A plurality of second shift register groups connected in series and a plurality of second shift register groups connected in series are provided, and the output of the k-th shift register of the first shift register group and the second shift register group And the output of the shift register of the (k + 1) th stage of the first shift register group and the output of the shift register of the kth stage of the And the sum of the logical product of the output of the k-th shift register of the second shift register group (that is, the output of the second logical product calculation means).

As shown in the figure, it can be seen that the same output waveform is obtained in both cases. That is, even if the pulse width of the start signal is increased, the pulse width of the output signal can be made approximately the same as the conventional one. Furthermore, when a start signal with the same pulse width as the conventional one is input, the pulse width of the output signal can be halved, and when these signals are used as switching signals, switching operation is faster. Become.

FIG. 5 shows a conventional signal generator and the first embodiment.
In the signal generator of the above, when the pulse width of the output signal is changed, it is shown how much the threshold value of the MOS transistor constituting the signal generator deteriorates and the output signal cannot be generated. In the figure, (2) is the case of the signal generator having the conventional configuration, and (1) is the case of the signal generator of the first embodiment. In the figure, the drive frequency on the horizontal axis means a value obtained by dividing 2π by the pulse width of the output signal. From this Vth ＝
At 1 (V), this embodiment is improved 1.6 times as compared with the conventional example. That is, it has been shown that the control signal generator can be configured with a low-performance device that could not be used conventionally.

Second Embodiment FIG. 6 is a diagram showing the configuration of a signal shift circuit in the signal generator of the second embodiment. In the figure, the same reference numerals as those in FIG. 1 are the same or equivalent.
In the figure, 3a and 4a are transfer gate switches. P-chan of transfer gate switch 3a
The clock signal Clk, n-channel is applied to the MOS transistor of the nel.
The clock signal Nclk is input to the MOS transistor. M of p-channel of transfer gate switch 4a
Clock signal Nclk, n-channel MOS is used for the OS transistor
The clock signal Clk is input to the transistor.

The signal generator according to the second embodiment has a shift register group in which shift registers in which transfer gate switches and inverters are alternately connected are connected in series. In the second embodiment, an example in which two shift registers are connected in series will be described. The p-channel MOS transistor of the transfer gate switch (that is, the transfer gate switch 1) before the shift register of the odd-numbered stage (here, the first stage) of the shift register group, the transfer gate switch of the rear-stage of the odd-numbered shift register (that is, the transfer gate switch 1) N-channe of transfer gate switch 2)
n-channel of the transfer gate switch (that is, the transfer gate switch 3a) in the preceding stage of the even-numbered stage (here, the second stage) shift register
The clock signal Nclk which is the first clock signal is input to the p-channel MOS transistor of the second MOS transistor and the transfer gate switch (that is, the transfer gate switch 4a) in the subsequent stage of the even-numbered shift register.

On the other hand, the n-channel MOS transistor of the transfer gate switch (that is, the transfer gate switch 1) in the front stage of the odd-numbered (first stage here) shift register of the shift register group and the rear-stage of the odd-numbered shift register P-channel MOS transistor of the transfer gate switch (that is, the transfer gate switch 2), p-channel MOS transistor of the transfer gate switch (that is, the transfer gate switch 3) of the preceding stage of the even-numbered stage (the second stage here) of the shift register The clock signal Clk, which is the second clock signal, is input to the n-channel MOS transistor of the transfer gate switch (that is, the transfer gate switch 4) in the subsequent stage of the even-numbered shift register.

Further, inverters are arranged at even-numbered stages of the shift register group. The output signals of the inverters located at the 4mth stage of the shift register group become the output signals Q1 and Q2 of the mth stage shift register (m: natural number). FIG. 7 is a circuit diagram for calculating the logical product of the output signal and the clock signal extracted from the shift register shown in FIG. 6, and FIG. 7A is the logical product of the output signal Q1 and the clock signal Clk. Is an AND circuit diagram corresponding to the first logical product calculating means for extracting as the output signal Out1, FIG. 7B shows the logical product of the output signal Q2 and the clock signal Nclk.
AN corresponding to the second AND operation unit that is extracted as 2
It is a D circuit diagram. FIG. 8 is a diagram showing an example of output signals of the signal generator shown in FIGS. 6 and 7.

The operation of the signal generator of the second embodiment will be described. Further, the start signal is input at t = t1.

When t1 <t ≦ t2, the transfer gate switches 1 and 4a are turned on and the transfer gate switches 2 and 3a are turned off, so that the output of the inverter 5 becomes LO, but both Q1 and Q2 remain LO. t
When 2 <t ≦ t3, transfer gate switches 1 and 4
Since a is OFF and transfer gate switches 2 and 3a are ON, the output of the inverter 5 is held at LO and Q1 becomes HI. In addition, Q2 remains LO.

When t3 <t ≦ t4, the transfer gate switches 1 and 4a are turned on and the transfer gate switches 2 and 3a are turned off. Therefore, the output of the inverter 5 becomes HI, but Q1 is held at HI. Further, since the output of the inverter 7 is held at LO, Q2 becomes HI. When t4 <t ≦ t5, the transfer gate switches 1 and 4a are OFF, the transfer gate switch 2 is
Since 3a is turned on, the output of the inverter 5 is held at HI and Q1 becomes LO. Further, the output of the inverter 7 becomes HI, but Q2 is held at HI. When t5 <t, Q1 and Q2 are LO.

In the shift register of the second embodiment, the clock signals input to the MOS transistors of the transfer gate switches of the even-numbered shift registers are opposite in phase to the clock signals input to the transfer gate switches of the odd-numbered shift registers. It is configured to be. As a result, the phase difference between the output signal Q1 and the output signal Q2 becomes a value corresponding to a half cycle of the clock signal (or a value corresponding to half the pulse width of the start signal).

Therefore, a waveform whose half-wavelength phase is delayed from Q1 is output to Q2. Therefore, Q1 and Q2 and the clock signals Clk and N that enter the transfer gate switch, respectively.
By taking the logical product with clk, each waveform becomes half of the start signal pulse width. When the logical product of the output signal Q1, the clock signals Nclk, Q2, and the clock signal Clk is obtained, the output signals Out1, Out2 have the waveforms shown by the alternate long and short dash line in FIG. In this case as well, the pulse width of the output signal is half the pulse width of the start signal.

Further, the shift registers are connected in N stages in series,
When configuring a shift register group, the MOS of each transfer gate switch of the even-numbered shift registers
The clock signal input to the transistor is configured to have the opposite phase of the clock signal input to the transfer gate switch of the odd-numbered shift register, and the output of the k-th shift register and the clock signal Nclk (or
Clk), and the output of the (k + 1) th stage shift register and the clock signal Clk (or Nclk).

Further, even if the logical product of the output signal Q1 and the output signal Q1 'of the signal generator shown in FIG. 1 and the clock signal Clk or the clock signal Nclk is obtained, the same effect can be obtained and the fan-out number can be increased. Is halved and the critical path is halved. In other words, when generating the same frequency as the control signal generated by the conventional circuit,
The frequency of the signal propagating through the circuit is halved, and the number of control signals can be doubled or the width of the chip can be halved.

In the second embodiment, the shift register has a structure in which the transfer gate switch and the inverter are alternately connected in series, but the structure of the shift register may be a static type structure. The static shift register is for suppressing fluctuations in the output of the shift register, and here, the signals output from the inverters 500 and 700, which will be described later, are fed back to the inputs to be accumulated in the inverters 500 and 700. Inverter 50 for a long time
This makes it possible to hold the output potentials of 0 and 700. FIG. 9 is a diagram showing an example in which a signal shift circuit of a signal generator is configured using a static shift register. In the figure, 100, 200, 30
0, 400 are transfer gate switches, 500,
Reference numerals 600, 700, 800, 900 and 1000 are inverters. The transfer gate switch 100, the inverter 500, and the inverter 600 are connected in series. Inverter 500 is obtained by connecting transfer gate switch 200 and inverter 900 in series.
Are connected in parallel. Transfer gate switches 100, 200 and inverters 500, 600, 9
00 constitutes one shift register. The transfer gate switch 300, the inverter 700, and the inverter 800 are connected in series. The transfer gate switch 400 and the inverter 1000 connected in series are connected in parallel to the inverter 700. Transfer gate switch 300, 400
Further, the inverters 700, 800 and 1000 form one shift register.

The signal generator shown in the figure inputs a start signal from the transfer gate switch 100, which is the first switching element, and takes out a signal from the inverter 600. The operation of the signal generator shown in the figure will be described. FIG. 10 is a diagram showing an example of an output signal of a signal generator configured by using a static shift register.

A start signal is input at t = t1. t1 <t ≦
At t2, transfer gate switches 100 and 400
Is ON, the transfer gate switches 200 and 300 are
It turns off. Therefore, since the output of the inverter 500 becomes LO, the output of the inverter 600 is HI and the output of the inverter 900 is
Output becomes HI. Therefore, Q1 becomes HI. Also Q2
It is LO. When t2 <t ≦ t3, the transfer gate switches 100 and 400 are turned off and the transfer gate switches 200 and 300 are turned on. Therefore, the inverter 90
Since the output from 0 is input to the inverter 500, the output of the inverter 500 is held at LO by this closed loop. Therefore, Q1 is held at HI. Also, because Q1 is input to the inverter 700 and its output becomes LO,
Q2 will be HI.

When t3 <t ≦ t4, the transfer gate switches 100 and 400 are turned on and the transfer gate switches 200 and 300 are turned off. At this time, since the level of the start signal becomes LO, the inverter 50
Since the output of 0 becomes HI, the output of the inverter 600 becomes LO. Moreover, since the output from the inverter 1000 is input to the inverter 700, the output of the inverter 700 is held at LO by this closed loop. Therefore,
Q2 is held at HI. When t4 <t, Q1 and Q2
Are both LO.

The pulse width of Out1 obtained by calculating the logical product of Q1 and the clock signal Clk is half the pulse width of the start signal. Similarly, O obtained by calculating the logical product of Q2 and the clock signal Nclk
The pulse width of ut2 is half the pulse width of the start signal. Therefore, the pulse width of the output signal that can be selected even when the shift register is of the static type can be half the start signal. In this case, since the signal output from the first-stage shift register is synchronized with the start signal, the output signals Out1 and Out2 can be half the pulse width of the start signal.

Further, the signal generator of the second embodiment has shown the shift registers connected in series in a plurality of stages, but it is not limited to this, and the transfer gate switches in the latter stages of the odd-numbered shift registers are eliminated. May be.
For example, as shown in FIG. 11, an odd number of stages (here, the first stage)
So that the transfer gate switch (here, transfer gate switch 2) at the rear stage of the shift register is eliminated and the signal output from the inverter (here, inverter 5) at the front stage is directly input to the inverter (here, inverter 6) at the rear stage. Even with such a configuration, the same effect can be obtained.

In this case, a series connection element in which the transfer gate switch 1, the inverters 5 and 6 are connected in series in this order, and the shift register having the transfer gate switches 3a and 4a and the inverters 7 and 8 are alternately connected in series. It becomes a composition.

Further, although the signal generator of the second embodiment has shown the shift registers connected in series in a plurality of stages, it is not limited to this, and the transfer gate switch in the preceding stage of the even-numbered shift registers is eliminated. May be.
For example, as shown in FIG. 12, the transfer gate switch (here, the transfer gate switch 3a) in the preceding stage of the even-numbered stage (here, the second stage) shift register is eliminated, and the signal output from the preceding stage shift register is converted into an inverter (here The configuration may be such that it is directly input to the inverter 7).

In this case, a series connection element in which the inverter 7, the transfer gate switch 4a, and the inverter 8 are connected in series in this order, and the transfer gate switches 1 and 2 are connected.
Also, the shift registers having the inverters 5 and 6 are alternately connected in series. Also, one transfer gate switch may be used instead of the series connection element described above.

Further, the Q output in the configuration of FIG.
Ou is the logical product of 1 and the clock signal Clk.
It is also possible to adopt a configuration in which the value of t1 and the logical product of Q1 and the clock signal Nclk are calculated as Out2.

Third Embodiment FIG. 13 is a diagram showing the configuration of the signal shift circuit in the signal generator according to the third embodiment. In the drawings, the same reference numerals as those used in the drawings used so far are the same or equivalent.
In the figure, 11a and 12a are transfer gate switches. N- of the transfer gate switch 11a
Clock signal Clk, p-cha is applied to the MOS transistor of channel.
The clock signal Nclk is input to the n-channel MOS transistor. In addition, the transfer gate switch 12a
The n-channel MOS transistor has a clock signal Nclk,
The clock signal Clk is input to the p-channel MOS transistor.

The shift register shown in the figure is composed of a first shift register group (here, the upper series circuit in FIG. 9) and a transfer gate switch in which shift registers in which transfer gate switches and inverters are alternately connected are connected in series. And a second shift register group in which shift registers in which inverters are alternately connected are connected in series (here, the lower series circuit in FIG. 9). The first shift register group and the second shift register group are connected in parallel.

(4m-3) th stage, (4m-1) th stage transfer gate switch and (4m-2) th stage,
The (4m) th stage inverter constitutes one shift register (m: natural number). Here, the first shift register group includes two shift registers connected in series,
The shift register group will be described with reference to an example in which two shift registers are connected in series. N shift registers are provided in the first shift register group and the second shift register group.
The same applies when they are connected in series.

In the shift register of the third embodiment, the clock signal input to the MOS transistors of the transfer gate switches of the even-numbered shift registers of the first shift register group is input to the transfer gate switches of the odd-numbered shift registers. The clock signal has a phase opposite to that of the clock signal. Furthermore, the clock signal input to the MOS transistors of the transfer gate switches of the even-numbered shift registers of the second shift register group is in the opposite phase of the clock signal input to the transfer gate switches of the odd-numbered shift registers. It is composed. Further, the clock signal input to the MOS transistors of the transfer gate switches of the even-numbered shift registers of the first shift register group is the clock signal input to the transfer gate switches of the odd-numbered shift registers of the second shift register group. It is configured to be in phase.

With this configuration, the first-stage shift register of the first shift register group (specifically, the transfer gate switch 1) and the first-stage shift register of the second shift register group are included. When a signal having a pulse width corresponding to two cycles of the clock signal is input to (specifically, the transfer gate switch 9), the output signals Q1, Q1 ', Q2, and Q2' respectively correspond to a half cycle of the clock signal. The output is shifted by the pulse width.

FIG. 14 is a diagram showing an AND circuit corresponding to the first AND operation means for calculating the AND of the output signals Q1 and Q1 'and the clock signal Clk. FIG. 15 is a diagram showing an AND circuit corresponding to the second logical product calculating means for calculating the logical product of the output signals Q2 and Q2 'and the clock signal Nclk.

FIG. 16 is a diagram showing a logical circuit of an AND circuit corresponding to the first logical product calculating means for calculating the logical product of the output signals Q1 and Q1 'and the clock signal Clk. FIG. 17 shows an AN corresponding to the second logical product calculating means for calculating the logical product of the output signals Q2 and Q2 'and the clock signal Nclk.
It is the figure which showed the D circuit by the logic circuit. 51 to 51 in the figure
Reference numeral 60 is an AND element.

In FIG. 16A, the AND operation of the logical product of the clock signal Clk and the output signal Q1 is performed by the AND element 51.
After the logical product of Clk and the output signal Q1 ′ is calculated by the AND element 52, the logical product of the outputs of the AND elements 51 and 52 is AN.
Calculation is performed by the D element 53 to obtain the output signal Out1. FIG.
In (b), the AND element 54 calculates the logical product of the clock signal Clk and the output signal Q1, and the AND element 55 calculates the logical product of the output signal of the AND element 54 and the output signal Q1 ′. Get Out1. 16 (a) or 16 (b), the same output signal Out1 is generated. However, if the first AND operation unit is configured as shown in FIG. 16 (b), it is necessary for the configuration. The number of AND elements is reduced.

In FIG. 17A, the logical product of the clock signal Nclk and the output signal Q2 is calculated by the AND element 56.
The AND element 57 calculates the logical product of Nclk and the output signal Q2 ′, and then the logical product of the outputs of the AND elements 56 and 57 is AN.
Calculation is performed by the D element 58 to obtain the output signal Out2. FIG. 17
In (b), after the logical product of the clock signal Nclk and the output signal Q2 is calculated by the AND element 59, the logical product of the output signal of the AND element 59 and the output signal Q2 ′ is calculated by the AND element 60 to output the output signal. Get Out2. 17 (a) or 17 (b) produces the same output, but if the second AND operation means is constructed as shown in FIG. 17 (b), an AND element is required for the construction. Is reduced in number.

FIG. 18 is a diagram showing an example of output signals of the signal generator of the third embodiment. When a start signal having a pulse width corresponding to two cycles of the clock signal Clk (or Nclk) is input to the signal generator shown in FIG.
The output signals Q1 and Q2 from the shift register group and the output signals Q1 'and Q2' from the second shift register group are as shown in (d) to (g) of FIG. The logical product of the output of the odd-numbered shift register and the clock signal Clk and the logical product of the output of the even-numbered shift register and the clock signal Nclk of the first shift register and the register group are shown in FIGS. It will be something like. Q1, Q2, Q as shown
As shown in FIG. 9, 1'and Q2 'are output with a phase shift corresponding to a half cycle of the clock signal Clk (or Nclk) from the waveform of the start signal.

A logical product (Q11, Q11 ') of the outputs of the even-numbered stages of these shift registers and the clock signal Clk, and a logical product (Q21, Q2) of the outputs of the odd-numbered stages and the clock signal Nclk.
1 ') and Q11, Q21, Q11',
It has two peaks like Q21 '. Therefore, these Q1
Q11 and Q1 for 1, Q21, Q11 'and Q21'
By taking the logical product of 1 ′ and the logical product of Q21 and Q21 ′, output signals Out1 and Out having a pulse width equal to the half cycle of the clock signal like Out1 and Out2.
t2 is obtained. Here, the logical product (Q11, Q1) of the output of the odd number stage of the shift register and the clock signal Clk.
1 '), the logical product (Q21, Q21') of the output of the even number stage and the clock signal Nclk is taken, but the logical product of the output of the odd number stage of the shift register and the clock signal Nclk, the output of the even number stage Even if it is configured to take the logical product with the clock signal Clk, the same effect is obtained.

In the figure, the pulse width corresponding to a half cycle of the clock signal is 1/4 times the start signal pulse width, but the present method is similarly used even if it is less than that. As a result, the pulse width of the signal output from the signal generator is not the limit operating frequency due to the fan-out number, but the frequency of the clock signal that is the input to the transfer gate switch (or the length of one cycle of the clock signal). You will be able to decide.

In the signal generator of the third embodiment, the first shift register group has a plurality of shift registers connected in series,
The second shift register group has been described by taking a plurality of shift registers connected in series as an example. However, as shown in FIG. 19, a transfer gate switch (here, a transfer gate switch) at a rear stage of an odd-numbered shift register of the first shift register group is used. The transfer gate switch 2) is eliminated so that the output signal of the inverter 5 is directly input to the inverter 6, and the transfer gate switch (here, the transfer gate switch) at the rear stage of the odd-numbered shift register of the second shift register group is used. The gate switch 10) may be omitted and the output signal of the inverter 13 may be directly input to the inverter 14.

At this time, the first shift register group alternates the series connection element in which the transfer gate switch 1, the inverters 5 and 6 are connected in this order, and the shift register having the transfer gate switches 3a and 4a and the inverters 7 and 8. It will be connected to. Further, at this time, the second shift register group alternately connects the series connection element in which the transfer gate switch 9 and the inverters 13 and 14 are connected in this order and the shift register including the transfer gate switches 11a and 12a and the inverters 15 and 16. It becomes the composition.

In the signal generator of the third embodiment, the first shift register group has a plurality of shift registers connected in series, and the second shift register group has a plurality of shift registers connected in series. As described above, as shown in FIG. 20, the transfer gate switch (here, the transfer gate switch 3a) in the previous stage of the even-numbered shift register of the first shift register group is eliminated, and the output signal of the inverter 6 (or the shift register in the previous stage is eliminated). Output signal of the second shift register group is directly input to the inverter 7, and the transfer gate switch (here, the transfer gate switch 11a) at the rear stage of the even-numbered shift register of the second shift register group is eliminated and the inverter 14 Input signal (or the output signal of the previous stage shift register) It may be configured to be directly input to the over motor 15.

At this time, the first shift register group includes a series connection element in which the inverter 7, the transfer gate switch 4a and the inverter 8 are connected in this order, and the shift register having the transfer gate switches 1 and 2 and the inverters 5 and 6. The configuration is such that they are connected alternately. At this time, the second shift register group alternately includes a series connection element in which the inverter 15, the transfer gate switch 12a, and the inverter 16 are connected in this order, and the shift register including the transfer gate switches 9 and 10 and the inverters 13 and 14 alternately. It becomes a connected configuration.

Further, one transfer gate switch may be used instead of the series connection element described above. Further, the same effect can be obtained even if the shift register is configured by using a static type shift register.

[0083]

According to the signal generator of the present invention,
A transfer gate switch at a front stage and a rear stage having a first switching element and a second switching element ;
It consists of two inverters ,
Switch and the above inverter are alternately connected in series.
A plurality of shift registers connected in series, first and second transfer gate switches having a first switching element and a second switching element, and two inverters. Consists of and on
The second shift register group in which a plurality of shift registers in which the transfer gate switch and the inverter are alternately connected in series are connected in series, and the k-th stage of the first shift register group ( k: a natural number) first logical product calculating means for calculating a logical product of the output signal of the shift register and the output signal of the k-th shift register of the second shift register group, the first shift register group Of (k +
1) A second logical product calculating means for calculating a logical product of the output signal of the shift register at the stage (k: natural number) and the output signal of the shift register at the k stage of the second shift register group, The first shift register group and the second shift register group are connected in parallel, the first switching element of the transfer gate switch in the preceding stage of the shift register of the first shift register group, and the first shift The second switching element of the transfer gate switch in the latter stage of the shift register of the register group, the second switching element of the transfer gate switch in the former stage of the shift register of the second shift register group, the second switching element
The first switching element of the transfer gate switch at the subsequent stage of the shift register of the shift register group of
Of the first shift register group, the second switching element of the transfer gate switch in the front stage of the shift register of the first shift register group, and the first switching gate of the transfer gate switch in the rear stage of the shift register of the first shift register group. The switching element, the first switching element of the transfer gate switch in the front stage of the shift register of the second shift register group, and the second switching element of the transfer gate switch in the rear stage of the shift register of the second shift register group Since the second clock signal having a phase opposite to that of the first clock signal is input, the pulse width corresponding to one cycle of the first clock signal is applied to the first shift register group and the second shift register group. Even if a signal having The pulse width of the output signal output from the logical product calculating means can be made to correspond to a half cycle of the first clock signal, so that the first logical product calculating means and the second logical product calculating means The pulse width of the output signal that is output can be shortened.

In the signal generator according to the present invention, the first logical product calculating means calculates the logical product of the output signal of the shift register of the first shift register group and the first clock signal, and the second logical product is obtained. Since the product calculating means is configured to calculate the logical product of the output signal of the shift register of the second shift register group and the second clock signal, the first logical product calculating means and the second logical product calculating means. The pulse width of the output signal output from can be shortened.

[0085] The present invention signal generator according to the prior having a first switching element and second switching element
It is composed of a stage and the subsequent stage of the transfer gate switch and two b <br/> inverter, the transfer gate Sui
Shift register in which a plurality of shift registers and the above inverters are alternately connected in series, a shift register group in which a plurality of shift registers are connected in series, an output signal of the shift register in an odd number stage of the shift register group, and a first shift register group First logical product calculating means for calculating a logical product with a clock signal, an output signal of an even-numbered shift register of the shift register group, and a logic of a second clock signal having a phase opposite to that of the first clock signal. Second to calculate the product
A first switching element of the transfer gate switch in the front stage of the odd-numbered shift register of the shift register group, and a second switching element of the rear stage of the odd-numbered shift register of the shift register group. Switching element, a second switching element of the transfer gate switch in the front stage of the even-numbered shift register of the shift register group, and a first switching element of the transfer gate switch in the rear stage of the even-numbered shift register of the shift register group. A second switching element of the transfer gate switch in the front stage of the odd-numbered shift register in the shift register group, the second switching element of the shift register group in the rear stage, and the transfer gate switch in the rear stage of the odd-numbered shift register of the shift register group A first switching element, a first switching element of a transfer gate switch in a front stage of the even-numbered shift register of the shift register group, and a second switching of a transfer gate switch of a rear-stage of the even-numbered shift register in the shift register group. Since the second clock signal is input to the element, the first AND operation means is provided even if a signal having a pulse width corresponding to one cycle of the first clock signal is input to the shift register group. Since the pulse width of the output signal output from the second AND operation unit can be set to correspond to the half cycle of the first clock signal, the first AND operation unit and the second AND unit. The pulse width of the output signal output from the calculation means can be shortened.

[0086] The present invention signal generator according to the prior having a first switching element and second switching element
It is composed of a stage and the subsequent stage of the transfer gate switch and two b <br/> inverter, the transfer gate Sui
Schiff the pitch and the inverter are connected in series alternately <br/> Torejisuta, and one transfer gate switch and a shift register group and two inverters connected alternately serially connected elements connected in series to the series A first logical product calculating means for calculating a logical product of an output signal of the shift register of the shift register group and a first clock signal, an output signal of a serial connection element of the shift register group and the first clock signal And a second switching element of the transfer gate switch in the preceding stage of the shift register of the shift register group, which comprises a second AND operation means for calculating a logical product with a second clock signal of opposite phase. Second switching element of the transfer gate switch in the latter stage of the group shift register and the shift register group The first clock signal is input to the second switching element of the transfer gate switch of the series connection element, and the second switching element of the transfer gate switch in the preceding stage of the shift register of the shift register group and the shift of the shift register group Since the second clock signal is input to the first switching element of the transfer gate switch in the latter stage of the register and the first switching element of the transfer gate switch of the series connection element of the shift register group, the shift register Even if a signal having a pulse width corresponding to one period of the first clock signal is input to the group, the pulse width of the output signal output from the first AND operation unit and the second AND operation unit is Can be equivalent to one half cycle of the clock signal Therefore, the pulse width of the output signal output from the first AND operation unit and the second AND operation unit can be shortened.

[0087] The present invention signal generator according to the prior having a first switching element and second switching element
It is composed of a stage and the subsequent stage of the transfer gate switch and two b <br/> inverter, the transfer gate Sui
Shift register in which a plurality of shift registers in which the switch and the inverter are alternately connected in series are connected in series, an output signal of the shift register in the shift register group, and a first clock signal. A logical product of the output signal of the shift register used in the first logical product calculating means and a second clock signal having a phase opposite to that of the first clock signal. A second switching element of a transfer gate switch in a front stage of the shift register of the shift register group, and a second transfer gate switch of a rear stage of the shift register in the shift register group. The first clock signal is input to the switching element of the transfer gates of The second switching element of the pitch, the second to the first switching element of the transfer gate switch in the subsequent stage of the shift register in the shift register group
Since the clock signal is input to the shift register group, even if a signal having a pulse width corresponding to one cycle of the first clock signal is input to the shift register group, the first AND operation unit and the second logic Since the pulse width of the output signal output from the product calculating means can be equivalent to a half cycle of the first clock signal, it is output from the first AND calculating means and the second AND calculating means. The pulse width of the output signal can be shortened.

[0088] The present invention signal generator according to the prior having a first switching element and second switching element
It is composed of a stage and the subsequent stage of the transfer gate switch and two b <br/> inverter, the transfer gate Sui
Switch group in which a plurality of shift registers in which the switch and the inverter are alternately connected in series are connected in series, a first switching element, and a second switching element. upstream and downstream transfer gate switch and is composed of two inverters, the Trang
A plurality of shift registers in which the far gate switch and the inverter are alternately connected in series are connected in series, and the output signals of the second shift register group and the odd-numbered shift registers of the first shift register group are provided. First AND operation means for calculating the logical product of the output signal of the odd-numbered shift registers of the second shift register group and the first clock signal, and the output of the even-numbered shift registers of the first shift register group A second logical product calculating means for calculating a logical product of the signal, the output signal of the even-numbered shift register of the second shift register group, and the second clock signal, and the first shift register group and the first shift register group. The second shift register group is connected in parallel, and the first transfer gate switch is provided before the odd-numbered shift register of the first shift register group.
Switching element, a second switching element of a transfer gate switch in a rear stage of the odd-numbered shift register of the first shift register group, a second switching element of a transfer gate switch in a front stage of the even-numbered shift register of the first shift register group, A second switching element, a first switching element of a transfer gate switch at a rear stage of the even-numbered shift register of the first shift register group, and a transfer gate of a front stage of the odd-numbered shift register of the second shift register group; A second switching element of the switch, a first switching element of the transfer gate switch in a subsequent stage of the odd-numbered shift register of the second shift register group, and a front stage of the even-numbered shift register of the second shift register group. Transfer gate switch First switching element, the second
Of the even number of shift registers of the first shift register group, the first clock signal is input to the second switching element of the switch, and the transfer gate of the first stage of the odd shift registers of the first shift register group is input. A second switching element of the switch, a first switching element of a transfer gate switch in a rear stage of the odd-numbered shift register of the first shift register group, and a front stage of a shift register of an even-numbered stage in the first shift register group. A first switching element of the transfer gate switch, a second switching element of a transfer gate switch in a subsequent stage of the even-numbered shift register of the first shift register group, and an odd-numbered shift register of the second shift register group. Previous transfer gate switch First switching element, the second
Second switching element of the transfer gate switch in the subsequent stage of the odd-numbered shift register of the shift register group, the second switching element of the transfer gate switch in the previous stage of the even-numbered shift register of the second shift register group, Since the second clock signal is input to the first switching element of the transfer gate switch at the subsequent stage of the even-numbered shift register of the second shift register group, the first shift register group and the second shift register group are provided. 2 of the first clock signal in the register group
Even if a signal having a pulse width corresponding to the cycle is input, the pulse width of the output signal output from the first AND operation unit and the second AND operation unit corresponds to a half cycle of the first clock signal. The pulse widths of the output signals output from the first AND operation means and the second AND operation means can be shortened.

[0089] The present invention signal generator according to the prior having a first switching element and second switching element
It is composed of a stage and the subsequent stage of the transfer gate switch and two b <br/> inverter, the transfer gate Sui
Pitch and shift <br/> Torejisuta and the inverter are connected alternately in series, and the first of the one transfer gate switch and two inverters connected in series a series connection element connected alternately in series Shift register group, first
Two transfer gate switches in the front stage and in the rear stage , each including the switching element of
The transfer gate is composed of the inverter and
Switch and the inverter and is <br/> shift registers connected in series alternately, and one of the transfer gate switch and a second shift, connecting the two inverters alternately series-connected elements connected in series to the series, Registers,
A first logical product calculating means for calculating a logical product of the output signal of the shift register of the first shift register group, the output signal of the serial connection element of the second shift register group, and the first clock signal; A second logical product calculating means for calculating a logical product of the output signal of the series connection element of the shift register group, the output signal of the shift register of the second shift register group, and the second clock signal is provided, and the first logical product calculating means is provided. A shift register group and the second shift register group are connected in parallel, a first switching element of a transfer gate switch in a preceding stage of the shift register of the first shift register group, and a shift of the first shift register group. The second switching element of the transfer gate switch in the latter stage of the register and the transfer gate switch of the series connection element of the first shift register group. The first switching element of the pitch,
The second switching element of the transfer gate switch in the front stage of the shift register in the second shift register group, the first switching element of the transfer gate switch in the rear stage of the shift register in the second shift register group, and the second A second switching element of the transfer gate switch in the preceding stage of the shift register of the first shift register group, in which the first clock signal is input to the second switching element of the transfer gate switch of the series connection element of the shift register group, A first switching element of a transfer gate switch in a subsequent stage of the shift register of the first shift register group, a second switching element of a transfer gate switch of series-connected elements of the first shift register group, and the second shift Register group A first switching element of the transfer gate switch in the front stage of the shift register, a second switching element of the transfer gate switch in the rear stage of the shift register of the second shift register group, and a series connection element of the second shift register group. Since the second clock signal is input to the first switching element of the transfer gate switch,
Even if a signal having a pulse width corresponding to two cycles of the first clock signal is input to the shift register group and the second shift register group, the first logical product calculating means and the second logical product calculating means Since the pulse width of the output signal output can correspond to a half cycle of the first clock signal, the pulse width of the output signals output from the first AND operation means and the second AND operation means is increased. The pulse width can be shortened.

[0090] According to the signal generating apparatus according to the present invention, since a series connection element and transformer fur gate switch, the pulse width of the first logical product operation means and the second AND output signal output from the arithmetic means Can be shortened .

In the signal generator according to the present invention, since the shift register is a static type shift register,
The pulse width of the output signal output from the first AND operation unit and the second AND operation unit can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a signal generator according to a first embodiment.

FIG. 2 is a diagram showing the first embodiment of the signal generator of the first embodiment.
FIG. 3 is a circuit diagram showing an example of the configuration of the logical product calculation means and the second logical product calculation means of FIG.

FIG. 3 is a diagram showing an example of an output waveform of the signal generator according to the first embodiment.

FIG. 4 is a diagram showing an example of an output waveform of the signal generator according to the first embodiment.

FIG. 5 is a diagram showing the relationship between the frequency of an output signal and the threshold value of a MOS transistor included in the device in the signal generator of the first embodiment.

FIG. 6 is a circuit diagram showing a configuration of a signal generator according to a second embodiment.

FIG. 7 is a diagram showing a first embodiment of the signal generator of the third embodiment.
FIG. 3 is a circuit diagram showing an example of the configuration of the logical product calculation means and the second logical product calculation means of FIG.

FIG. 8 is a diagram showing an example of output waveforms of the signal generator according to the second embodiment.

FIG. 9 is a diagram showing an example of a signal generator according to a second embodiment.

FIG. 10 is a diagram showing an example of output waveforms of the signal generator according to the second embodiment.

FIG. 11 is a diagram showing an example of a signal generator according to a second embodiment.

FIG. 12 is a diagram showing an example of a signal generator according to a second embodiment.

FIG. 13 is a circuit diagram showing a configuration of a signal generator according to a third embodiment.

FIG. 14 is a circuit diagram showing first AND operation means in the signal generator according to the third embodiment.

FIG. 15 is a circuit diagram showing a second AND operation unit in the signal generator according to the third embodiment.

FIG. 16 is a circuit diagram showing first AND operation means in the signal generator according to the third embodiment.

FIG. 17 is a circuit diagram showing second AND operation means in the signal generator according to the third embodiment.

FIG. 18 is a diagram showing an example of output waveforms in the signal generator according to the third embodiment.

FIG. 19 is a circuit diagram showing a configuration of a signal generator according to a third embodiment.

FIG. 20 is a circuit diagram showing a configuration of a signal generator according to a third embodiment.

FIG. 21 is a diagram showing an example of a configuration of a conventional signal generator.

FIG. 22 is a diagram showing an example of an output waveform of a conventional signal generator.

[Explanation of symbols]

1, 2, 3, 4, 9, 10, 11, 12 shift registers 5, 6, 7, 8, 13, 14, 15, 16 inverters

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-61-202399 (JP, A) Special table S62-502370 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 5/00 H03K 23/42

Claims (11)

(57) [Claims] 1. A transfer gate switch including a first switching element and a second switching element in a front stage and a rear stage, and two inverters .
A first shift register group in which a plurality of shift registers in which a transfer gate switch and the inverter are alternately connected in series are connected in series, a front stage having a first switching element and a second switching element, and and the subsequent transfer gate switch
It consists of two inverters ,
Switch and the above inverter are alternately connected in series.
A plurality of shift registers connected in series, an output signal of the shift register at the k-th stage (k: natural number) of the first shift register group, and the second shift register group. A first logical product calculating means for calculating a logical product with the output signal of the k-th shift register, and the output signal of the (k + 1) th (k: natural number) shift register of the first shift register group The second shift register group includes a second logical product calculating means for calculating a logical product of the output signal of the k-th shift register of the second shift register group, and the first shift register group and the second shift register group. Are connected in parallel, and the first switching element of the transfer gate switch in the front stage of the shift register of the first shift register group and the rear stage of the shift register of the first shift register group The second switching element of the transfer gate switch, the second switching element of the transfer gate switch in the front stage of the shift register of the second shift register group, and the second switching element of the transfer stage of the shift register in the second shift register group. A first clock signal is input to the first switching element, the second switching element of the transfer gate switch in the front stage of the shift register in the first shift register group, the second stage of the shift register in the first shift register group First switching element of the transfer gate switch, the first switching element of the transfer gate switch in the front stage of the shift register of the second shift register group, and the transfer of the rear stage of the shift register in the second shift register group A signal generator characterized in that it is configured to input a second clock signal having a phase opposite to that of the first clock signal to the second switching element of the gate switch. 2. A first logical product calculating means calculates a logical product of an output signal of a shift register of a first shift register group and a first clock signal, and a second logical product calculating means is a second logical product calculating means. 2. The signal generator according to claim 1, wherein the signal generator is configured to calculate a logical product of an output signal of the shift register of the shift register group and the second clock signal. 3. A transfer gate switch at a front stage and a rear stage having a first switching element and a second switching element, and two inverters .
A shift register group in which a plurality of shift registers in which a transfer gate switch and the inverter are alternately connected in series are connected in series, an output signal of a shift register in an odd number stage of the shift register group, and a first clock signal And a logical product of an output signal of the even-numbered shift register of the shift register group and a second clock signal having a phase opposite to that of the first clock signal. A second switching element of a transfer gate switch before the odd-numbered shift register of the shift register group, and a second transfer gate of the odd-numbered shift register of the shift register group The second switching element of the switch, the transistor of the previous stage of the even-numbered shift register of the shift register group. The first clock signal is input to the second switching element of the shift gate switch and the first switching element of the transfer gate switch at the subsequent stage of the even-numbered shift register of the shift register group, and the odd number of the shift register group is input. Second switching element of the transfer gate switch in the front stage of the shift register in the first stage, the first switching element of the transfer gate switch in the rear stage of the odd-numbered shift register in the shift register group, and the shift register in the even-numbered stage of the shift register group The second clock signal is input to the first switching element of the transfer gate switch in the preceding stage and the second switching element of the transfer gate switch in the subsequent stage of the even-numbered shift register of the shift register group. Special Signal generating apparatus according to. 4. A transfer gate switch at a front stage and a rear stage having a first switching element and a second switching element, and two inverters .
Lance Fur gate switch and the inverter connected in series are alternately been a shift register, and connected in series a series connection element connects the one tiger <br/> Nsu fur gate switches and two inverters in series alternately A shift register group, first logical product calculating means for calculating a logical product of the output signal of the shift register of the shift register group and the first clock signal, the output signal of the serial connection element of the shift register group, and the first signal The first switching element of the transfer gate switch in the preceding stage of the shift register of the shift register group is provided with a second AND operation unit that calculates a logical product of a second clock signal having a phase opposite to that of the first clock signal. , A second switching element of a transfer gate switch in a subsequent stage of the shift register of the shift register group. And the second switching element of the transfer gate switch of the series connection element of the shift register group, the first clock signal is input to the second switching element of the transfer gate switch of the preceding stage of the shift register of the shift register group, The second clock signal is input to the first switching element of the transfer gate switch in the subsequent stage of the shift register of the shift register group and the first switching element of the transfer gate switch of the series connection element of the shift register group. A signal generator characterized by being configured. 5. A pre-stage and post-stage transfer gate switch having a first switching element and a second switching element, and two inverters .
A shift register group in which a plurality of shift registers in which a transfer gate switch and the inverter are alternately connected in series are connected in series, and the output signal of the shift register of the shift register group and the logic of the first clock signal First logical product calculating means for calculating a product, and a logical product of an output signal of the shift register used in the first logical product calculating means and a second clock signal having a phase opposite to that of the first clock signal. A second switching element of a transfer gate switch in a front stage of the shift register of the shift register group, and a second switching of a transfer gate switch of a rear stage of the shift register in the shift register group. The first clock signal is input to the element, and the first stage clock signal of the shift register of the shift register group is input. A signal characterized in that the second clock signal is input to the second switching element of the transfer gate switch and the first switching element of the transfer gate switch in the subsequent stage of the shift register of the shift register group. Generator. 6. A front and rear transfer gate switch having a first switching element and a second switching element, and two inverters .
A first shift register group in which a plurality of shift registers in which a transfer gate switch and the inverter are alternately connected in series are connected in series, a front stage having a first switching element and a second switching element, and and the subsequent transfer gate switch
It consists of two inverters ,
Switch and the above inverter are alternately connected in series.
A plurality of shift registers connected in series, an output signal of the odd-numbered shift registers of the first shift register group, and an output signal of the odd-numbered shift registers of the second shift register group First AND operation means for calculating the AND of the signal and the first clock signal, the output signal of the even-numbered shift register of the first shift register group and the even-numbered shift register of the second shift register group Second logical product calculating means for calculating a logical product of the output signal of the second shift signal and the second clock signal, the first shift register group and the second shift register group are connected in parallel, The first switching element of the transfer gate switch in the front stage of the odd-numbered shift register of the first shift register group, and the first switching element of the odd-numbered shift register of the first shift register group Second switching element of the first-stage transfer gate switch, second switching element of the previous-stage transfer gate switch of the even-numbered shift register of the first shift register group, and even-numbered shift of the first shift-register group A first switching element of a transfer gate switch at a subsequent stage of the register, a second switching element of a transfer gate switch at a previous stage of the odd-numbered shift register group of the second shift register group, an odd-numbered stage of the second shift register group The first switching element of the transfer gate switch in the subsequent stage of the shift register, the first switching element of the transfer gate switch in the previous stage of the even-numbered shift register in the second shift register group, and the second switching register group in the second shift register group Even-numbered shift register First to the second switching element in the subsequent stage of the transfer gate switch
The second switching element of the transfer gate switch in the front stage of the odd-numbered shift register of the first shift register group and the transfer of the rear stage of the odd-numbered shift register in the first shift register group. A first switching element of the gate switch, a first switching element of the transfer gate switch in a front stage of the even-numbered shift register of the first shift register group, a rear stage of the even-numbered shift register of the first shift register group Second switching element of the transfer gate switch, the first switching element of the transfer gate switch in the previous stage of the odd-numbered shift register of the second shift register group, and the odd-numbered shift register of the second shift register group Transfer gate switch in the latter stage Second switching element, the second switching element of the transfer gate switch in the previous stage of the even-numbered shift register of the second shift register group, the second stage of the even-numbered shift register of the second shift register group Second to the first switching element of the transfer gate switch of
A signal generator characterized in that it is configured to input the clock signal of. 7. A front gate and a rear stage transfer gate switch having a first switching element and a second switching element, and two inverters .
Lance Fur gate switch and the inverter connected in series are alternately been a shift register, and connected in series a series connection element connects the one tiger <br/> Nsu fur gate switches and two inverters in series alternately first shift register group was, and upstream and downstream transfer gate switch having a first switching element and second switching element
It consists of two inverters ,
Switch and the above inverter are alternately connected in series.
Shift register which, as well as one transfer gate switch and two of the second shift register group and inverters are connected alternately serially connected elements connected in series in series, the output signal of the shift register of the first shift register group AND means for calculating the logical product of the output signal of the serially connected elements of the second shift register group and the first clock signal, and the output signal of the serially connected elements of the first shift register group and the first A second logical product calculating means for calculating a logical product of the output signal of the shift register of the second shift register group and the second clock signal, and the first shift register group and the second shift register group. Are connected in parallel, the first switching element of the transfer gate switch in the preceding stage of the shift register of the first shift register group, the first switching element Second switching element of the transfer gate switch in the subsequent stage of the shift register of the shift register group, the first switching element of the transfer gate switch of the series connection element of the first shift register group, and the shift of the second shift register group The second switching element of the transfer gate switch in the front stage of the register, the first switching element of the transfer gate switch in the rear stage of the shift register of the second shift register group, and the transfer of the series connection element of the second shift register group. The first clock signal is input to the second switching element of the gate switch, the second switching element of the transfer gate switch in the preceding stage of the shift register of the first shift register group, and the shift register of the first shift register group. The first switching element of the transfer gate switch in the latter stage of the transistor, the second switching element of the transfer gate switch of the series connection element of the first shift register group, and the transfer of the preceding stage of the shift register in the second shift register group. A first switching element of a gate switch, a second switching element of a transfer gate switch in a subsequent stage of the shift register of the second shift register group, and a first transfer gate switch of a series connection element of the second shift register group. 2. A signal generator, wherein the switching element is configured to input the second clock signal. 8. A signal generating apparatus according to the series connected elements to claim 4 and 7, characterized in that it has a transformer fur gate switch. 9. The signal generator according to claim 1, wherein the shift register is a static shift register. 10. First AND operation means and second theory
The logical product calculating means is composed of logic circuits having the same configuration.
The method according to any one of claims 1 to 7, characterized in that
Signal generator. 11. A first AND operation means and a second theory
The logical product calculating means is composed of AND circuits having the same configuration.
The method according to any one of claims 1 to 7, characterized in that
On-board signal generator.