JP3482982B2 - Manufacturing method of epitaxial wafer with EG layer - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an epitaxial silicon wafer whose back surface is subjected to external gettering (hereinafter referred to as EG). More specifically, an epitaxial layer on the wafer surface,
In addition, the EG layer (extrinsic gettering sin
The present invention relates to a method for manufacturing an epitaxial wafer with an EG layer in which k) are simultaneously formed.

[0002]

2. Description of the Related Art In a device manufacturing process involving high temperature heat treatment, a silicon wafer is contaminated with impurities such as transition metals, which adversely affect device characteristics. In order to remove the impurities from the front surface of the wafer, a polysilicon layer having a thickness of 1 to 2.0 μm is formed on the back surface of the wafer by a chemical vapor deposition (CVD) method, and the polysilicon layer is removed by E
A back surface gettering process for forming a G layer is known.
On the other hand, a silicon epi technique capable of forming a single crystal silicon layer having an arbitrary film thickness and resistivity on a substrate has become indispensable for manufacturing a high performance device. An EG layer is previously formed on the back surface of the epitaxial wafer manufactured by the silicon epi technique to remove impurities.

Conventionally, this epitaxial wafer with an EG layer has, as shown in FIG. 3, a slicing step 1 in which a pulled silicon single crystal is sliced to obtain a silicon wafer, and flatness on both sides of the silicon wafer and the parallelism of the wafer. Lapping step 2 for increasing the degree of processing, chemical etching step 3 for removing the work-affected layer of the lapping silicon wafer, cleaning step 4 for cleaning the chemically etched silicon wafer, and EG treatment step for forming an EG layer on the back surface of the wafer 5 and a polishing step 6 in which only the surface of the EG-treated wafer is polished to a mirror surface,
It is manufactured through a cleaning step 7 for cleaning the polished silicon wafer and a step 8 for epitaxially growing single crystal silicon on the surface of the cleaned silicon wafer. In this step 8, a raw material gas containing Si is introduced into the reaction furnace by a CVD method together with a carrier gas such as H ₂ and is generated by thermal decomposition of the raw material gas on the surface of a silicon wafer heated to a high temperature of 1000 ° C. or higher. The deposited Si is deposited.

[0004]

However, in the above-mentioned conventional manufacturing method, since the formation of the EG layer and the formation of the epitaxial layer are performed separately, the number of steps is large and the production efficiency is not high. Further, since the epitaxial growth is performed at a high temperature of about 1000 ° C., there is a drawback that the warp of the wafer becomes relatively large. The object of the present invention is to efficiently and efficiently perform E with a small number of steps.
It is to provide a method capable of manufacturing an epitaxial wafer with a G layer. Another object of the present invention is to provide a method of manufacturing an epitaxial wafer with an EG layer, in which the warp of the wafer is relatively small.

[0005]

The invention according to claim 1 is
The surface roughness is 1.2 nm or less and the back surface roughness is 1.2 n
A method for producing an epitaxial wafer with an EG layer, characterized in that Si produced by thermal decomposition of SiH ₄ at 400 to 1000 ° C. is respectively deposited on both surfaces of a silicon wafer having a thickness of more than 0.1 m and not more than 0.1 μm. is there. The surface roughness of the wafer is 1.2 nm or less, and the back surface roughness of the wafer is more than 1.2 nm and 0.1 μm or less.
When H ₄ is pyrolyzed at 400 to 1000 ° C., Si generated by this pyrolysis is deposited on both sides of this wafer,
An epitaxial layer is simultaneously formed on the front surface of the wafer and an EG layer is simultaneously formed on the rear surface of the wafer.

The invention according to claim 2 is the invention according to claim 1, wherein the surface roughness is 1.2 nm or less and the back surface roughness exceeds 1.2 nm and is 0.1 μm as shown in FIG. The following silicon wafer is a slicing step 10 in which a pulled silicon single crystal is sliced to obtain a silicon wafer, and a step 11 in which both sides of the silicon wafer are lapped or ground to increase the flatness of the wafer and the parallelism of the wafer. A chemical etching step 12 for removing the work-affected layer of the lapped or ground silicon wafer, a polishing step 13 for polishing only the surface of the chemically etched silicon wafer to a mirror surface, and a cleaning step 14 for cleaning the polished silicon wafer. It is a method for manufacturing an epitaxial wafer with an EG layer obtained through By keeping the back surface of the wafer chemically etched and polishing only the front surface of the wafer to a mirror surface, the roughness of the front surface of the wafer can be made smaller than the roughness of the back surface of the wafer.

The invention according to claim 3 is the invention according to claim 1, wherein, as shown in FIG. 2, the surface roughness is 1.2 nm or less and the back surface roughness exceeds 1.2 nm and is 0.1 μm. The following silicon wafer is a slicing step 10 for slicing the pulled silicon single crystal to obtain a silicon wafer, and a step 11 for lapping or grinding both sides of the silicon wafer to enhance the flatness and parallelism of the wafer. A polishing step 16 for polishing both surfaces of the lapped or ground silicon wafer to a mirror surface, and a chemical etching step 17 for chemically etching only the back surface of the polished silicon wafer,
Step 1 of cleaning the chemically etched silicon wafer
8 is a method for manufacturing an epitaxial wafer with an EG layer obtained through the steps of By polishing both surfaces of the wafer to make them mirror-finished and then chemically etching only the back surface of the wafer to increase the roughness of the back surface, the roughness of the back surface of the wafer can be made larger than the roughness of the front surface of the wafer.

The invention according to claim 4 relates to claims 1 to 3.
The invention according to any one of claims 1 to 3, wherein a step 19 of lightly polishing only the surface of the silicon wafer on which Si is deposited on both sides as shown in FIGS. 1 and 2, and a step of cleaning the lightly polished silicon wafer It is a manufacturing method of an epitaxial wafer with an EG layer further including 20. After the epitaxial layer is formed, since light polishing is performed, it is difficult to remove N by a normal cleaning process.
Impurities such as transition metals such as i can be easily removed by this light polishing. In addition, compared with conventional polishing, the light polishing has a very small polishing allowance, so the polishing time is greatly reduced,
Productivity is dramatically improved.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. (a) Simultaneous formation of epi layer and EG layer In order to simultaneously form an epitaxial layer on the wafer surface of the present invention and an EG layer on the back surface of the wafer, the surface roughness of the silicon wafer is made different from that of the back surface. There is a need. That is, the roughness of the surface forming the epitaxial layer must be a mirror surface of 1.2 nm or less, and the roughness of the back surface of the EG layer must be more than 1.2 nm and 0.1 μm or less. . This surface roughness is preferably 0.3n
m or more and 1.2 nm or less, and the back surface roughness is preferably 5
It is 0 nm or more and 0.1 μm or less. Surface roughness is 1.2n
When it exceeds m, the epitaxial layer of silicon cannot be vapor-phase grown, and when the back surface roughness is 1.2 nm or less, the EG layer made of a polysilicon layer cannot be formed. If the back surface roughness exceeds 0.1 μm, the site flatness and the like deteriorate. In addition, all of these surface roughness displays described in the present specification are RMS displays of the surface roughness in a measurement area of 1 μm × 1 μm by an atomic force microscope. When a silicon wafer having the above surface roughness is put in a furnace for CVD and SiH ₄ is pyrolyzed in the furnace at 400 to 1000 ° C., Si produced by the pyrolysis is deposited on both surfaces of the wafer, and the wafer surface At the same time, an epitaxial layer and an EG layer are simultaneously formed on the back surface of the wafer. This step is indicated by reference numeral 15 in FIGS. The thermal decomposition temperature of this SiH ₄ is preferably 600 to 800 ° C. S below 400 ° C
The thermal decomposition of iH ₄ is not sufficient, and if it exceeds 1000 ° C., the warp of the wafer becomes large, which is not preferable.

(B) Pretreatment The silicon wafer before being placed in this CVD furnace is
Made by the street method. The first method is to cut a grown single crystal ingot into blocks having a constant resistivity range, grind each block to an outer diameter to make the diameter uniform, and then show a specific crystal orientation. Orient flat or notch the outer diameter ground block. Next, as shown by reference numeral 10 in FIG. 1, the above block is sliced to obtain a silicon wafer. After chamfering (beveling), both surfaces of the silicon wafer are mechanically polished (lapped) or ground as indicated by reference numeral 11. This lapping method is a method of pouring a lapping liquid, which is a mixture of alumina or silicon carbide abrasive grains and glycerin, between a lapping plate and a wafer, rotating under pressure, and mechanically polishing both surfaces of the wafer by sliding. By this lapping, the concavo-convex layer on both sides of the wafer, which is mainly caused by slicing, is shaved, and the flatness of the wafer surface and the parallelism of the wafer are increased. Next, as shown by reference numeral 12, the silicon wafer that has been lapped or ground is chemically etched. As a result, the damage layer on both surfaces of the wafer, that is, the work-affected layer, which is generated in the machining process such as block cutting, outer diameter grinding, slicing, lapping, and grinding is removed. This etchant includes an acid etchant or an alkaline etchant. The former uses a mixed acid of hydrofluoric acid (HF) and nitric acid (HNO ₃ ) as water (H ₂ O).
Alternatively, it is an etchant with a ternary element diluted with acetic acid (CH ₃ COOH), and Si is oxidized by nitric acid to form S.
After forming iO ₂ , this SiO ₂ is dissolved and removed by hydrofluoric acid. The latter is an etchant prepared by diluting KOH or NaOH with water. Then, as indicated by reference numeral 13,
After only the surface of the chemically etched silicon wafer is polished to a mirror surface, as shown by reference numeral 14, the polished silicon wafer is a mixed solution of inorganic alkali and hydrogen peroxide and has an etching rate of 10 angstroms with respect to silicon. / Min or less (eg KOH (1% by weight), H ₂ O ₂ (1% by volume) at 50 ° C)
(Mixed solution of 1.), then immersed in a HF solution having a concentration of 1.5%, and further washed with pure water. This polishing is performed by a silicon wafer polishing machine, a lens polishing machine, or the like. The wafer surface is abraded to a depth of 1 to 10 angstroms, preferably about 2 angstroms by polishing. The second method is shown by reference numerals 10 and 11 in FIG.
As shown in (1), after slicing a block to obtain a silicon wafer as in the first method, both surfaces of the wafer are lapped or ground. Then, as indicated by reference numeral 16, both sides of the lapped or ground silicon wafer are polished to be mirror-finished. The lapping, grinding and polishing are performed in the same manner as the first method. Next, as indicated by reference numeral 17, only the back surface of this silicon wafer is chemically etched. Examples of this etching method include a method of spin-coating the back surface of the wafer with an etchant on the back surface, and a method of exposing the back surface of the wafer to the bottom surface with an etchant shower from below. This etchant has an etching rate of 7 to 100 μm / min, a surface tension of at least 60 dyne / cm, and a viscosity of 1.4 to
An acid etchant or an alkaline etchant having a viscosity of 4.5 mPa · sec can be used. An example of an acid etchant is HF (50%): HNO ₃ (70%): H ₃ PO ₄ (85%): H ₂ O = 2: 1: 1: 1 or 2:
1: 1: 1.5 or HF (50%): HNO ₃ (70%): H ₃ PO ₄ (85%) = 2: 1: 1
and so on. Further, as indicated by reference numeral 18, the silicon wafer whose back surface is etched is washed in the same manner as in the method described in reference numeral 14 of the pretreatment in FIG.

(C) Post-treatment After forming an epitaxial layer on the front surface of the wafer and an EG layer on the back surface of the wafer at the same time, reference numeral 1 in FIGS.
As shown in FIGS. 9 and 20, polishing of the wafer surface and cleaning of the silicon wafer are performed. This polishing is lightly performed by a silicon wafer polishing machine, a lens polishing machine, or the like. 50 to 5 wafer surface by polishing
Polish to a depth of 00 Å, preferably about 100 Å. If it is less than 50 angstroms, the contamination is not completely removed, and if it exceeds 500 angstroms, the defect density increases, which is not preferable. RC the silicon wafer after light polishing
Wash with a washing method such as method A. If either the epitaxial layer or the EG layer is formed to be thicker than a desired thickness by CVD, only the thicker layer is polished after the simultaneous formation of the epitaxial layer and the EG layer, and then the above-mentioned reference numeral is used. The steps designated 19 and 20 are performed.

[0012]

EXAMPLES Next, examples of the present invention will be described together with comparative examples. <Example 1> An epitaxial wafer with an EG layer was manufactured through the steps shown in FIG. That is, a P-type silicon wafer having a diameter of 200 mm and a thickness of 750 μm, which was polished simultaneously on both sides, was obtained from a silicon single crystal ingot pulled up by the CZ method. This silicon wafer was chemically etched with the above-mentioned acid etchant to remove the work-affected layer of the wafer, and then only the wafer surface was polished to a depth of 100 Å to make the surface mirror-finished. This silicon wafer was washed in the same manner as the method described with reference numeral 14 in FIG. The surface roughness of the cleaned silicon wafer is about 0.8.
nm, and the back surface roughness was about 80 nm. After placing the silicon wafer to wafer duplex is exposed to the furnace for CVD, introducing SiH ₄ together with a carrier gas of H _2, under a pressure of 0.19Torr, the SiH ₄ approximately at a temperature of 655 ± 5 ° C. It was pyrolyzed for 100 minutes. Pyrolytically produced Si was deposited on both sides of the wafer at a rate of about 200 Å / min. The silicon wafer was taken out of the furnace, only the surface of the wafer was lightly polished, and the entire wafer was washed by the RCA method. The cleaned silicon wafer had a mirror surface on the front surface and polysilicon on the back surface.

<Embodiment 2> EG is processed through the steps shown in FIG.
An epitaxial wafer with layers was manufactured. The same silicon wafer as in Example 1 was polished on both sides, and then the back surface of the wafer was turned to the upper surface, and HF (50%): HNO ₃ (70%): H ₃ was applied to this back surface.
Spin coating was performed while dropping an acid etchant of PO ₄ (85%): H ₂ O = 2: 1: 1: 1.5. This silicon wafer was washed in the same manner as the method described with reference numeral 14 in FIG. The cleaned silicon wafer had a surface roughness of about 0.6 nm and a back surface roughness of about 90 nm. Thereafter, this silicon wafer was put into a furnace for CVD in the same manner as in Example 1, and
SiH ₄ was pyrolyzed under the same conditions as above. After processing for 100 minutes, the silicon wafer was taken out of the furnace, only the surface of the wafer was lightly polished, and the entire wafer was washed by the RCA method. The cleaned silicon wafer had a mirror surface on the front surface and polysilicon on the back surface.

<Comparative Example 1> After the steps shown in FIG.
An epitaxial wafer with layers was manufactured. After lapping both surfaces of the same silicon wafer as in Example 1, chemical etching was performed with an acid etchant as in Example 1, and RC
The silicon wafer was washed by method A. Then the silicon wafer was placed in a furnace for CVD, introducing SiH ₄ together with a carrier gas of H _2, under a pressure of 0.20Torr, to decompose the SiH ₄ to about 100 minutes heat at a temperature of 655 ± 5 ° C.. Pyrolytically produced Si was deposited on both sides of the wafer at a rate of about 200 Å / min. The silicon wafer was taken out of the furnace, only the wafer surface was polished, and the entire wafer was cleaned by the RCA method. The cleaned silicon wafer had a mirror surface on the front surface and polysilicon on the back surface.

After putting this silicon wafer in a furnace for CVD, SiH ₄ was introduced together with a carrier gas of H ₂ ,
SiHCl ₃ was pyrolyzed at a temperature of 1150 ° C. under atmospheric pressure for about 10 minutes. Si produced by pyrolysis at a rate of about 1 μm / min was deposited on both sides of this wafer. The silicon wafer was taken out of the furnace, only the wafer surface was polished, and the entire wafer was cleaned by the RCA method.

<Comparison Evaluation> The crystallinity of the front and back surfaces of the silicon wafers of Examples 1, 2 and Comparative Example 1 was examined by the X-ray diffraction method. As a result, it was found that the peaks of the single crystal silicon appeared on the front surface of the wafer, while the peaks other than the single crystal silicon appeared on the back surfaces of any of the wafers, and the wafer was converted into polysilicon.

The average thickness of the epitaxial layer on the front surface of the silicon wafers of Examples 1, 2 and Comparative Example 1 was measured by infrared interferometry, and E on the back surface was made of polysilicon.
The average thickness of the G layer was examined by a spectroscopic film thickness meter. The results are shown in Table 1.

[0018]

[Table 1]

As is clear from Table 1, the thickness of the epitaxial layer of Examples 1 and 2 is almost equal to the thickness of the epitaxial layer of Comparative Example 1 of the prior art, and the thickness is sufficient for forming a high performance device. Have. In addition, Example 1 and Example 2
It was found that the thickness of the EG layer of No. 2 was thicker than that of the conventional EG layer of Comparative Example 1, and was a thickness capable of sufficiently performing the back surface gettering.

The warp of the silicon wafers of Example 1, Example 2 and Comparative Example 1 was examined by ADE9300. As a result, the average values of Example 1 and Example 2 were 17 to
While falling within the range of 18 μm, the average value of Comparative Example 1 was 27.6 μm. From this, the wafers of Example 1 and Example 2 have lower thermal decomposition temperatures than Comparative Example 1,
This proves that the warpage is smaller than that of the wafer of Comparative Example 1.

[0021]

As described above, according to the present invention, E
Since the G layer is formed and the epitaxial layer is formed at the same time, an epitaxial wafer with an EG layer can be efficiently obtained in a small number of steps. SiH when forming these layers
_Since the thermal decomposition temperature of ₄ is relatively low, the warp of the obtained wafer is relatively small and the thermal energy can be saved. In particular, after forming the epitaxial layer, FIG.
Also, if the light polishing shown by reference numeral 19 in FIG. 2 is performed, impurities such as transition metals that are difficult to remove by the normal cleaning process can be easily removed by this light polishing. In addition, compared with the conventional polishing, the light polishing has a very small polishing allowance, so that the polishing time is greatly reduced and the productivity is dramatically improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a method of manufacturing an epitaxial wafer with an EG layer according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a diagram showing a method of manufacturing an epitaxial wafer with an EG layer according to a second embodiment of the present invention in the order of steps.

FIG. 3 is a diagram showing a method of manufacturing an epitaxial wafer with an EG layer in Comparative Example 1 in the order of steps.

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-56-18412 (JP, A) JP-A-58-191422 (JP, A) JP-A-2-50434 (JP, A) JP-A-3- 201440 (JP, A) JP-A-6-104229 (JP, A) JP-A-8-115918 (JP, A) JP-A-8-316180 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/20 H01L 21/205 H01L 21/304 601 H01L 21/322

Claims (4)

(57) [Claims] 1. By thermally decomposing SiH ₄ at 400 to 1000 ° C. on both surfaces of a silicon wafer having a surface roughness of 1.2 nm or less and a back surface roughness of more than 1.2 nm and 0.1 μm or less. A method for manufacturing an epitaxial wafer with an EG layer, characterized in that the generated Si is deposited respectively. 2. A slicing method for obtaining a silicon wafer by slicing a pulled silicon single crystal to obtain a silicon wafer having a surface roughness of 1.2 nm or less and a back surface roughness of more than 1.2 nm and 0.1 μm or less. Step (10), and step (11) of lapping or grinding both sides of the silicon wafer to increase flatness and parallelism of the wafer.
A chemical etching step (12) for removing the work-affected layer of the lapped or ground silicon wafer, a polishing step (13) for polishing only the surface of the chemically etched silicon wafer to a mirror surface, and the polishing. The manufacturing method according to claim 1, which is obtained through a cleaning step (14) of cleaning a silicon wafer. 3. A slicing method for obtaining a silicon wafer by slicing a pulled silicon single crystal to obtain a silicon wafer having a surface roughness of 1.2 nm or less and a back surface roughness of more than 1.2 nm and 0.1 μm or less. Step (10), a step of lapping or grinding both sides of the silicon wafer to increase flatness of the wafer and parallelism of the wafer
(11), a polishing step (16) to polish both sides of the lapped or ground silicon wafer to a mirror surface, a chemical etching step (17) to chemically etch only the back surface of the polished silicon wafer, and the chemical The manufacturing method according to claim 1, which is obtained through a cleaning step (18) of cleaning the etched silicon wafer. 4. The method according to claim 1, further comprising a step (19) of lightly polishing only the surfaces of the silicon wafers having Si deposited on both sides thereof, and a step (20) of cleaning the lightly polished silicon wafers. Or the manufacturing method described.