JP3485745B2 - Solid-state imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device in which a color filter is mounted on a CCD image sensor to perform color image pickup.

[0002]

2. Description of the Related Art In a solid-state image pickup device such as a television camera using a CCD image sensor, each scanning timing of the image sensor is set based on various synchronizing signals according to a predetermined television system. For example, in the case of the NTSC system, the vertical scanning period is set to 1/60 seconds, and the horizontal scanning period is set to 2/525 of the vertical scanning period. As a result, a video signal in which the video information for one screen is continuous in units of one horizontal line is output.

FIG. 10 is a block diagram showing the basic construction of an image pickup apparatus using a CCD image sensor.
FIG. 6 is a timing diagram explaining the operation. The frame transfer type CCD image sensor 1 includes an image pickup unit 1i, a storage unit 1s, a horizontal transfer unit 1h, and an output unit 1d. The image pickup unit 1i is composed of a plurality of CCD shift registers that are continuous in the vertical direction and are parallel to each other. Each bit of the shift register constitutes a light receiving pixel, and stores information charges generated during the image pickup period. The storage unit 1s is
It is composed of a plurality of CCD shift registers which are continuous with the shift register of the image pickup unit 1i and have the same number of bits, and information charges transferred and output from the respective light receiving pixels of the image pickup unit 1i are temporarily supplied to each bit of these shift registers. accumulate.
The horizontal transfer unit 1h includes a single CCD shift register in which the output of each shift register of the storage unit 1s is coupled to each bit, and sequentially outputs the information charges transferred and output from the storage unit 1s in units of one horizontal line. Transfer to 1d side. The output unit 1d includes a capacitor that receives information charges on the output side of the horizontal transfer unit 1h, receives the information charges transferred and output from the horizontal transfer unit 1h, and outputs a voltage value according to the charge amount. The change in the voltage value output here becomes the image signal Y0 (t).

The drive circuit 2 includes a frame clock generator 2
f, vertical clock generator 2v, horizontal clock generator 2
h, a reset clock generator 2r and a sampling clock generator 2s. The frame clock generator 2f generates a frame clock φf in response to the frame shift timing signal FT and supplies it to the image pickup unit 1i. As a result, the information charges accumulated in each light receiving pixel of the image pickup section 1i are transferred at high speed to the accumulation section 1s in each vertical scanning period. The vertical clock generation unit 2v generates a vertical clock φv in response to the vertical synchronization signal VT and the horizontal synchronization signal HT and supplies it to the storage unit 1s. As a result, in the storage unit 1s, the information charges transferred and output from the image pickup unit 1i are taken in and temporarily stored, and the stored information charges are transferred in units of one horizontal line in each horizontal scanning period to the horizontal transfer unit 1h. Transferred to. The horizontal clock generation unit 2h generates a horizontal transfer clock φh in response to the horizontal synchronization signal HT and supplies it to the horizontal transfer unit 1h. As a result, the information charges taken from the storage unit 1s to the horizontal transfer unit 1h for each horizontal line are sequentially transferred and output to the output unit 1d side. The reset clock generation unit 2r generates a reset clock φr for sequentially discharging the information charges of the output unit 1d in synchronization with the operation of the horizontal clock generation unit 2h, and supplies the reset clock φr to the output unit 1d. As a result, the information charges output from the horizontal transfer section 1h to the output section 1d are accumulated in pixel units. Then, the sampling clock generation unit 2s, similarly to the reset clock generation unit 2r, generates a sampling clock φs for sequentially sampling the image signal Y0 (t) output from the output unit 1d in synchronization with the operation of the horizontal clock generation unit 2h. Occurs,
It is supplied to the sample hold circuit 4 described later.

The timing control circuit 3 operates on the basis of a reference clock CLK having a constant cycle, and generates and drives a vertical synchronizing signal VT and a horizontal synchronizing signal HT which determine respective timings of vertical scanning and horizontal scanning of the image sensor 1. Circuit 2
Supply to. At the same time, the frame shift timing signal FT is generated in a cycle that coincides with the vertical synchronization signal VT and is supplied to the drive circuit 2. In this timing control circuit 3, in order to keep the exposure state of the image sensor 1 optimum,
Shutter control is performed to discharge the information charges of the image pickup unit 1i in the middle of the vertical scanning period according to the amount of the information charges generated in the image pickup unit 1i. That is, if the timing of the shutter operation is advanced, the period until the start of frame transfer becomes longer,
The information charge is accumulated in the imaging unit 1i for a longer period. On the contrary, if the timing of the shutter operation is delayed, the period until the start of frame transfer is shortened, and the imaging unit 1
In i, information charges are accumulated in a short period. The shutter operation for discharging the information charges of the image pickup unit 1i is executed by the action of the drive clock supplied from the drive circuit 2 to the image sensor 1.

The sample and hold circuit 4 samples the image signal Y0 (t) in response to the sampling clock φs supplied from the sampling clock generator 2s to generate an image signal Y1 (t) which maintains the signal level. To do. Normally, in the output unit 1d, the charging and discharging of the capacitance is repeated according to the reset clock φr, so that the output unit 1d
The image signal Y0 (t) obtained from d has a reset level and
The signal level corresponding to the amount of information charges continues alternately. Therefore, the phase of the sampling clock φr is set so that only the signal level of the image signal Y0 (t) is extracted. Therefore, it is possible to obtain the image signal Y1 (t) in which only the signal level corresponding to the amount of information charges accumulated in the output section 1d is continuous.

The frequency dividing circuit 5 includes a first frequency divider 5a for dividing the reset clock φr and a sampling clock φs.
Is composed of a second frequency divider 5b which divides the frequency. The divider circuit 5 divides the reset clock φr and the sampling clock φs as necessary, and the output unit 1
By intermittently performing the reset operation of d, the output unit 1d
The information charges of a plurality of pixels can be mixed with each other. For example, as shown in FIG. 12, the reset clock φr0 and the sampling clock φs0, which are generated in the same cycle as the horizontal clock φh, are divided in half, and the reset clock φr1 has a cycle twice that of the horizontal clock φh. And the sampling clock φs1 are supplied to the output section 1d and the sample and hold circuit 4. In the reset clock φr1 whose cycle is doubled, the information charge is reset every time the information charge of two pixels is accumulated in the output section 1i, so that the image signal Y0 (t) of approximately double level is output. Obtainable.

In the image pickup section 1i of the image sensor 1, the maximum period for accumulating the information charges for one screen is one vertical scanning period. However, when the object captured by the image sensor 1 is dark, the accumulation period is set to the maximum. However, there are cases where the insufficient exposure cannot be resolved. In such a case, the frequency divider circuit 5 is operated to halve the reset operation of the information charges in the output section 1d.
The information charges of two pixels are taken out as one pixel by thinning out. Therefore, even for a dark subject, the image signal Y1 (t) of a sufficient level can be obtained without underexposure.

[0009]

When a color image is picked up by the image pickup device, the image pickup section 1i of the image sensor 1 is equipped with a color filter which associates each light receiving pixel with a predetermined color component. In this color filter, the three primary colors or their complementary colors are regularly assigned to the segments corresponding to the respective light receiving pixels in a predetermined order. For example, in the mosaic filter,
White (W) and green (G) are alternately assigned to the odd row segments, and cyan (Cy) and yellow (Ye) are alternately assigned to the even row segments.

When the color filter as described above is attached to the image pickup unit 1i of the image sensor 1, two pixels which are adjacent in the horizontal direction are associated with different color components, and are thus accumulated in the adjacent light receiving pixels. The information charges also represent different color components. Therefore, if the image signal Y0 (t) is obtained by synthesizing the information charges of two pixels at the output section, different color components are mixed, and the desired color component cannot be reproduced correctly in the subsequent signal processing. is there. For example, W and G are combined in an odd row and C is combined in an even row.
When y and Ye are combined, W + G = Cy + Ye = R
+ 2G + B (W = R + G + B, Cy = G + B, Ye = R
+ G), the color information contained in the image signal Y0 (t) is single. Therefore, even if each light receiving pixel of the image pickup unit 1i is associated with a specific color component, it is impossible to reproduce information corresponding to those color components from the image signal Y0 (t).

Therefore, an object of the present invention is to make it possible to synthesize and take out information charges of two pixels or more than three pixels with respect to an image sensor equipped with a color filter.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that a plurality of color filters are arranged in a matrix in association with each segment. The light-receiving pixels of are coupled to a plurality of vertical transfer units for each column, the outputs of the plurality of vertical transfer units are coupled to the bits of the horizontal transfer unit, and the output charge amount of the horizontal transfer unit is output to the output unit. After being transferred to the plurality of vertical transfer units by the image sensor that is converted into a voltage value and output, and the information charges generated in the plurality of light receiving pixels, the horizontal transfer is performed for each horizontal line from the plurality of vertical transfer units. A drive circuit that transfers to the transfer section, further transfers from the horizontal transfer section to the output section, and discharges the information charges accumulated in the output section in synchronization with the transfer operation of the horizontal transfer section, and the output section. Output from A detection circuit that extracts the voltage value to be generated in synchronization with the discharge operation of the drive circuit, and the drive circuit alternately supplies information charges to the horizontal transfer unit in the odd columns and the even columns of the plurality of vertical transfer units. And the transfer cycle of the output section is set to an integral multiple of the transfer operation cycle of the horizontal transfer section, and information charges for a plurality of pixels are accumulated in the output section. It is to take out the potential change stepwise in the process in which the information charges for a plurality of pixels are sequentially accumulated in the output section in synchronization with the transfer operation of the horizontal transfer section.

According to the present invention, when each light receiving pixel of the image sensor is associated with the same color component every other column, the transfer from the vertical transfer unit to the horizontal transfer unit is performed every other column. As a result, the information charges associated with the same color component are simultaneously transferred to the vertical transfer unit.
On the output side of the horizontal transfer unit, information charges of a plurality of pixels associated with the same color component are accumulated and a voltage value corresponding to the amount of information charges is output. At the same time, the output voltage value at each stage of the process of sequentially accumulating the information charges for a plurality of pixels is extracted. Therefore, the information charges of the plurality of pixels can be combined without mixing different color components, and the combined output of the plurality of pixels and the individual output of each pixel can be extracted.

[0014]

1 is a block diagram showing the configuration of a solid-state image pickup device of the present invention, and FIG. 2 is a mosaic type color filter mounted on an image sensor 11 used in the solid-state image pickup device of the present invention. 2 is a plan view showing the configuration of FIG. The frame transfer type CCD image sensor 11 has an image pickup unit 11i, a storage unit 11s, and a horizontal transfer unit 11h, as in FIG.
And an output unit 11d. The image pickup section 11i is composed of a plurality of CCD shift registers that are continuous in the vertical direction and are parallel to each other. Each bit of these shift registers constitutes a light receiving pixel, and accumulates information charges generated during the image pickup period. The storage unit 11s is connected to the shift register of the imaging unit 11i and has a plurality of Cs having the same number of bits.
The shift register is composed of a CD shift register, and the information charge transferred and output from each light receiving pixel of the image pickup section 11i is temporarily stored in each bit of these shift registers. The shift register of the storage unit 11s is a horizontal transfer unit 11h for even columns.
Are formed so that the number of sides connected to is increased by 1 bit. The horizontal transfer unit 11h includes a single CCD shift register in which the output of each shift register of the storage unit 11s is coupled to each bit, and sequentially transfers the information charges transferred and output from the storage unit 11s to the output unit 11d side. . In the shift register of the horizontal transfer unit 1h, two columns of the shift register of the image pickup unit 11i and the storage unit 11s are associated with 1 bit. The output unit 11d includes a capacitor that receives information charges on the output side of the horizontal transfer unit 11h, receives the information charges transferred and output from the horizontal transfer unit 11h, and outputs a voltage value according to the charge amount.

A mosaic type color filter as shown in FIG. 2 is attached to the image pickup section 11i of the image sensor 11. This color filter is divided into a plurality of segments C so as to correspond to the respective light receiving pixels of the image pickup section 11i, and each segment C is associated with a predetermined color component. For example, when four types of color components of white (W), green (G), yellow (Ye) and cyan (Cy) are used, W and G are alternately associated with the segment C of the odd-numbered row, and Ye and Cy is alternately associated with the segment C of the even-numbered row.
Therefore, in the odd-numbered light-receiving pixels, the information charge corresponding to the W component and the information charge corresponding to the G component are alternately accumulated in each column, and in the light-receiving pixels in the even-numbered row, the Ye component is accumulated for each column. And information charges corresponding to the Cy component are alternately accumulated.

The drive circuit 12 includes a frame clock generator 12f, a vertical clock generator 12v, an auxiliary clock generator 12u, a horizontal clock generator 12h, a reset clock generator 12r and a sampling clock generator 12s.
It is composed of The frame clock generation unit 12f generates a frame clock φf in response to the frame shift timing signal FT of the vertical scanning cycle, and supplies it to the image pickup unit 11i. As a result, the information charge accumulated in each light receiving pixel of the image pickup section 1i is transferred at high speed to the accumulation section 1s in each vertical scanning period. The frame clock generator 12f is the same as the drive circuit 2 in FIG. Vertical clock generator 1
2v generates a vertical clock φv in response to the vertical synchronizing signal VT and the horizontal synchronizing signal HT and supplies it to the storage unit 11s. The auxiliary clock generating unit 12u generates the auxiliary clock φu having a cycle of ½ of the vertical clock φh in response to the horizontal synchronizing signal HT, and outputs only to the bits additionally provided in the even columns at the output end of the storage unit 11s. Supply. As a result, in the storage unit 11s, the information charges transferred and output from the image pickup unit 11i are taken in and temporarily stored, and the information charges are stored in odd-numbered columns and even-numbered columns every ½ of the horizontal scanning period. The data is transferred to the horizontal transfer unit 11h alternately by ½ line for each column.

The horizontal clock generator 12h generates a horizontal transfer clock φh in response to the horizontal synchronizing signal HT and supplies it to the horizontal transfer unit 11h. Since the number of bits of the shift register of the horizontal transfer unit 11h is reduced to 1/2, the information charges taken into the horizontal transfer unit 11h are transferred to the output unit 11d in a period of 1/2 of the horizontal scanning period. Transfer output is completed. The transfer output of the information charges of 1/2 the number of pixels is repeated twice during one horizontal scanning period, so that the transfer output of the information charges for one row is completed. When a mosaic type color filter as shown in FIG. 2 is connected to the image pickup unit 11i of the image sensor 11, the accumulation unit 11
When the information charges are transferred from s to the horizontal transfer portion 11s every other column (an odd column and an even column are separately provided), the same color component becomes continuous in a half of the horizontal scanning period.

The reset clock generation section 12r generates a reset clock φr for sequentially discharging the information charges of the output section 1d in synchronization with the operation of the horizontal clock generation section 12h and supplies it to the output section 11d. As a result, the horizontal transfer unit 11h
The information charges output from the output unit 11d to the output unit 11d are discharged in pixel units. Then, the sampling clock generation unit 12s generates a sampling clock φs for sequentially sampling the image signal Y0 (t) output from the output 11d in synchronization with the operation of the horizontal clock generation unit 12h, similarly to the reset clock generation unit 12r. Then, it is supplied to the sample hold circuit 14 described later.

The timing control circuit 13 generates a vertical synchronizing signal VT and a horizontal synchronizing signal HT which determine respective timings of vertical scanning and horizontal scanning of the image sensor 11, and further transfers a frame in a cycle that coincides with the vertical synchronizing signal VT. The timing signal FT is generated and supplied to the drive circuit 12, respectively. The timing control circuit 13 is the same as the timing control circuit 3 shown in FIG.

The sample hold circuit 14 samples the image signal Y0 (t) output from the image sensor 11 in response to the sampling clock φs supplied from the sampling clock generator 12s. Normally, output unit 1
In 1d, since the charge and discharge of the capacitance are repeated at the timing according to the reset clock φr, the reset level and the signal level corresponding to the amount of information charges are alternately continuous in the image signal Y0 (t) obtained from the output unit 11d. . Therefore, the phase of the sampling clock φr is set so that only the signal level of the image signal Y0 (t) is extracted. Therefore,
It is possible to obtain the image signal Y1 (t) in which only the signal level corresponding to the amount of information charges accumulated in the output section 1d is continuous.

The frequency dividing circuit 15 divides the reset clock φr at a predetermined ratio and supplies it to the output section 11d. As a result, the reset operation of the output unit 1d becomes intermittent, and the information charges of a plurality of pixels are mixed at the output unit 11d. For example, the reset clock φr0 generated at the same frequency as the horizontal clock φh is divided in half, and the reset clock φr1 whose cycle is twice the horizontal clock φh is supplied to the output unit 11d. It Further, the frequency dividing circuit 15 shifts the timing of the frequency dividing operation by one clock cycle in each vertical scanning period according to the frame identification signal FLD which is inverted every vertical scanning period. As a result, the combination of pixels combined by the output unit 11d is shifted by one pixel in each vertical scanning period to perform pseudo interlaced scanning, and deterioration of resolution due to pixel combination is suppressed.

As described above, the discharging operation of the output section 11d is intermittently performed so that the sample-hold circuit 14 is connected to the horizontal transfer section 11h.
The image signal Y1 (t) containing the image information corresponding to the information charge amount for each pixel and the image information corresponding to the information charge amount obtained by combining a plurality of pixels can be obtained by operating in accordance with the transfer operation of it can. For example, when the information charges for two pixels are combined and taken out, the image signal Y1 (t) corresponds to the period of the voltage value corresponding to the information charge amount for one pixel and the information charge amount for two pixels. The period of the applied voltage value is repeated. Therefore, in the process of signal processing of the image signal Y1 (t), the information when the information charge of each pixel is independently read and the information when the plurality of pixels are combined and read are selected as needed. It becomes possible to handle.

FIG. 3 shows the storage unit 11 of the image sensor 11.
It is a top view which shows an example of the structure of the connection part of s and the horizontal transfer part 11h. Multiple vertical transfer channels 21a, 21b
Are separated by the separation region 22 and extend parallel to each other in the vertical direction (transfer direction). Vertical transfer channel 21
Each of the vertical transfer channels 21a, 21a,
The horizontal transfer channel 23 continuous to 21b
It is divided by 4 and extends in the horizontal direction. On the plurality of vertical transfer channels 21a and 21b, a plurality of transfer electrodes 25a to 25d having a two-layer structure extend in the horizontal direction so as to be common to each column, and are parallel to each other in an insulated state. Will be placed. Four-phase vertical clocks φv1 to φv4 are applied to these transfer electrodes 25a to 25d. On the horizontal transfer channel 23, a plurality of transfer electrodes 26a and 26b having a two-layer structure are arranged extending in the vertical direction. These transfer electrodes 26a and 26b are commonly connected to two adjacent electrodes, and are supplied with two-phase horizontal clocks φh1 and φh2. Of the transfer electrodes 26a and 26b, the lower layer side covers the connection portion between the vertical transfer channels 21a and 21b and the horizontal transfer channel 23 so as to cover the vertical transfer channel 2a.
It extends to the side of 1a and 21b. Further, the connection portion between the vertical transfer channels 21a in the odd columns and the horizontal transfer channels 23 is formed longer than that in the even columns by one bit, and the connection electrode is also covered with the transfer electrodes 26a.

Auxiliary transfer electrodes 27a to 27d having a two-layer structure are formed on the output side (horizontal transfer channel 23 side) of the vertical transfer channels 21a and 21b. The auxiliary transfer electrodes 27b and 27d on the lower layer side are provided only on the vertical transfer channels 21b in even columns. In addition, the auxiliary transfer electrodes 27a and 27c on the upper layer side include all the vertical transfer channels 21a and 27a.
21b, but overlaps the transfer electrodes 26a on the vertical transfer channels 21a in the odd columns, and acts only on the vertical transfer channels 21b in the even columns. Then, four-phase auxiliary clocks φu1 to φu4 are applied to these auxiliary transfer electrodes 27a to 27d. As a result, the auxiliary transfer electrodes 27a to 27d form one bit of auxiliary bits at the output ends of the vertical transfer channels 21b in the even columns,
In the process of transferring the information charges from the storage unit 11s to the horizontal transfer unit 11h, the information charges for one pixel can be temporarily stored in the vertical transfer channels 21b in the even columns.

6 and 7 are timing charts for explaining the operation of the image sensor 11 shown in FIG. 3. FIG. 6 shows the operation in the horizontal scanning cycle and FIG. 7 shows the operation in the horizontal clock cycle. This figure shows a case where the output portion 11d of the image sensor 11 synthesizes and reads out the information charges of two pixels. Although the vertical clock φv and the auxiliary clock φu are actually four phases and the horizontal clock φh is two phases, only the representative clock is shown in the drawing.

As shown in FIG. 6, the vertical clock φv is
Transfer electrodes 25a to 25d in a cycle according to the horizontal synchronization signal HT
Clocking the vertical transfer channels 21a, 21b
The information charges therein are vertically transferred pixel by pixel in one horizontal scanning period. The auxiliary clock φu is 1 / of the vertical clock φv.
The auxiliary transfer electrodes 27a to 27d are clocked at a cycle of ½ of the horizontal synchronizing signal HT. The auxiliary transfer electrodes 27a to 27d effectively act only on the vertical transfer channels 21b in the even columns, so that the information charges in the vertical transfer channels 21b in the even columns are output by two pixels in one horizontal scanning period at the output end. Vertically. At this time, the transfer electrodes 25a to 25d are transferred to the auxiliary transfer electrodes 27a to 27d.
Since only the information charge of one pixel is transferred to the 7d portion in one horizontal scanning period, the auxiliary transfer electrodes 27a to 27d are actually used.
In the portion, idle transfer is performed every other pixel. Therefore, in the odd-numbered vertical transfer channels 21a and the even-numbered vertical transfer channels 21b, the information charge of one pixel is transferred to the horizontal transfer channel 23 at a timing shifted by a 1/2 vertical scanning period.

The horizontal clock φh is activated in response to the vertical clock φv and the auxiliary clock φu, and the transfer electrode 26a,
26b is clocked at a period sufficiently shorter than the horizontal scanning period. The period of the horizontal clock φh is set so that all the information charges in the horizontal transfer channel 23 can be transferred and output in a half period of the horizontal scanning period and a constant blanking period can be secured. As a result, in the first half period of each horizontal scanning period, the vertical transfer channels 21 of the odd columns are
The information charges from a are transferred and output, and the information charges from the vertical transfer channels 21b of even columns are transferred and output in the latter half period.

As shown in FIG. 7, the reset clock φr0
Discharges the information charges accumulated in the output section 11d of the image sensor 11 in a cycle that is synchronized with the horizontal clock φh and matches the horizontal transfer cycle. Divided reset clock φr1
Is generated by dividing the reset clock φr0 by half, and the image sensor 11 has a cycle twice as long as the horizontal transfer cycle.
The information charges accumulated in the output section 11d of the above are discharged. As a result, in the output section of the image sensor 11, information charges for two pixels are accumulated at the same time, and the output image signal Y0 (t) is output after the reset period designated by the frequency division reset clock φr1. The signal level is changed in two steps.

The sampling clock φs has the same cycle as the reset clock φr0 and has sampling timing immediately before the reset period of the reset clock φr0. As a result, the signal level immediately before the reset timing of the image signal Y0 (t) is sampled in the sample hold circuit 14 and the image signal Y1 (t is maintained for one clock period (one cycle of the horizontal clock φh). ) Is generated. At this time, since the reset operation of the output unit 11d is intermittent, the signal level of the image signal Y0 (t) corresponds to the voltage value corresponding to the information charge amount of one pixel and the information charge amount of two pixels. Repeat with the voltage value you want. For example,
When the odd-numbered pixels are read out independently, the signal level becomes a voltage value according to the information charge amount y (2m-1) of the odd-numbered pixels. Then, when the even-numbered pixel is combined with the preceding odd-numbered pixel and read out, the signal level is the information charge amount y (2m) of the even-numbered pixel to the information charge amount y (of the odd-numbered pixel. The voltage value follows the charge amount y (2m-1) + y (2m) obtained by adding 2m-1). Therefore, in the image signal Y1 (t), a period representing the information charge amount of one pixel and a period representing the information charge amount of two pixels are alternately repeated.

In the image sensor 11 described above, when a mosaic type color filter as shown in FIG. 2 is mounted, each color component becomes continuous every ½ of each horizontal scanning period. For example, in the horizontal scanning period corresponding to the odd-numbered light-receiving pixels in which the W component and the G component are alternately associated, as shown in FIG. 8, the W component is continuous in the first half period and the G component is continuous in the second half period. . Further, in the horizontal scanning period corresponding to the light receiving pixels in the even rows in which the Cy component and the Ye component are alternately associated, the Cy component is continuous in the first half period and the Ye component is continuous in the second half period. As a result, even if the information charges of two pixels are combined in the horizontal direction, different color components do not mix with each other, and appropriate processing can be performed by the signal processing circuit.

FIG. 4 is a block diagram showing the configuration of the input stage of the signal processing circuit for subjecting the image signal Y1 (t) output from the sample hold circuit 14 to signal processing. In this figure, according to FIG. 6 and FIG.
The case where the signal processing is performed on the image signal Y1 (t) read out by combining the information charges of the two pixels in the first output unit 11d is shown.

The signal processing circuit includes an A / D conversion circuit 31, latch circuits 32 and 33, a subtraction circuit 34, and a selection circuit 35. The signal processing circuit further includes a color signal processing system that performs white balance adjustment, balanced modulation, and the like, and a luminance signal processing system that performs two-dimensional filter processing, contour correction, and the like. A
The / D conversion circuit 31 captures the image signal Y1 (t) in synchronization with the sample hold circuit 14 and generates image data D0 (n) corresponding to each light receiving pixel of the image sensor 11. In this image data D0 (n), the data corresponding to the information charge amount for one pixel and the data corresponding to the information charge amount for two pixels are repeated as in the image signal Y1 (t) shown in FIG. .
For example, when the 2m-1 (odd) th pixel is read out independently, the image data D0 (2m-1) is the data d (2m-1) representing the information charge amount y (2m-1) of the 2m-1th pixel. -1).
Then, when the 2m (even number) pixel is combined with the previous pixel and read, the image data D0 (2m) is 2m.
Charge amount y (2m-1) + y (2m) obtained by adding the information charge amount y (2m) of the 2nd pixel to the information charge amount y (2m-1) of the 2nd pixel
Is data d (2m-1) + d (2m).

The first latch 32 responds to the first latch pulse LT1 and outputs the image data D0 (n) every other data.
The data charges for two pixels are latched at the timing of output, and the data d (2m-1) + d (2
Image data D1 (n) in which m) are continuous is generated. The second latch 33 responds to the second latch pulse LT2, latches the image data D0 (n) every other data at the timing at which the information charge for one pixel is independently output, and the second latch 33 latches for one pixel. Image data D2 in which data d (2m) representing the information charge amount of
generates (n). Image data D1 (n) and image data D2
In (n), data d (2m-1) + d (2m) and data d
(2m-1) continues every two clocks. However, the timings of the image data D1 (n) and the image data D2 (n) are shifted by one clock period.

The subtraction circuit 34 subtracts the image data D2 (n) output from the second latch circuit 33 from the image data D1 (n) output from the first latch circuit 32. In this subtraction processing, the image data D1 (n) representing the information charge amount of two pixels to the image data D2 representing the information charge amount of one pixel.
Since (n) is subtracted, the information charge amount before the information charges are combined is calculated. The selection circuit 35 selects either the subtraction result of the arithmetic circuit 34 or the image data D2 (n) in response to the selection pulse SEL, and outputs it as image data D3 (n) representing the information charge amount for each pixel. To do. That is, during the period in which the data d (2m-1) indicating the information charge amount of one pixel is input, the image data D2 (n) side is selected and the data d (2m-1) indicating the charge amount of two pixels is selected. During the period when + d (2m) is input, the subtraction circuit 24 side is selected. Therefore, the image data D3 representing only the information charge amount of each light receiving pixel before being combined by the output section 11d of the image sensor 11
(n) is generated.

The image data D1 (n) indicating the information charge amount for every two pixels output from the first latch 32 is supplied to a signal processing system for obtaining a color signal and output from the selection circuit 35. The image data D3 (n) indicating the information charge amount for each pixel is
It is supplied to a signal processing system for obtaining a luminance signal. In the generation processing of the color signal, the number of data has little influence on the resolution of the reproduction screen. Therefore, even if the number of data is 1/2, the image data D3 representing the information charge amount of two pixels having a sufficient level. (n) is used. On the other hand, in the generation processing of the luminance signal, since the number of data directly affects the resolution of the reproduction screen, the image data D1 (n) with the secured number of data is used.

By the way, when the image signal Y0 (t) is extracted by synthesizing the information charges of two pixels, the deterioration of the resolution in the horizontal direction cannot be avoided. Therefore, it is conceivable that the combination of two pixels that combine the information charges is inverted every vertical scanning period to perform pseudo interlaced driving to minimize deterioration of resolution. FIG. 9 is a timing chart for explaining the operation when the two pixels that combine the information charges are inverted between the odd-numbered vertical scanning period (odd frame) and the even-numbered vertical scanning period (even frame).

The frequency-divided reset clock φr1 is set such that the frequency division timing between the odd-numbered frame and the even-numbered frame, that is, the pulse thinning-out timing is shifted by one clock period. Therefore, the divided reset clock φr1 has a period twice that of the reset clock φr0, and has a phase difference of ½ period between the odd frame and the even frame.
The image signal Y is generated by such a divided reset clock φr1.
If 1 (t) is obtained, the combination of the two pixels synthesized by the output unit 11d of the image sensor 11 is inverted between the odd frame and the even frame. The inversion of the combination of the two pixels that combine the information charges may be performed in units of vertical scanning periods or in units of horizontal scanning periods. Further, by combining the combination inversion in the vertical scanning period unit and the combination inversion in the horizontal scanning period unit, a further effect can be expected.

In the above embodiment, the case where the information charges are combined in units of two pixels has been illustrated, but the information charges of three pixels or more may be combined. In this case, it can be easily dealt with by changing the division ratio when obtaining the divided reset clock φr1 and the divided sampling clock φs1 from the reset clock φr0 and the sampling clock φs0.

[0039]

According to the present invention, even in an image sensor equipped with a mosaic type color filter, the information charges of a plurality of pixels can be combined and taken out in the horizontal direction. At this time, since the color components are not mixed, the signal processing for the output image signal is performed accurately. Further, a color signal that does not easily affect the resolution of the reproduction screen is obtained from the output in which the information charges of a plurality of pixels are combined, and a luminance signal that directly affects the resolution of the reproduction screen is read out independently of the information charges of one pixel. I'm trying to get from the output. Therefore, in color imaging, it is possible to ensure color reproducibility on the reproduction screen without lowering the resolution.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a solid-state imaging device of the present invention.

FIG. 2 is a plan view showing the structure of a mosaic type color filter.

FIG. 3 is a plan view showing an example of a structure of a connecting portion between a storage unit and a horizontal transfer unit of the image sensor.

FIG. 4 is a block diagram showing a part of a signal processing circuit used in the image sensor of the present invention.

5 is a timing diagram illustrating an operation of the signal processing circuit of FIG.

FIG. 6 is a timing diagram illustrating a first operation of the solid-state imaging device of the present invention.

FIG. 7 is a timing diagram illustrating a second operation of the solid-state imaging device of the present invention.

FIG. 8 is a timing diagram showing an arrangement of color components of an image signal output from an image sensor equipped with a mosaic type color filter.

FIG. 9 is a timing diagram illustrating a third operation of the solid-state imaging device of the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional solid-state imaging device.

FIG. 11 is a timing diagram illustrating a first operation of the conventional solid-state imaging device.

FIG. 12 is a timing diagram illustrating a second operation of the conventional solid-state imaging device.

[Explanation of symbols]

1, 11 image sensor 1i, 11i Imaging unit 1s, 11s storage unit 1h, 11h Horizontal transfer section 1d, 11d output section 2, 12 drive circuit 2f, 12f frame clock generator 2v, 12v vertical clock generator 2h, 12h Horizontal clock generator 2r, 12r Reset clock generator 2s, 12s sampling clock generator 3, 13 Timing control circuit 4,14 Sample and hold circuit 5, 15 frequency divider 12u Auxiliary clock generator 21a, 21b Vertical transfer channel 22, 24 channel separation area 23 horizontal transfer channels 25a to 25d, 26a, 26b Transfer electrodes 27a to 27d auxiliary electrodes 31 A / D conversion circuit 32, 33 Latch circuit 34 Subtraction circuit 35 selection circuit

Claims (3)

(57) [Claims] 1. A plurality of light receiving pixels arranged in a matrix in association with each segment of a color filter are coupled to a plurality of vertical transfer units for each column, and respective outputs of the plurality of vertical transfer units are horizontally transferred. An image sensor that is coupled to each bit of the horizontal transfer unit and outputs the amount of output charge of the horizontal transfer unit after being converted into a voltage value at the output unit, and the information charges generated in the plurality of light receiving pixels. To the horizontal transfer unit for each horizontal line from the plurality of vertical transfer units, and further to the output unit in units of one pixel from the horizontal transfer unit and accumulated in the output unit. A drive circuit for discharging and resetting the information charges in synchronization with the transfer operation of the horizontal transfer section, and a voltage value according to the amount of accumulated charge output from the output section for the transfer operation of the horizontal transfer section. Retrieve in sync A detection circuit, and the drive circuit transfers the information charges stored in the plurality of vertical transfer units to the horizontal transfer unit for the information charges of one horizontal line and the horizontal transfer unit. To the output section, the series of transfer operations are alternately performed in the odd-numbered column and the even-numbered column, and the reset operation cycle of the output section is set to an integral multiple of the transfer operation cycle of the horizontal transfer section. Then, the information charge for a plurality of pixels is accumulated in the output section, and the detection circuit samples the output of the output section in synchronization with the transfer operation of the horizontal transfer section to correspond to the information charge amount of one pixel. And an output corresponding to the information charges of a plurality of pixels. 2. A color signal is generated based on a final potential immediately before the reset operation, which is detected when information charges of a plurality of pixels are accumulated in the output section among detection potentials of the detection circuit, Information charges for one pixel are accumulated in the output section
Of the electric potential and the information charges of the plurality of pixels are output
Output of the output unit in the process of being sequentially accumulated in the unit in pixel units
Generated from the difference in each potential when the potential changes stepwise
The solid-state imaging device according to claim 1, further comprising a signal processing circuit that generates a luminance signal based on a potential corresponding to an information charge of each light receiving pixel . 3. The driving circuit is provided for each vertical scanning period of the image sensor which is vertically and horizontally scanned.
The solid-state imaging device according to claim 1, wherein the reset operation timing of the output section is shifted by one cycle of the transfer operation of the horizontal transfer section for each horizontal scanning period .