JP3486031B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip and a circuit wiring board are flip-chip mounted, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been highly integrated, and along with this, there is a demand for higher packaging technology. Wire-bonding technology and TAB technology are typical examples of high-density mounting technology for semiconductor devices. In recent years, the flip-chip mounting technology has been the highest-density mounting technology for high-density mounting of semiconductor devices such as computer equipment. It is widely used as a technology for

This flip chip mounting technology is disclosed in US Pat. No. 3,401,126 and US Pat. No. 3,429,040.
It has become a widely known technique since the publication of the publication.
In the flip chip mounting technique, as shown in FIG. 8, a bump electrode 83 having a protrusion shape is formed on a bonding pad 82 of a semiconductor chip 81, and the bonding pad 82 of the semiconductor chip 81 and a circuit are formed through the bump electrode 83. This is a technique for electrically and mechanically interconnecting the connection pads 85 of the wiring board 84. In the figure, 86 is a passivation film, 87 is a barrier metal, and 88 is a solder resist.

In the flip-chip mounting technology, since the coefficient of thermal expansion of the semiconductor chip and the coefficient of thermal expansion of the circuit wiring board are generally different from each other, the temperature difference from the external temperature atmosphere or the heat generated during the operation of the semiconductor chip. Is transmitted to the circuit wiring board through the bump electrode, so that the semiconductor chip and the circuit wiring board are displaced. The generated displacement causes stress strain in the bump electrode connecting the semiconductor chip and the circuit wiring board.

Reliability life is described by IBM J. Res. De
velop. , 13; 251 (1969), Nf = Cf ^1/3 γ _max ⁻² · exp (142
8 / Tmax), which is obtained by the cycle life formula (C; constant, f; frequency, Tmax; maximum temperature). Therefore, from the above cycle life formula, the maximum shear strain γ generated in the bump electrode portion is obtained. Reliable life can be improved by reducing _max .

Further, the maximum shear strain γ _max generated in the bump electrode shown in the reliability life formula is expressed by the following formula.

Γ _max = {1 / (Dmin / 2) ^{2 / β} }
(V / πh ^{1 + β} ) ^{1 + β} · d · ΔT · Δα (Dmin; minimum bump diameter, β; material constant, V; solder volume, h; solder height, Δα; thermal expansion coefficient difference, ΔT; Temperature difference, d; distance from the center of the semiconductor chip to the center of the bump electrode) Therefore, in order to improve the reliability of flip-chip mounting, the distance from the center point of the semiconductor chip to the center point of the bump electrode may be reduced, or Measures such as reducing the difference in the coefficient of thermal expansion between the chip and the circuit wiring board, improving the heat dissipation so that the temperature difference does not increase, or making the structure of the bump electrode strong against stress strain are available. It is used.

In addition, when the semiconductor chip and the circuit wiring board are significantly different in thermal expansion coefficient from each other, as in the case of flip chip mounting using an organic resin substrate as a circuit wiring board which has been frequently performed in recent years, As shown in FIG. 9, resin 89 is injected into the gap between the semiconductor chip 81 and the circuit wiring board 84 to strengthen the flip-chip mounting structure, thereby improving reliability.

Such a technique is disclosed in, for example, Japanese Patent Laid-Open No. 57-57.
208149, JP-A-58-10841 and JP-A-5
Although disclosed in Japanese Patent Application Laid-Open No. 8-103143, in the case of these techniques, it is not possible to sufficiently prevent the connection portion from being broken by the bump electrode because the resin property of sealing is not appropriate.

Further, Japanese Patent Publication No. 4-51057 and Japanese Patent Laid-Open No. 6-510
In order to solve such a problem, JP-A-3-316447 considers the shear modulus of the sealing resin in consideration of the shear modulus of the solder to be about 300 kg / mm ² , or 10 k.
g / mm ^{2 to} 900 kg / mm ² , and the coefficient of thermal expansion is made equal to that of the solder or smaller than that of the solder (20
X10 ^{-6 to} 28x10 ^-6 / ° C.) To reduce the amount of shear deformation of the solder and prevent breakage due to shear fatigue at the connection portion by the bump electrode.

Further, in Japanese Patent Application Laid-Open No. 4-219944, even if an organic material substrate is used by using a curable resin composed of a thermosetting binder and a filler as a sealing material, It is disclosed that highly reliable flip chip mounting can be realized.

As a method of sealing the resin in the gap between the semiconductor chip and the circuit wiring board, for example, Japanese Patent Laid-Open No.
As disclosed in Japanese Patent No. 7447, Japanese Patent Application Laid-Open No. 2-234447, and Japanese Patent Application Laid-Open No. 62-132331,
A method in which a resin is applied in advance on the surface of the semiconductor chip or on the place where the semiconductor chip is mounted on the circuit wiring board, and then the semiconductor chip is connected and bonded to the circuit wiring board, or in JP-A-60-147140 and JP-A-3-18435. As disclosed in the publication, a method in which a semiconductor chip is flip-chip mounted on a circuit wiring board and then a resin is sealed in a gap between the semiconductor chip and the circuit wiring board and a peripheral portion of the semiconductor chip by utilizing a capillary phenomenon It has been known.

However, in such a resin sealing method,
If the resin intervenes in the gap between the bump electrode of the semiconductor chip and the electrode pad of the circuit wiring board and connection failure occurs, or if the resin viscosity is not an appropriate value for the gap dimension, the resin to be sealed will be the semiconductor chip. Since it is not formed uniformly in the entire gap with the circuit wiring board, when a temperature cycle is applied,
There was also the problem of reduced reliability.

Further, in Japanese Patent Laid-Open No. 64-72537, as shown in FIG. 10, a hole is made at a predetermined position of the insulating resin film 90, and a predetermined amount of paste solder is used as the bump electrode 83 in this hole. Print and hold semiconductor chip 81
It is disclosed that the stress strain of the bump electrode portion is alleviated by flip-chip mounting of the above. Further, Japanese Patent Laid-Open No. 59-202643 discloses a method shown in FIG.
As shown in FIG. 7, a sealing resin film 90a having bump electrodes 82 provided on the bonding pads 82 of the semiconductor chip 81 is used, and the bonding pads 82 of the semiconductor chip 81 and the bump electrodes 82 of the sealing-like resin film 90a are used. And the electrode pad 85 of the circuit wiring board 84 are aligned and then thermocompression bonded,
It is disclosed that the semiconductor chip 81 is attached to the circuit wiring board 84.

On the other hand, the flip-chip mounting technique has conventionally been required to have an inspection technique in a bare chip state. Many tests and developments are currently being conducted on this test as KGD (Known Good Die).

For example, as shown in FIG. 12, there has been proposed a method of forming an inspection wiring 91 on a semiconductor chip 81 or a circuit wiring board 84 and inspecting it. In particular,
As disclosed in Japanese Patent Laid-Open No. 61-23332, after a probe wiring (inspection wiring) is arranged on a circuit wiring board on which a semiconductor chip is mounted, and a predetermined bump electrode is short-circuited to perform inspection. A method of opening a short portion by performing wet back is known.

Further, JP-A-62-24335, JP-A-63-31129, and JP-A-3-125448 disclose methods for inspecting semiconductor chips in a wafer state.

Further, TCP (Tape Carrier)
In the case of r package) and the like, a method of putting a semiconductor chip mounted on a TAB tape in a socket and inspecting it is also used.

However, according to these inspection methods, not only is it difficult to handle the bare chip, but the inspection wiring used for the inspection after assembly remains on the semiconductor chip, so that impurities enter from the remaining inspection wiring. Then, there was a problem that reliability was lowered.

[0020]

As described above, the conventional flip-chip mounting technique requires the inspection technique in the bare chip state, but in the conventional inspection method, the inspection wiring remains on the semiconductor chip. However, there is a problem that impurities enter from the remaining inspection wiring and the reliability is lowered.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a method for manufacturing a flip-chip mounted semiconductor device capable of improving reliability.

[0022]

In particular, the present invention (claims 1 to 5 ) has an object to improve the reliability of a semiconductor device mounted by flip chip mounting by improving a method for inspecting a semiconductor chip.

[0024]

[0025]

[0026]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention (claim 1).
In order to connect the semiconductor chip on which the bump electrodes are formed and the thermosetting resin sheet on the surface of which the wiring having the same pattern as the predetermined pattern is formed, the thermosetting resin on the wiring is connected. Forming an opening in the conductive resin sheet, connecting the bump electrode and the wiring through the opening, and using the wiring as an inspection electrode to inspect the semiconductor chip; By dissolving or solid-dissolving the wiring in the bump electrode,
While removing the wiring , reduce the volume of the bump electrode.
The method is characterized by including the step of increasing the number and the step of electrically and mechanically connecting the circuit wiring of the circuit wiring substrate on which the circuit wiring having the predetermined pattern is formed and the bump electrode.

A method of manufacturing a semiconductor device according to the present invention (claim 2 ) is a method of manufacturing the semiconductor device (claim 2 ).
1 ), a plurality of semiconductor chips are connected to the thermosetting resin sheet, the thermosetting resin sheet is cut at the outer peripheral portion of each semiconductor chip, and bump electrodes of each semiconductor chip are provided with different circuit wirings. It is characterized in that it is electrically and mechanically connected to the circuit wiring of the substrate.

On the contrary, after connecting the bump electrodes of each semiconductor chip to the circuit wirings of different circuit wiring boards,
The thermosetting resin sheet may be cut at the outer peripheral portion of each semiconductor chip.

A method of manufacturing a semiconductor device according to the present invention (claim 3 ) is a method of manufacturing the semiconductor device (claim 3 ).
1 ) The circuit wiring and the bump electrode according to claim 2 ).
In the state where the semiconductor chip is connected to the thermosetting resin sheet after the step of electrically and mechanically connecting the poles, the thermosetting resin sheet is heated to form a gap between the semiconductor chip and the circuit wiring board. Is sealed with a thermosetting resin.

A method of manufacturing a semiconductor device according to the present invention (claim 4 ) is a method of manufacturing the semiconductor device (claim 4 ).
In claim 1 , claim 2 and claim 3 ), the inspection is performed after electrically connecting the bump electrode and the circuit wiring.

The method for manufacturing a semiconductor device according to the present invention (claim 5) is the same as the method for manufacturing a semiconductor device (claim 1, claim 2, claim 3, claim 4). The ratio of the total area of the resin sheet to the area of the thermosetting resin sheet in the gap between the semiconductor chip and the circuit wiring board is 1 or more and 1.5 or less.

In the present invention, the bump electrodes are lead, tin,
It is preferable that the main component is at least one of indium, antimony, and bismuth.

Further, the wiring formed on the thermosetting resin member and the thermosetting resin sheet contains at least one of gold, silver, copper, lead, tin, indium, antimony and bismuth as a main component. It is preferable.

The wiring formed on the thermosetting resin sheet is preferably protected by a sheet made of the same resin as the constituent resin of the thermosetting resin sheet.

[Operation] As described above, the reliability life of the bump electrode is Nf = Cf ^1/3 γ _max ⁻² · exp (142
8 / Tmax), γ _max = {1 / (Dmin /
2) ^{2 / β} } (V / πh ^{1 + β} ) ^{1 + β} · d · ΔT · Δα.

[0036]

[0037]

Further, in the present invention (claims 1 to 5 ), the wiring having at least a part of the same pattern as the circuit wiring formed on the thermosetting resin sheet is used as the inspection electrode, and Inspect semiconductor chips. Since such wiring is usually larger than the bump electrode, it is possible to easily and accurately apply a probe for inspection, which allows the semiconductor chip to be easily and accurately inspected. Therefore, it becomes possible to manufacture a semiconductor device in which only good semiconductor chips are reliably mounted, and reliability can be improved.

According to the present invention (claim 3 ), when the bump electrode is melted, the wiring formed on the thermosetting resin sheet is dissolved or solid-dissolved in the bump electrode,
Since the wiring is substantially removed after the inspection, it is possible to prevent a short circuit between the wiring due to the remaining wiring and a corrosion due to the intrusion of impurities.

Furthermore, since the volume of the bump electrode is increased by melting or solid-dissolving the wiring in the bump electrode, the reliability life is extended, and a highly reliable flip-chip mounted semiconductor device can be easily manufactured. Like

For this purpose, as the wiring, one containing at least one of gold, silver, copper, lead, tin, indium, antimony and bismuth as a main component is used, and as the bump electrode, lead is used. It is preferable to use a material containing at least one of tin, indium, antimony, and bismuth as a main component.

According to the present invention (Claim 3 ), the thermosetting resin sheet is heated in a state where the semiconductor chip is connected to the thermosetting resin sheet, and the gap between the semiconductor chip and the circuit wiring board is provided. Since it is sealed with a thermosetting resin,
It is possible to prevent the thermosetting resin from remaining in the gaps between the bump electrodes and the circuit arrangement, or to prevent the reliability from being lowered due to uneven formation.

According to the present invention (claim 4 ), the electrode bumps are aligned and in contact with the circuit wiring through the wiring formed on the thermosetting resin sheet, that is, mechanically connected. Not connected but electrically connected,
By performing the inspection, not the inspection at the semiconductor chip level but the inspection at the semiconductor device level in which the semiconductor chip and the circuit wiring board are integrated can be performed.

Further, according to the present invention (claim 4 ), since the semiconductor chip and the circuit wiring board are not mechanically connected, the semiconductor chip can be replaced when a defect is found by inspection. It will be easy to do.

[0045]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments (embodiments) of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 and 2 are process sectional views showing a method of manufacturing a flip-chip mounted semiconductor device according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a semiconductor chip 1 having a bump electrode 3 formed on a bonding pad 2 and a passivation film 4 formed on a portion other than a portion of the bonding pad 2, and wiring on the back surface. The pattern 7 is formed, the through hole 8 is formed on the wiring pattern 7,
A thermosetting resin sheet 6 for mounting and holding the semiconductor chip 1 is prepared.

A Cu / Ti barrier metal 5 is provided between the bonding pad 2 and the bump electrode 3. The passivation film 4 is made of PSG (phosphorus / silica /
It is formed of glass) and SiN (silicon nitride).

The bump electrode 3 is formed, for example, in US Pat. No. 34.
It is formed using a vapor deposition method or an electroplating method which is a known technique disclosed in JP-A-58925, JP-A-47-24765 or JP-A-2-232928.

Solder is generally used as the material of the bump electrode 3, but in the case of the present embodiment, it is not always necessary to use solder, and the point is that the wiring pattern on the back surface of the thermosetting resin sheet 6 is essential. Any metal that dissolves or solid-dissolves 7 may be used.

In this embodiment, a Pb / Sn = 40/60 alloy is used as the material of the bump electrode 3. Further, in the present embodiment, along with the periphery of the semiconductor chip 1,
256 bump electrodes 3 having a diameter of 100 μm were formed with an accuracy of 75 μm ± 5 μm in height. The size of the semiconductor chip 1 is 10 mm × 10 mm.

On the other hand, as the thermosetting resin sheet 6 for mounting and holding the semiconductor chip 1, bisphenol epoxy,
Containing 45 wt% of imidazole curing catalyst, acid anhydride curing agent and spherical quartz filler in weight ratio, film thickness is 50μ
An m-thick epoxy resin sheet was used.

The wiring pattern 7 on the back surface of the thermosetting resin sheet 6 is the same as the circuit wiring pattern.
The u thin film is formed in a range of 12 mm × 12 mm.
The circuit wiring pattern may be partly the same pattern.

Although the through hole 8 is provided on the wiring pattern 7 as described above, more specifically, the through hole 8 is formed at a position corresponding to the bump electrode 3 of the semiconductor chip 1 and The diameter is 110 μm.

There are various methods for forming the wiring pattern 7, but in the present embodiment, the sputtering method is used.
After forming the u thin film, a method of etching away unnecessary portions was used. The wiring pattern 7 may be formed by any method as long as it can form a circuit wiring pattern on the thermosetting resin sheet 6, such as a printing method.

Further, although Au is used as the material of the wiring pattern 7 in the present embodiment, it is not limited to this, and the point is Cu, Ag, Pb, Sn, In, Sb, B.
Any metal, such as i, which can be melted or solid-dissolved in solder may be used, and the same material as the bump electrode 3 may be used. That is, the material of the bump electrode 3 and the material of the wiring pattern 7 may be any material as long as the wiring pattern 7 is melted or solid-dissolved in the bump electrode 3.

The thermosetting resin sheet 6 is not particularly limited, and for example, 100 parts by weight of a cresol novolac type epoxy resin (ECON-195XL; manufactured by Sumitomo Chemical Co., Ltd.) and 54 parts by weight of a phenol resin as a curing agent. 100 parts by weight of fused silica as a filler, 0.5 parts by weight of benzylmethylamine as a catalyst, 3 parts by weight of carbon black as another additive, and 3 parts by weight of a silane coupling agent are pulverized, mixed and melted, and an epoxy resin melt is prepared. It is also possible to use a sheet having a size of 12 mm × 12 mm by rolling.

Next, as shown in FIG. 1B, a bump electrode 3 of the semiconductor chip 1 and a thermosetting resin sheet are used by using a flip chip bonder having a half mirror, which is a known technique, for alignment. The position of the through hole 6 is aligned with that of the through hole 8.

Next, as shown in FIG. 1C, the thermosetting resin sheet 6 is heat-cured to mount and hold the semiconductor chip 1 on the thermosetting resin sheet 6. In addition, in the case of the present embodiment, the wiring pattern 7 is formed on the back surface of the thermosetting resin sheet 6.
Since the wiring pattern 7 is formed, the wiring pattern 7 may be damaged during transportation, resulting in a defect.

Therefore, for example, regarding a semiconductor device for an application requiring transportation, as shown in FIG.
A protective resin sheet 9 made of the same material as the thermosetting resin sheet 6 may be provided on the thermosetting resin sheet 6 to protect the wiring pattern 7. As a result, it is possible to reduce defects due to damage to the wiring pattern 7 to 0%.

In this case, if a metal such as Au or Cu that is harder than solder is used as the material for the bump electrode 3, the bump electrode 3 can be easily protected by the protective resin sheet 9.
Can be penetrated and connected to the connection electrode of the circuit wiring board.

Next, as shown in FIG. 2A, the wiring pattern 7 on the back surface of the thermosetting resin sheet 6 is subjected to an electrical inspection of the semiconductor chip 1 by using a well-known probing technique.

In this inspection, as shown in FIG.
The probe needle 10 made of Be is generally applied to the wiring pattern 7, but the inspection method is not limited to this.

For example, as shown in FIG. 3, an inspection board 12 provided with a protrusion inspection electrode 11 composed of a bump having a protrusion shape is prepared, and the protrusion inspection electrode 11 and the wiring pattern 7 are aligned with each other. It may be performed by connecting the projection inspection electrode 11 and the wiring pattern 7. It is also possible to sandwich the thermosetting resin sheet 6 on which the semiconductor chip 1 is mounted in a socket for inspection.

Next, as shown in FIG. 2 (b), the thermosetting resin sheet 6 having the semiconductor chip 1 mounted thereon is passed through a reflow oven heated to 250 ° C. having a nitrogen atmosphere, whereby the bump electrode 3 is formed. Is reflowed to dissolve and remove the wiring pattern 7 formed on the back surface of the thermosetting resin sheet 6 in the bump electrode 3.

At this time, as shown in FIG. 7B, a part of the wiring pattern 7 remains, but it does not remain as a wiring pattern, so that the wiring pattern 7 is substantially removed. Further, the volume of the bump electrode 3 is substantially increased by the remaining wiring pattern 7 and the dissolved wiring pattern 7.

Next, as shown in FIG. 2C, for example, the blade 13 is pressed onto the thermosetting resin sheet 6 so that the semiconductor chip 1 is centered at 12 mm × 12 mm.
The thermosetting resin sheet 6 is cut with the dimension of. The cutting method and the device therefor are not limited to those of the present embodiment.

Next, as shown in FIG. 2D, a circuit wiring board 14 is prepared. The circuit wiring board 14 is formed by using a known method such as, for example, US Pat. No. 4,811,082 or an ordinary laminated glass epoxy board.

Although the material and structure of the circuit wiring board 14 are not particularly limited, in the present embodiment, the circuit wiring board 14 is an SLC (Surface) which is a printed board in which an insulating layer and a conductor layer are built up on a glass epoxy substrate.
A Laminar Circuit substrate will be used.

The semiconductor chip 1 is provided on the circuit wiring board 14.
A connection electrode 15 made of Cu corresponding to the bump electrode 3 is provided. The circuit wiring board 14 is a solder resist 1
It is covered by 6. However, openings of 110 μmφ and 100 μm square are provided in the connection electrode 15, and the connection electrode 15 is exposed in a rectangular shape.

Next, as shown in FIG. 1D, the bump electrodes 3 of the semiconductor chip 1 and the circuit wiring board 14 are connected using a known flip chip bonder having a half mirror for alignment. After the alignment with the electrode 15, the bump electrode 3 and the connection electrode 15 are electrically and
The semiconductor chip 1 is mounted on the circuit wiring board 14 by mechanical contact.

At this time, the circuit wiring board 14 is held on a stage having a heating mechanism (not shown), and the bump electrode 3 is held.
It is preheated to 200 ° C., which is higher than the melting point of the solder (Pb / Sn = 40/60) which is the material of the above, in a nitrogen atmosphere.

Further, in the state where the semiconductor chip 1 and the circuit wiring board 14 are in contact with each other as described above, the collet (not shown) holding the semiconductor chip 1 is heated to the same temperature of 200 ° C. as the stage on which the circuit wiring board 14 is mounted. By heating in a nitrogen atmosphere to melt the solder forming the bump electrode 3, the bump electrode 3 and the connection electrode 15 are temporarily connected electrically and mechanically.

Next, the bump electrode 3 and the connecting electrode 15 are electrically and mechanically passed by passing through the circuit wiring substrate 14 on which the semiconductor chip 1 is mounted in a reflow furnace heated to 250 ° C. having a nitrogen atmosphere. Make a real connection.

At this time, in the semiconductor chip 1, the self-alignment effect is generated due to the surface tension of the solder forming the bump electrodes 3, a slight positional deviation generated during mounting is corrected, and bonding is performed at an accurate position. become.

The gap formed between the semiconductor chip 1 and the circuit wiring board 14 of the semiconductor device flip-chip mounted as described above has the height of the bump electrode 3 formed on the semiconductor chip 1 before the flip-chip mounting. Than 25
It had a value of 50 μm, which is a μm small dimension.

Finally, as shown in FIG. 2 (e), the circuit wiring board 14 on which the semiconductor chip 1 is mounted is stored in a clean oven at 80 ° C. for 4 hours to seal the thermosetting resin sheet 6 Completely cure.

As described above, the reliability life of the bump electrode 3 is Nf = Cf ^1/3 γ _max · exp (1428 / Tm
ax), γ _max = {1 / (Dmin / 2) ^{2 / β} } (V /
πh ^{1 + β} ) ^{1 + β} · d · ΔT · Δα.

According to this embodiment, since the volume of the bump electrode 3 is substantially increased, the reliability life is extended by the above equation, and a highly reliable flip-chip mounted semiconductor device can be obtained.

The present embodiment (claims 3 to 7)
Then, the semiconductor chip 1 is inspected by using the wiring pattern 7 having the same pattern as the circuit wiring formed on the thermosetting resin sheet 6 as an inspection electrode. Since such a wiring pattern 7 is usually larger than the bump electrode 3, it is possible to easily and accurately apply the probe needle 10 for inspection, which allows the semiconductor chip 1 to be easily and accurately inspected. . Therefore, it becomes possible to manufacture a semiconductor device in which only a good semiconductor chip 1 is reliably mounted, and it is possible to improve reliability.

When the bump electrode 3 is melted, the wiring pattern 7 formed on the thermosetting resin sheet 6 is dissolved in the bump electrode 3, so that the wiring pattern 7 is substantially removed after the inspection. Therefore, it is possible to prevent a short circuit between the wirings due to the remaining wiring pattern 7 and a corrosion due to the intrusion of impurities.

Furthermore, since the wiring pattern 7 is dissolved in the bump electrode 3 and a part of the wiring pattern 7 remains on the bump electrode 3, the volume of the bump electrode 3 is substantially increased, so that the reliability life is improved. This makes it possible to easily manufacture a highly reliable flip-chip mounted semiconductor device.

Further, according to the present embodiment, the thermosetting resin sheet 6 is heated in the state where the semiconductor chip 1 is connected to the thermosetting resin sheet 6, and the gap between the semiconductor chip 1 and the circuit wiring board is obtained. Since it is sealed with a thermosetting resin,
It is possible to prevent a decrease in reliability due to residual thermosetting resin in the gaps between the bump electrodes 3 and the connection electrodes 15 or the circuit wiring, or nonuniform formation.

As shown in FIG. 4, the semiconductor chip 1 is inspected in a state in which the wiring pattern 7 on the back surface of the thermosetting resin sheet 6 is aligned with the wiring pattern of the circuit wiring board 14 in contact with the wiring pattern in the roll sheet state. That is, in other words, by performing the inspection in a state where the semiconductor chip 1 and the circuit wiring board 14 are not connected mechanically but are electrically connected, it is possible to perform an inspection at a semiconductor device level in which the semiconductor chip 1 and the circuit wiring board 14 are integrated. It is possible.

In this case, since the semiconductor chip 1 and the circuit wiring board 14 are not mechanically connected, the semiconductor chip can be easily replaced when a defect is found by inspection.

Further, the method of inspecting in the roll sheet state is suitable for mass production as compared with the method of the present embodiment. On the other hand, on the other hand, the method of this embodiment is suitable for inspection of a semiconductor device for a specific application.

When the inspection and connection are performed in the roll sheet state, it is preferable that the thermosetting resin sheet 6 be cut on the circuit wiring board 14.

FIG. 5 is a diagram showing the relationship between the number of temperature cycles and the cumulative defective rate as a result of the reliability test of the semiconductor device manufactured according to the method of the present embodiment and the semiconductor device manufactured according to the conventional resin sealing method. Is.

Also in the conventional method, similarly to the present embodiment, the diameter of 100 μm composed of 256 solders is formed on the semiconductor chip.
The φ bump electrode 3 (Pb / Sn = 40/60) is formed, and the SLC substrate is used as the circuit wiring substrate. The wiring pattern has a width of 100 μm and a thickness of 20 μm.

In this test, the number of samples is 1000, and the case where the connection is open even at one of the 256 bump connection portions is regarded as a defect. Also,
Temperature cycle conditions are -55 ° C (30 min) to 25 ° C
(5 min) to 125 ° C (30 min) to 25 ° C (5 m
in).

In the case of the conventional method, a defect was generated after 1000 cycles and 100% defective after 2000 cycles.

On the other hand, in the case of this embodiment (the material of the wiring pattern 7 is solder), high reliability that no defects occur up to 3000 cycles can be obtained. It is considered that this is because the wiring pattern 7 and the bump electrode 3 are made of the same material, so that the volume of the bump electrode 3 is effectively increased and the stress strain is relaxed.

In the case of this embodiment (the material of the wiring pattern 7 is Au) (however, the width of the wiring pattern 7 is 100 μm).
m, thickness 20 μm), no defects occurred until 4500 cycles. The material of the wiring pattern 7 is Cu and is Au.
Also in the case of the same size as above, no failure occurred similarly up to 4500 cycles.

FIG. 6 shows a semiconductor chip 1 and a circuit wiring board 1.
Area of thermosetting resin sheet 6 in the gap with 4 (vertical and horizontal dimensions)
FIG. 5 is a diagram showing the relationship between the percentage of the total area of the thermosetting resin sheet 6 (amount of resin protruding) and the fatigue life cycle number. The shape, number, and reliability test environment of the samples are the same as in the case of FIG.

When the amount of the protruding resin was 25% or more, the thermosetting resin sheet 6 for encapsulating the bump electrodes 3 was peeled off regardless of the type of substrate.

However, when the amount of the protruding resin was 25%, it was found that the thermosetting resin sheet 6 did not peel off and the reliability life was high.

According to this embodiment, the thermosetting resin sheet is heated in the state where the semiconductor chip 1 is connected to the thermosetting resin sheet 6, and the gap between the semiconductor chip 1 and the circuit wiring board 14 is increased. Since it is sealed with a thermosetting resin, the conventional sealing speed of 0.1 mm / min is about 1
It became possible to seal at 0 times faster.

Further, in the case of the conventional method, 2 mm × 2 m
Although about 10 voids of about m were generated with a probability of about 50%, according to the present embodiment, the generation of voids can be prevented.

An MCM (Multi-chip) for flip-chip mounting 25 semiconductor chips using the method of this embodiment.
As a result of the hip module), the inspection became possible before assembly, so the yield, which was 64% in the past, could be improved to 98%. Further, since the semiconductor chip 1 can be burned in, the initial failure of the MCM can be reduced to 0%.

(Second Embodiment) FIG. 7 shows a second embodiment of the present invention.
FIG. 6 is a perspective view showing the middle of the manufacturing process of the flip-chip mounted semiconductor device according to the embodiment of the present invention. This is Figure 1
This corresponds to the step of mounting and holding the semiconductor chip 1 on the thermosetting resin sheet 6 in (c).

The present embodiment differs from the first embodiment in that, first, instead of the thermosetting resin sheet 6, the width is 35 mm.
mm, the thermosetting resin roll sheet 6a having sprocket holes 17 on both sides and a wiring pattern (inspection pattern) 7a on the back surface is used, and a plurality of semiconductors are formed on the thermosetting resin roll sheet 6a. It is because the chip was mounted and held.

The wiring pattern on the back surface of the thermosetting resin roll sheet 6a of each semiconductor chip 1 is the same wiring pattern as the circuit wiring. The circuit wiring pattern may be partly the same pattern.

After the step shown in FIG. 7, the steps shown in FIGS.
It is similar to the process of. That is, first, each semiconductor chip 1 is applied to each wiring pattern on the back surface of the thermosetting resin roll sheet 6a by using a known probing technique.
Conduct electrical inspection of.

Next, a plurality of semiconductor chips 1 are placed in the reflow furnace.
The bump electrode 3 is reflowed by passing through the thermosetting resin roll sheet 6a on which the wiring pattern formed on the back surface of the thermosetting resin roll sheet 6a is dissolved in the bump electrode to form the wiring pattern 7 Is substantially removed and the volume of the bump electrode is substantially increased.

Next, the blade is pressed against the thermosetting resin roll sheet 6a to cut the thermosetting resin roll sheet 6a with a predetermined size (for example, 12 mm × 12 mm) centering on each semiconductor chip 1.

Next, the same number of circuit wiring boards as the semiconductor chips are prepared, and the bump electrodes of each semiconductor chip 1 and the circuit wiring boards are formed by using the flip chip bonder for aligning the half mirror, which is a known technique. After the alignment with the connection electrode of (1), the bump electrode and the connection electrode are brought into electrical and mechanical contact, and the semiconductor chip 1 is mounted on the circuit wiring board. Then, similar to the first embodiment, the main connection is performed through the preheating and the temporary connection.

Finally, the circuit wiring board on which the semiconductor chip 1 is mounted is completely cured by the thermosetting resin roll sheet 6a.

In this embodiment, the same effect as that of the first embodiment can be obtained. Further, it becomes possible to efficiently manufacture flip-chip mounted semiconductor devices in large quantities. It should be noted that various modifications can be made as in the first embodiment.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the SLC substrate is used as the circuit wiring substrate, but another substrate may be used. Further, although the bump electrodes are arranged around the semiconductor chip in the above embodiment, they may be arranged in a matrix.

Besides, various modifications can be made without departing from the scope of the present invention.

[0111]

[0112]

According to the present invention (claims 1 to 5) , the wiring having at least a part of the same pattern as the circuit wiring formed on the thermosetting resin sheet is used as the inspection electrode. As a result, the semiconductor chip can be easily and accurately inspected, so that it becomes possible to manufacture a semiconductor device in which only good semiconductor chips are reliably mounted, and reliability can be improved.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing a first half manufacturing method of a flip-chip mounted semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a manufacturing method of the latter half of the flip-chip mounted semiconductor device according to the first embodiment of the invention.

FIG. 3 is a diagram for explaining another inspection method.

FIG. 4 is a diagram for explaining another inspection method.

FIG. 5 is a diagram showing the relationship between the number of temperature cycles and the cumulative defective rate, which are the results of a reliability test showing the effect of the present invention.

FIG. 6 is an area (length and width) of the thermosetting resin sheet in the gap between the semiconductor chip 1 and the circuit wiring board showing the effect of the present invention.
Showing the relationship between the percentage of the total area of the thermosetting resin sheet (the amount of resin protruding) and the number of fatigue life cycles

FIG. 7 is a perspective view showing the middle of a manufacturing process of a flip-chip mounted semiconductor device according to a second embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a schematic configuration of a conventional flip-chip mounted semiconductor device.

FIG. 9 is a sectional view showing a schematic configuration of another conventional flip-chip mounted semiconductor device.

FIG. 10 is a sectional view showing a schematic configuration of another conventional flip-chip mounted semiconductor device.

FIG. 11 is a sectional view showing a schematic configuration of another conventional flip-chip mounted semiconductor device.

FIG. 12 is a plan view for explaining another conventional inspection method for a flip-chip mounted semiconductor device.

[Explanation of symbols]

1 ... Semiconductor chip 2 ... Bonding pad 3 ... Bump electrode 4 ... passivation film 5 ... Barrier metal 6 ... Thermosetting resin sheet 6a ... Thermosetting resin roll sheet 7 ... Wiring pattern 8 ... Through hole 9 ... Protective resin sheet 10 ... Probe needle 11 ... Projection inspection electrode 12 ... Inspection board 13 ... Blade 14 ... Circuit wiring board 15 ... Connection electrode 16 ... Solder resist

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-2-96343 (JP, A) JP-A-3-290936 (JP, A) JP-A-7-29938 (JP, A) JP-A-4- 273464 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/60 H01L 21/92

Claims (5)

(57) [Claims] 1. A semiconductor chip on which bump electrodes are formed and a thermosetting resin sheet on which wiring having at least a part of a predetermined pattern is formed on the surface of the semiconductor chip for connecting to the wiring. A step of providing an opening in the thermosetting resin sheet and connecting the bump electrode and the wiring through the opening; and a step of inspecting the semiconductor chip by using the wiring as an inspection electrode When, by dissolving or solid solution of the wiring to the bump electrode, thereby removing the wiring, a step of increasing the volume of the bump electrodes, the circuit wiring board on which a circuit wiring is formed to have a predetermined pattern A method of manufacturing a semiconductor device, comprising a step of electrically and mechanically connecting the circuit wiring and the bump electrode. 2. A plurality of semiconductor chips are connected to the thermosetting resin sheet, the thermosetting resin sheet is cut at an outer peripheral portion of each semiconductor chip, and bump electrodes of each semiconductor chip are provided with different circuits. The method for manufacturing a semiconductor device according to claim 1 , wherein the method is electrically and mechanically connected to the circuit wiring of the wiring board. 3. The circuit wiring and the bump electrode are electrically connected.
After the process of mechanically and mechanically connecting the semiconductor chip to the thermosetting resin sheet, the thermosetting resin sheet is heated so that the gap between the semiconductor chip and the circuit wiring board is thermoset. the method of manufacturing a semiconductor device according to claim 1 or claim 2, characterized in that the sealing with resin. 4. After electrically connecting the circuit wiring and the bump electrode according to claim 1, characterized in that performing the test, the semiconductor device according to any one of claims 2 and 3 Production method. 5. The ratio of the total area of the thermosetting resin sheet to the area of the thermosetting resin sheet in the gap between the semiconductor chip and the circuit wiring board is 1 or more and 1.5.
It is the following, The manufacturing method of the semiconductor device in any one of Claim 1 , Claim 2 , Claim 3, and Claim 4 .