JP3486641B2 - Method for manufacturing field effect transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field effect transistor, and more particularly to processing a gate portion of a field effect transistor using a compound semiconductor.

[0002]

2. Description of the Related Art HEMT which is often used in high frequency region
In the (high electron mobility field effect transistor), as is well known, a T-shaped gate is used to reduce the gate resistance. Further, in order to improve the withstand voltage between the source and the drain, it is often practiced to make the distance between the gate and the drain larger than the distance between the source and the gate to form a recess structure.

As described above, as a method of manufacturing a field effect transistor having a T-shaped gate and a recess structure in the drain portion, there is an invention described in Japanese Patent Application Laid-Open No. 11-008256. In this method, a first film (for example, a first film having an opening with a width corresponding to the width of a recess to be formed on the active layer
An opening having a width equal to the gate length of the gate electrode to be formed, which is made of a material having a lower adhesion to the active layer than the material forming the first film. Form a structure in which a second film (for example, a resist) provided in a position included in the opening of the first film is formed, and recess etching (recess forming step) is performed on the structure. It is a thing.

However, in this method, since there is always a positioning error for forming the opening, it is impossible to control with a positional accuracy less than that error, so that it is impossible to fabricate especially when the recess distance is about that error. become,
There is a drawback that.

Further, there is an invention described in Japanese Patent Application Laid-Open No. 10-107261, which corresponds to a gate electrode by making the areas of openings of a resist material formed on a source electrode and a drain electrode different from each other. The above structure is realized by changing the amount of side etching on the source electrode side and the drain electrode side when removing the cap layer in the region.

Further, there is an invention described in Japanese Patent Application Laid-Open No. 11-186289, in which a resist film is formed on a GaAs substrate on which a channel region, a drain electrode and a source electrode are formed. A gate groove having a cross-sectional shape with a partial surface of the channel region as the bottom and an overhang-shaped drain groove with a partial surface of the drain electrode as the bottom is formed and then immersed in an etching solution. After stacking and etching, Al is vapor-deposited on the entire surface and then the resist film is removed.

Further, there is an invention described in Japanese Patent Laid-Open No. 10-098180, which corresponds to a gate electrode by making the areas of openings of a resist material formed on a source electrode and a drain electrode different from each other. The above structure is realized by changing the amount of side etching on the source electrode side and the drain electrode side when removing the cap layer in the region.

However, these methods have a drawback that it is difficult to obtain a large difference between the side etching amounts on the source side and the drain side.

Further, there is an invention described in Japanese Patent Application Laid-Open No. 10-125696, which is "a buffer layer, an active layer, an etching stopper layer, on a semi-insulating semiconductor substrate,
A cap layer is provided, and a first resist film having two first openings is formed on the cap layer. The cap layer is etched to form a recess connecting under the two openings. A second resist film is formed, and a hardly soluble resist mixed layer is formed at the interface between both resists. The second resist film is exposed and developed to form an undercut-shaped second film on one of the first openings.
To form an opening. The gate electrode is formed by depositing the gate metal and lifting off. ], The above structure is realized.

However, in this method, since the resist is also applied to the recess etching surface, it is necessary to etch the semiconductor surface again after the second resist development. At this time, side etching newly proceeds. In addition to the disadvantage that the drain side etching occurs, it is difficult to make the side etching amount on the drain side inside the umbrella-shaped portion of the T-type gate.

[0011]

In the conventional method for manufacturing a field effect transistor, as described above, since 1) there is always an alignment error, it is not possible to control with a position accuracy less than that error, so that the recess distance is particularly large. If it is about that error, it becomes impossible to manufacture. 2) It is difficult to obtain a large difference in the side etching amount between the source side and the drain side. 3) The resist is also applied to the recess etching surface. After the second resist development, it is necessary to etch the semiconductor surface again,
At this time, there are disadvantages that side etching is newly advanced, and 4) it is impossible to make the side etching amount on the drain side inside the umbrella-shaped portion of the T-type gate.

The present invention has been proposed in view of the above,
Characteristics of the field effect transistor, specifically, the source resistance,
A field-effect transistor capable of forming a T-shaped gate electrode in a desired position close to the source side in a recess with high precision and uniformity in order to reduce gate resistance, gate-drain capacitance, and improve source-drain breakdown voltage. It aims at providing the manufacturing method of.

[0013]

[Means for Solving the Problems] To achieve the above object
The first invention relates to a method for manufacturing a field effect transistor.
The source region and the drain on the compound semiconductor substrate.
After forming the in region, the source region or the drain region is formed.
Alignment for drawing directly or indirectly
Transistor manufacturing process to perform and form gate electrode
The shape of the contact area between the gate electrode and the semiconductor
Placed on the source side, reaching the semiconductor substrate in the layer to be defined
Placed on the straight groove and on the drain side reaching the semiconductor substrate
Forming a plurality of dot-shaped holes that are formed and isotropic etching
The recess shape between the source and gate and the gate
The step of forming a recess shape between the drain and the above,
Of the compound semiconductor substrate has a momentum component in the vertical direction.
In the process of depositing metal atoms or particles in the above groove,
In order to reduce the deposition on the semiconductor substrate through the plurality of dot-shaped holes as compared with the above case, after forming the source region and the drain region on the compound semiconductor substrate, In a transistor manufacturing process in which a gate electrode is formed by directly or indirectly performing alignment for drawing, a straight line arranged on the source side reaching the semiconductor substrate in a layer that defines the shape of the contact portion between the gate electrode and the semiconductor. A step of forming the upper groove and a plurality of dot-shaped holes arranged on the drain side reaching the semiconductor substrate, and a recess shape between the source and the gate and a recess shape between the gate and the drain by the isotropic etching. And a step of forming a momentum component perpendicular to the compound semiconductor substrate surface, and a motion parallel to the semiconductor surface and orthogonal to the linear groove A step of depositing a metal atom or particle having a component, which is larger than the compound semiconductor substrate surface and a momentum component parallel to the linear groove parallel to the surface of the compound semiconductor substrate, in the groove. There is.

In addition, in order to apply the lift-off method, a second aspect of the invention is that in addition to the structure of the first aspect of the invention, the first layer is provided in a layer that defines the shape of the contact portion between the gate electrode and the semiconductor.
Second resist layer and a third resist layer on top of it, and the width of each groove is such that the groove of the first resist layer <the groove of the third resist layer <the second groove
It is characterized in that the groove is formed in the resist layer.

In addition to the structure of the first aspect of the invention , the third aspect of the invention is arranged on the drain side reaching the semiconductor substrate in order to make it difficult for the deposits to deposit in a plurality of point holes. The shape of the plurality of dot-shaped holes formed is characterized in that the size in the direction orthogonal to the groove is larger than the size in the direction parallel to the groove.

In addition to the structure of the first invention , a fourth invention is to improve the withstand voltage between the source and drain,
The array of the plurality of dot-shaped holes arranged on the drain side reaching the semiconductor substrate is characterized by including a plurality of rows arranged in a direction parallel to the groove.

In addition to the structure of the first invention , a fifth invention is to improve the withstand voltage between the source and drain,
The length of the etching in the direction parallel to the surface of the semiconductor substrate caused by the above isotropic etching is longer than half the length of the interval of the array of the plurality of dot-shaped holes arranged on the drain side. There is.

In addition to the structure of the first aspect of the invention, the sixth aspect of the invention is parallel to the surface of the compound semiconductor substrate and on the straight line so that the extraction electrode can be formed without disconnection. It is characterized in that the momentum component parallel to the groove goes from one end of the gate wiring connected to the other end of the gate wiring not connected.

In addition to the structure of the first invention , the seventh invention is such that the angle between the momentum direction of the metal atom or particle group deposited in the groove and the compound semiconductor substrate surface is The angle is such that the bottoms of the plurality of dot-shaped holes arranged on the drain side cannot be expected.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. However, in the following explanation, regarding the structure having the same function and the similar substance,
Description will be given with the same reference numerals.

First, FIG. 1 is a diagram showing a first embodiment of the present invention. FIG. 1 is a view showing a cross section of a field effect transistor during the manufacturing process.
Micron InP semi-insulating semiconductor substrate 1, 300 nm thick In
AlAs layer 2, 15 nm thick InGaAs layer 3, 10 nm thick InAl
As layer 4, InP layer 5 with a thickness of 6 nm, InGaAs layer 6 with a thickness of 25 nm,
0.25 micron thick AuGe on the InGaAs layer 6
The source electrode 11 and the drain electrode 7 formed of / Ni / Au are joined, and the semiconductor InGaAs layer 6 has a thickness
A 12 nm silicon oxide film 12 is attached, and a 180 nm thick resist layer 8 (Nippon Zeon ZE
P), and on top of it there is a 450 nm thick resist layer 9 (Microlithography Chem
musical Corp. PMGI) is attached and a resist layer 10 (Nihon Zeon ZEP) having a thickness of 240 nm is attached on the uppermost part, and a schematic cross-sectional view of one having already been patterned twice. Is shown.

The above patterning will be described in detail. As shown in FIG. 1A, when forming a resist pattern for forming a T-type gate electrode, a commercially available electron beam apparatus is used as the uppermost layer and the intermediate layer. After exposure and development using a mask, a gate electrode pattern is formed on the lowermost layer resist (the thickness of the resist is d), and a plurality of slit patterns finer than that on the drain side of the gate electrode pattern (pattern size is a And the depth is b) at a desired position between the source and the drain (the distance from the gate electrode pattern is l (el)).

Next, as shown in FIG. 1B, a silicon oxide film is opened by a reactive ion etching (RIE) process, and subsequently, etching for forming a recess structure (recess etching) is performed. The recess etching is based on wet etching using citric acid. As can be seen from FIGS. 3B and 3C showing cross sections when the recess etching time is changed, each pattern does not depend on the pattern size. With respect to the center, the symmetry progresses symmetrically in the source side / drain side and in the front / depth direction (the side etching amount at this time is defined as r). Therefore, the recess regions on the source side and the drain side are connected to each other when r = 1/2. The SEM image of this state is shown in FIG.
A sectional view is shown in (a) and a bird's-eye view is shown in FIG. 7 (b). The etching amount from the gate electrode to the source side is determined by r, and the length of the gap extending from the gate electrode to the drain side is (l + a +
Since it is determined by r), the length of the gap extending in each of the source side and the drain side can be controlled independently. At this time, the side etching rate (recess rate)
Was almost constant until the etching time was 4 to 5 minutes. Therefore, it is apparent that the side etching amount r during this period can be accurately controlled by the etching time.

Next, as shown in FIG. 1 (c) and FIG. 2, a metal (Ti / Pt / A) for forming a gate electrode is formed.
u) The beam is vacuum-deposited from the front (gate electrode wiring side) toward the back at an angle of α> tan ⁻¹ (b / d) from the vertical direction. Here, FIG. 2 shows a plan view of FIG. As a result, the gate metal is not deposited on the semiconductor surface directly below the fine slit pattern, but is deposited only on the semiconductor surface directly below the gate pattern. Since the fine pattern is completely closed with metal when the thickness of the deposited film reaches b (sin ^-1 α), metal does not enter the fine slit pattern portion after that, so the gate metal May be vapor-deposited from the vertical direction. After that, the resist layers 8, 9 and 10 are removed at the same time, whereby an extra metal film which does not contribute as a gate electrode can be removed. This method is well known as lift-off.

In the above description, the gate metal is vapor-deposited from one direction at an end and then from the vertical direction. However, when the plurality of dot-shaped holes arranged on the drain side are sufficiently fine, the gate metal is originally formed. , Even if the gate metal reaches the surface of the semiconductor substrate through the holes by vapor deposition from the vertical direction, the deposited metal accumulates in a triangular shape with a base on the surface of the semiconductor substrate, so it is separated from the gate electrode and the transistor characteristics are It doesn't get worse.

The process described above realizes a transistor having an asymmetric recess structure. Figure 4
FIG. 6 is an AFM image of the recess structure formed by the above-described process, in which the film on the upper portion of the recess structure is removed in order to see the etching state. Here, the slit spacing (Fig. 4 (a))
If c) is smaller than the side etching amount (r in FIG. 4A), the unevenness at the boundary portion of the recess structure can be suppressed within about 10% of the side etching amount r. As shown in FIG. 4C, the unevenness on the semiconductor surface is
It is suppressed to 1 nm or less. By the way, Figure 4 (c)
Is an average value obtained by measurement performed by scanning the square portion of FIG.

In the above process, it is effective to use a silicon oxide film formed by vapor deposition as the silicon oxide film between the resist and the semiconductor surface in order to perform uniform side etching. The reason for this is that the adhesion between the semiconductor substrate and the silicon oxide film formed by vapor deposition is weaker than that of a silicon oxide film formed by a normal CVD method, so that side etching reduces the opening size of the silicon oxide film (resist pattern size). This is because it does not depend on it and progresses similarly.

FIG. 5 shows a TEM image showing the gate length dependence of the recess etching amount when the TEOS film is used as the silicon oxide film. In a normal CVD film, as shown in FIGS. 5A to 5C, the adhesion between the semiconductor and the silicon oxide film is strong, and the side etching amount tends to become smaller as the pattern size becomes smaller. Has been done.

For etching the silicon oxide film having a fine pattern, it is desirable to carry out gas etching using CF4 or the like with the resist pattern as a mask. In this case, the resist itself is also etched and its shape changes, so it is important to thin the silicon oxide film to about 10 nm to shorten the etching time.

As is clear from the above description, in the present invention,
Patterning to form a recess structure on the source electrode side,
The alignment with the patterning that forms the recess structure on the drain electrode side is unnecessary, and by selecting the patterning data and controlling the etching time to determine the etching amount, the recess structure on the source side / drain side can be easily formed. Can be arbitrarily selected, and since the resist coating step for forming the recess structure is performed only once, the etched semiconductor surface is not exposed to the resist, so that contamination by the resist can be suppressed.

Next, FIG. 6 shows a second embodiment of the present invention. FIG. 6A shows a semiconductor substrate having a structure similar to that of the semiconductor substrate according to the first embodiment, with a thickness of 0.25.
The source electrode 11 (and the drain electrode 7 formed of micronized AuGe / Ni / Au are joined, and the semiconductor In
The GaAs layer 6 is provided with a silicon oxide film 12 having a thickness of 12 nm, and a resist layer 8 having a thickness of 180 nm is formed on the silicon oxide film 12.
A schematic cross-sectional view of a structure having (Zeon Corporation, ZEP) provided with a gate electrode pattern and a plurality of slit patterns finer than that on the drain side of the gate electrode pattern is shown.

The structure of FIG. 6 (a) is subjected to the recess etching described above, and then a metal (Ti / Pt / Au) beam for forming a gate electrode is formed as shown in FIG. 6 (c). Vacuum deposition is performed from the front (gate electrode wiring side) to the back from the vertical direction at an angle α> tan ^-1 (b / d). The conditions at this time may be the same as those in the above-described first embodiment. Next, the gate electrode is formed by photolithography using the well-known resist 14.

As compared with the first embodiment, the advantage of this method is that the exposure conditions of the lowermost layer are not influenced by the exposure of the uppermost layer / intermediate layer, and therefore a finer pattern can be formed.
Since the electron beam is not used, it is possible to prevent the adverse effect of the electron beam at the time of patterning the channel portion.

[0034]

Since the present invention has the above-mentioned structure,
The effects described below can be achieved.

First, according to the first invention, the recess shape between the source and the gate and the recess shape between the gate and the drain can be independently controlled, and further, it is possible to form the source with high accuracy and uniformity. The resistance, the drain resistance, the gate-drain capacitance, and the source-drain breakdown voltage can be controlled with high precision, and the characteristics of the field effect transistor can be optimized.

Further, according to the second invention , in addition to the effect of the first invention , the lift-off process can be used.

Further, the controllability of the effect of the first invention is further improved by any one of the third to fifth inventions .

Further, according to the sixth invention , in addition to the effect of the first invention , disconnection of the extraction electrode is reduced.

Further, according to the seventh invention , it becomes difficult to form a region connected to the gate electrode in the recess region near the drain, and it is possible to prevent one of the factors that reduce the effect of the first invention. became.

[Brief description of drawings]

1A, 1B, 1C are cross-sectional views of a field effect transistor during a manufacturing process.

FIG. 2 is a diagram showing a plan view of FIG. 1 (c).

FIG. 3 is a diagram showing a cross section when the recess etching is changed, (a) immediately after development and before etching, (b) after recess etching for 2 minutes, and (c) recess for 3 minutes. It is an SEM image showing a section after etching.

4A is a view showing an AFM image of the formed recess structure from which a film on the upper part is removed, FIG. 4B is a view showing a measurement region for unevenness of a semiconductor surface, and FIG. FIG. 5 is a diagram showing the measurement results.

FIG. 5 is a TEM image showing the gate length dependence of the recess etching amount when a TEOS film is used as a silicon oxide film.

FIG. 6 is a diagram showing a second embodiment of the present invention.

FIG. 7 is a view showing an SEM image in a state where the source-side and drain-side recess regions are connected, and FIG. 7A is a sectional view,
(B) shows a bird's-eye view.

[Explanation of symbols]

1 InP semi-insulating semiconductor substrate 2 InAlAs buffer layer 3 InGaAs channel layer 4 InAlAs barrier layer 5 InP etching stopper layer 6 InGaAs cap layer 7 drain electrode 8 ZEP 9 PMGI 10 ZEP 11 source electrode 12 silicon oxide film 13 gate electrode 14 negative resist

Claims (7)

(57) [Claims] 1. A transistor manufacturing process for forming a gate electrode by forming a source region and a drain region on a compound semiconductor substrate, and then directly or indirectly aligning the source region or the drain region for writing. A linear groove arranged on the source side reaching the semiconductor substrate and a plurality of dot-shaped holes arranged on the drain side reaching the semiconductor substrate, in the layer that defines the shape of the contact portion between the gate electrode and the semiconductor. A step of forming a recess shape between the source and the gate by isotropic etching, and a recess shape between the gate and the drain, and a momentum component in the direction perpendicular to the compound semiconductor substrate surface,
A metal atom or particle having a momentum component parallel to the semiconductor surface and orthogonal to the above linear groove, and a larger momentum component parallel to the compound semiconductor substrate surface and parallel to the above linear groove, And a step of depositing in the groove. 2. A first resist is used as a layer for defining a shape of a contact portion between the gate electrode and the semiconductor, a second resist layer is formed on the first resist layer, and a third resist layer is further formed on the second resist layer. The field effect transistor according to claim 1 , wherein the width of each groove is formed so that the groove of the first resist layer <the groove of the third resist layer <the groove of the second resist layer. Production method. 3. The shape of the plurality of dot-shaped holes arranged on the drain side reaching the semiconductor substrate is such that the size in the direction orthogonal to the groove is larger than the size in the direction parallel to the groove. The method for manufacturing the field effect transistor according to claim 1 . Wherein the sequence of said plurality of point-like holes arranged on the drain side to reach the semiconductor substrate, the row arranged in a direction parallel to the groove, characterized in that it comprises a plurality of rows 請
A method for manufacturing a field effect transistor according to claim 1 . 5. The length of the etching in the direction parallel to the surface of the semiconductor substrate caused by the isotropic etching is half the length of the interval of the array of a plurality of dot-shaped holes arranged on the drain side. The method for manufacturing a field effect transistor according to claim 1 , wherein the field effect transistor is also long. 6. A momentum component parallel to the surface of the compound semiconductor substrate and parallel to the linear groove is directed from one end to which the gate wiring is connected to the other end to which the gate wiring is not connected. The method for manufacturing a field effect transistor according to claim 1 . 7. The angle formed by the momentum direction of the metal atom or particle group deposited in the groove and the surface of the compound semiconductor substrate is determined by the bottom of a plurality of dot-shaped holes arranged on the drain side. The method of manufacturing a field effect transistor according to claim 1 , wherein the angle is such that the angle cannot be expected.