JP3487724B2 - Method of forming tunnel junction - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a minute tunnel junction.

[0002]

2. Description of the Related Art In recent years, interest in single-electron transistors for controlling individual electrons has been increasing. Ordinary MO that could only control the current as a group of electrons
This is because it is considered that this single-electron transistor can dramatically reduce power consumption and high integration as compared with the S-type field effect transistor. Several structures of such single-electron transistors have been described in, for example, Document I (Physics of microtunnel junctions and their applications (Applied Physics Vol. 62, No. 9).
No. pp.889-897 (1993)). In either structure, a single-electron transistor consists of two small tunnel junctions, a control gate, and a small island (also called a central conductive layer or dot) surrounded by these tunnel junctions and control gates. With the basic structure
I have it (details will be explained later using FIG. 1). The operating principle of this type of single-electron transistor is described in, for example, Document I, and therefore its details are omitted here. However, in order to operate this type of single-electron transistor at room temperature, the following conditions are required. Required (eg, page 890, left column of document I and page 892, left column). However, in the following conditional expression, C is the element capacitance given by C = C ₁ + C ₂ + C _g, where C ₁ and C ₂ are the capacitances of the two tunnel junctions and C _g is the gate capacitance. Further, k _B is Boltzmann's constant and T is temperature. Further, R _T is a tunnel resistance, and h is a Planck constant.

E _C = e ² / 2C << k _B T (1) R _T >> R _k = h / e ² (2) Therefore, at room temperature, for example 300K, the formula (1) is satisfied. In order to do so, if T = 300 in equation (1), then C << 3a
It is necessary to satisfy F (atofarad).

[0004]

The device capacitance C is C << 3.
In order to satisfy aF, it is necessary to form a tunnel junction having a minute junction area. If the junction thickness of the tunnel junction is increased, the device capacitance can be reduced. However, since the function of the tunnel junction cannot be obtained in the first place, the junction area must be reduced. Therefore, specifically, a processing technology of the order of 10 nm is required. The electron beam lithography technique is currently most suitable as such a processing technique. However, even with the electron beam lithography technique, since the beam diameter of a commercially available electron beam exposure apparatus is about 30 nm at the minimum, the above 10
It has been difficult to perform fine processing on the order of nm. A new technique capable of forming a minute tunnel junction is desired.

[0005]

Therefore, according to the first invention of the method for forming a tunnel junction of this application, in forming a tunnel junction having a structure in which an insulating film is sandwiched between conductive layers, the following (A) ) Claim a method that includes the steps (1) to (E).

(A). A second layer having a property of leaving a portion exposed to an electron beam directly or through an intermediate film is formed on the first layer for forming a conductive layer. Process.

(B). The first approaching layer in the second layer
And the second region are exposed by an electron beam at an exposure dose such that the energy of the electron beam is exuded around the region at least in the approaching portion.

(C). By developing the exposed second layer, the first region of the second layer and the second region of the second layer are developed.
And a third region in which the energy bleeding between the first and second regions overlaps each other.

(D). The first layer is directly or indirectly patterned by using the mask pattern as an etching resistant mask, and the first layer is formed in a portion corresponding to each of the first to third regions. The step of leaving the layers.

(E). A step of forming an insulating film to be a tunnel insulating film between the remaining portions of the first layer after removing the mask pattern.

According to the first aspect of the method for forming a tunnel junction, a portion of the electron beam energy that oozes out when these regions are exposed is provided between the first region and the second region. An exposure area is formed due to the overlapping. The area of the exposure region exposed due to the overlap of the electron beam energy seepage can be made smaller than in the case of direct exposure with an electron beam. The small area of the exposure region means that a conductive layer having a small plane area (a dot having a small area (a central conductive layer) in the example of a single electron transistor) can be formed. If the conductive layer has a small plane area, the area of the side wall becomes smaller accordingly,
The junction area of the tunnel junction can be made smaller than before. In addition, the fact that a conductive layer having a small plane area can be obtained means
Considering this in the example of a single electron transistor, the gate capacitance can be reduced.

According to the second invention of the method for forming a tunnel junction of this application, the following steps (a) to (d) are performed when forming a tunnel junction having a tunnel barrier composed of a silicon fine wire portion. Insist on how to include.

(A). A step of forming a silicon oxide film on the silicon layer.

(B). A step of patterning the silicon oxide film so that a part of the silicon oxide film has a band shape with a predetermined width.

(C). At least two regions lined up at a predetermined interval in the longitudinal direction of the strip-shaped silicon oxide film portion,
A step of removing a predetermined amount from the surface and forming a mask pattern made of a silicon oxide film in which the film thickness of these regions is reduced from the others.

(D) The width of the silicon layer portion under the mask pattern portion having the film thickness reduced from the other can be set to a new predetermined width less than the predetermined width after etching, and the width of the other silicon layer portion can be reduced. A step of etching the silicon layer under an etching condition of a selection ratio capable of making the width suitable for the mask pattern to form the constricted portion under the mask pattern portion whose film thickness is reduced from the others.

According to the second invention of the method for forming a tunnel junction, the silicon layer is formed by using a predetermined mask pattern made of a silicon oxide film having a partially thinned film as a mask and an etching means with a predetermined selection ratio. To etch. Since the etching selection ratio becomes insufficient in the portion where the film thickness is thin in the mask pattern, the silicon layer portion below that portion is also etched laterally. Therefore, when the etching of the silicon layer is completed, the silicon layer portion below the thinned portion of the mask pattern becomes a thinner portion (constricted portion) than the other portions. This narrowed portion can be used as a tunnel barrier. It is difficult to form a resist pattern for forming such a narrowed portion from the beginning by the electron beam lithography technique. However, in the second invention, a part of the film thickness is thin and a strip-shaped mask pattern is formed. Electron beam lithography is used until formation, and then a predetermined constricted portion is obtained by the above predetermined etching. In carrying out the second invention, after the etching of the silicon layer is completed, the silicon layer may be subjected to a treatment of oxidizing the surface portion of the silicon layer by a predetermined amount. By further oxidizing the surface layer of the silicon layer by a predetermined amount, the constricted portion can be further thinned.

According to each of the first and second inventions of the method for forming the tunnel junction described above, it is expected to realize a single electron transistor having a small device capacitance to the extent that it can operate at room temperature.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a tunnel junction forming method and a single electron transistor manufacturing method according to the present invention will be described below with reference to the drawings. In addition,
Each drawing used in the description merely schematically shows the dimensions, shapes, and arrangement relationships of the respective constituents so that the present invention can be understood. In addition, in each drawing, the same components are denoted by the same reference numerals, and the duplicate description may be omitted. Further, the numerical conditions such as film thickness, temperature, time, size, and exposure dose and materials used described below are merely examples within the scope of the present invention.

1. Description of First Invention of Method of Forming Tunnel Junction An embodiment of the first invention of method of forming a tunnel junction will be described with reference to FIGS. 1 to 4. Here, FIG. 1 is an explanatory view of a single-electron transistor formed by applying the first invention of the method for forming a tunnel junction. FIG. 1A is a plan view of the transistor seen from above, FIG. 7A is a cross-sectional view of the transistor taken along line I-I in FIG. In FIG. 1, 11 is a silicon substrate, 13 is an insulating film (silicon oxide film), 15a is a source region, 15b is a drain region, 15c is a small island (also called a dot or central conductive layer), and 17a and 17b, respectively. Is an insulating film serving as a tunnel barrier, 17c is a gate insulating film, 19 is a control gate, and 21a and 21b are tunnel junctions. 2 to 4 are process drawings for explaining the procedure for forming a tunnel junction by the method of the first invention. However, FIGS. 2 and 4 are shown in a cross-sectional view corresponding to FIG. 1B, and FIG. 3 is a plan view corresponding to FIG. 1A.

First, in the silicon wafer 11a, a surface layer portion is a silicon layer 11x having a thickness of about 40 nm, and an insulating film (embedded silicon oxide film) 13 having a thickness of about 100 nm is formed thereunder. Silicon wafer 11a
Are prepared (FIG. 2 (A)). Here, the silicon layer 11x
Corresponds to the first layer for forming the conductive layer referred to in the present invention, and a part of the layer is the source region 15 shown in FIG.
a, the drain region 15b, and the minute island 15c. In addition, such a silicon wafer 11a is
For example, the upper layer Si of a silicon wafer formed by the SIMOX technique can be prepared by adjusting the desired film thickness (here, about 40 nm) by repeating thermal oxidation and peeling of the oxide film by hydrofluoric acid.

Next, an oxide film 31 of about 30 nm is formed on the silicon layer 11x by thermal oxidation (FIG. 2 (B)). The oxide film 31 corresponds to the intermediate layer in the present invention. This intermediate layer is used later as an etching mask for the silicon layer 11x, and also protects the crystallinity of the silicon layer 11x. Of course, the intermediate layer may not be used.

Next, a negative type electron beam exposure resist layer 33 is formed on the oxide film 31 as a second layer having a property that the portion exposed by the electron beam remains (FIG. 2).
(C)). The second layer 33 has a resist of, for example, SAL601 (manufactured by Shiple Co.) on the oxide film 31, and the thickness is
To a thickness of 120 by spin coating, and apply it to 120
Formed by baking at 2 ° C. for 2 minutes. The silicon wafer on which the second layer 33 is formed is introduced into the electron beam exposure apparatus.

Next, the resist pattern which is a feature of the present invention.
The film forming step is performed as follows.

In the electron beam exposure process, as shown in FIG.
As shown in (A), each of the first region 33a and the second region 33b which are close to each other in the second layer 33 is exposed. However, the first region 33a and the second region 33
It is preferable that each of the regions b has a planar shape in which a portion close to the other region is convex toward the other region. This is because it is easier to reduce the tunnel junction area. In the example of FIG. 3A, the first area 33a
The second area 33b and the second area 33b are each an area having a pentagonal planar shape in which a corner is close to the other area. Of course, the first area 33a and the second area 33
Each of b may have a planar shape such as a triangular shape or a quadrangular shape, and a corner portion of which is on the side of the other region.
Further, the approach distance X ₁ between the first region 33a and the second region 33b is determined in consideration of the fact that the exposure energies from both regions 33a and 33b affect each other when exposed. . Although not limited to this, here, the distance X ₁ is, eg, 50 nm. In addition, the first area 33a
The exposure amount for exposing each of the second region 33b and the second region 33b is set to a dose amount higher than usual. Specifically, at least the portions of each of the first and second regions 33a and 33b that are close to each other (here, around the apex of the triangular portion), the energy of the electron beam exudes around the portions. Exposure is performed with such an exposure amount. Although not limited to this, here, the exposure amount is usually 20 μC / cm.
² is exposed under the condition of 30 μC / cm ^{2 over} the first and second regions 33a and 33b. As a result, the first and second areas 33, which are design pattern areas, are provided.
On the outside of a and 33b, a region where the energy of the electron beam is exuded occurs due to the proximity effect. FIG. 3 (A) schematically shows the region 33x (the hatched region in the drawing) of the energy leakage of the electron beam. First and second areas 3
The area 33c (third area 33c) between the areas 3a and 33b where the bleeding energy from both areas overlaps is exposed with an exposure amount about twice that of the other bleeding area 33x. Become. Therefore, the third region 33c also remains after the subsequent development.

After the exposed wafer is taken out of the exposure apparatus, it is baked at 105 ° C. for 2 minutes, and then N
Development is performed by immersion in MDW (developing solution manufactured by Tokyo Ohka Kogyo Co., Ltd.) for about 10 minutes. After the development, the pattern remains in the first region 33a, the second region 33b, and the third region 33c in the resist 33, respectively.
As shown in FIG. 3B, a resist pattern 33y in which dots are left between two patterns, that is, a mask pattern according to the first invention is obtained. When the exposure amounts of the first and second regions 33a and 33b are the same, a resist pattern in which dots are located in the approximate center between the regions 33a and 33b is obtained. The distance X ₁ between the close portions of the first and second regions is, for example, about 50 nm. The interval X ₂ between each of the first and second regions and the dot is, for example, about 10 nm. The dots are circular and have a crossover dimension (also called diameter) X ₃ of about 20 nm. When the exposure amounts of the first and second regions 33a and 33b are different to form a resist pattern in which dots are biased toward one of the regions 33a and 33b (asymmetric resist pattern). There is no problem.

Then, using the resist pattern 33y as an etching resistant mask, the oxide film 31 is etched.
Specifically, the oxide film 31 is etched by reactive ion etching using, for example, a CF ₄ / CHF ₃ / He mixed gas (FIG. 4A). After that, the resist is removed in an O ₂ plasma atmosphere. Next, the silicon layer 11x, which is the first layer of oxide film 31 as a mask, for example, Cl ₂ /
Etching is performed by reactive ion etching using a mixed gas of O ₂ / He. By a series of these steps, a pattern similar to the resist pattern 33y by the electron beam exposure is realized in the remaining portion of the silicon layer 11x.
The source region 15a, the drain region 15b, and the dots 15c formed of these remaining portions are respectively formed (FIG. 4B).

Next, the oxide film 31 used as a mask
Are removed with dilute hydrofluoric acid. Next, the oxide film 35 is formed to a thickness of about 50 nm by using, for example, a chemical vapor deposition method (CVD method) using a SiH ₂ Cl ₂ / O ₂ mixed gas. By this step, the source region 15a, the drain region 15b and the S
Minute tunnel barriers 17a, 17 between the i-dot 15c
b is formed, and the gate insulating film 17c is formed on the Si dot 15c (FIG. 4C). Of course, the method of forming the minute tunnel barriers 17a and 17b and the gate insulating film 17c may be another suitable method. After that, the control gate is formed to obtain the single electron transistor described with reference to FIG.

According to the forming method of the first aspect of the present invention, by positively utilizing the proximity effect due to the electron beam exposure, it is possible to accurately form a minute tunnel junction which is difficult to achieve by the conventional electron beam exposure. I understand.

It is considered that the element capacitance C of the single electron transistor realized by the above embodiment is estimated as follows.

It is considered that the size X ₃ of the dot 15c is 20 nm and the height is 30 nm. Although the initial film thickness of the silicon layer 11x is 40 nm, the dot height is set to 30 nm in consideration of the film reduction due to the formation of the oxide film 31.
Further, since the dot 15c is circular and the tip of the source / drain region is convex, the opposing relationship between the two is assumed as follows in consideration of these shapes. That is, the opposing width between the dot 15c and the source electrode 15a (drain electrode 15b) is considered to be 10 nm, and the distance between the dot 15c and the source electrode 15a (drain electrode 15b) is 15 nm.
I think. The relative permittivity of the insulating films 17a and 17b is set to 3.
9, and the dielectric constant of vacuum is 8.85 × 10 ⁻¹² (F /
m). Then, the capacitance at the tunnel junction is 8.8.
5 x 10 ^-12 x 3.9 x 10 x 10 ^-9 x 30 x 10 ^-9 /
15 × 10 ⁻¹⁵ = 0.7 × 10 ⁻¹⁸ (F) = 0.7 (a
F). The capacitance in the control gate portion is 8.85 × 10 ⁻¹² × because the gate insulating film 17c has a thickness of 50 nm and the dot radius is 10 nm.
3.9 x 3.14 x 10 ² x 10 ^-18 / 50 x 10 ^-9 =
0.2 × 10 ⁻¹⁸ (F) = 0.2 (aF). Eventually, the element capacitance of this single electron transistor becomes 1.6 aF. When converted into electrostatic energy, E _C = e ² /
It becomes 57 meV from 2C. Since this is a value larger than the thermal energy at room temperature (26 meV), this first
Single electron transistors manufactured using the method of the invention are expected to operate at room temperature.

In the above description of the first embodiment of the invention, an example in which a silicon layer is used as the first layer for forming the conductive layer has been described. The layer may be a metal layer such as an aluminum layer.

2. Description of Second Invention of Tunnel Junction Forming Method Next, an embodiment of a novel method of forming a tunnel junction (second invention) composed of a silicon thin wire having a constricted portion will be described. This description will be given with reference to the manufacturing process diagrams shown in FIGS. 5 to 8 and the etching characteristic diagram shown in FIG. However, FIG. 5 is a process diagram showing a cross-sectional view of the sample during the forming process taken along a plane parallel to the tunnel junction surface, and FIGS. 6 to 8 are process diagrams showing a plan view of the sample seen from above. .

First, a silicon wafer 11a having a surface layer of a silicon layer 11x having a thickness of about 40 nm and an embedded silicon oxide film 13 having a thickness of about 100 nm below the surface is formed. Prepare (FIG. 5 (A)). Such a silicon wafer 11a is
For example, the upper layer Si of a silicon wafer formed by the SIMOX technique can be prepared by adjusting the desired film thickness (here, about 40 nm) by repeating thermal oxidation and peeling of the oxide film by hydrofluoric acid.

Next, an oxide film 31 of about 30 nm is formed on the silicon layer 11x by thermal oxidation (FIG. 5 (B)). Next, a resist layer 41 for electron beam exposure is formed on the oxide film 31 (FIG. 5C). In the case of the second invention,
It does not matter whether the resist for electron beam exposure is a negative type or a positive type. However, a negative type is preferable in this step in order to reduce the irradiation area of the electron beam. Here, as the resist layer 41, for example, SAL601 (resist manufactured by Shipre Co.) is spin-coated on the oxide film 31 to a film thickness of 0.1 μm.
It is applied by a coating method and baked at 120 ° C. for 2 minutes. The silicon wafer on which the resist layer 41 is formed is introduced into the electron beam exposure apparatus.

In the electron beam exposure process, first, referring to FIG.
As shown in (A), a resist pattern 41a is formed in the shape of a band, a part of which has a predetermined width W ₁ . Moreover, the length of this strip-shaped portion is Y, and both sides of this strip-shaped portion are W ₂
A resist pattern 41a which is a portion of (W ₂ > W ₁ ) × Y ₁ is formed. In this case, the predetermined width W ₁ is 30
nm. The exposure condition for forming the resist pattern 41a may be, for example, 20 μC / cm ² . After the exposure, the wafer is first baked at 105 ° C. for 2 minutes, and then the wafer is immersed in NMDW (developer of Tokyo Ohka Kogyo Co., Ltd.) for about 10 minutes for development. To do.

Next, the oxide film 3 is formed by reactive ion etching using, for example, a CF ₄ / CHF ₃ / He mixed gas.
Etch 1. After that, the resist is removed in an O ₂ plasma atmosphere. Oxide film pattern 3 similar to the resist pattern formed by electron beam exposure through these series of steps.
1a is formed (FIG. 6 (A), FIG. 5 (D)). In addition,
FIG. 5D is a diagram corresponding to a cross-sectional view taken along the line I-I of FIG.

After the fine line of the oxide film is formed as described above, the resist layer for electron beam exposure is formed again on this sample. In this case, as will be described later, since a resist pattern having an opening is formed, it is preferable to use a positive type electron beam exposure resist layer in order to reduce the exposure area. Here, for example, ZEP520 (positive type resist manufactured by Zeon Corporation) is applied. Then, at least two regions lined up at a predetermined interval in the longitudinal direction of the band-shaped silicon oxide film portion are exposed, and then the resist is developed. The development can be performed, for example, by immersing in normal hexyl acetate for about 8 minutes. By doing so, as shown in FIG. 6B, at least two openings 4 aligned in the longitudinal direction of the strip-shaped silicon oxide film 31a with a predetermined interval y _0.
A resist pattern 43 having 3a is obtained. The predetermined interval y ₀ is a dimension that determines the length of the silicon dot.
The dimension y ₁ of each opening 43a along the longitudinal direction of the strip-shaped silicon oxide film 31a is a dimension that defines the length of the tunnel barrier. Although not limited to this, each of y ₀ and y _{1 is} set to 30 nm here.

Next, using this resist pattern 43 as an etching mask, the oxide film in the opening 43a is etched. The etching conditions at this time may be the same as the etching conditions when forming the oxide film pattern 31a described above, but the etching conditions are such that the oxide film 31 remains to a certain extent. Here, the thickness of the oxide film 31 in the opening 43a is set to about 15 n so as to be about half that of the other portions.
Etch by m. Next, the resist pattern 43 is removed in an O ₂ plasma atmosphere. By this series of steps, the mask pattern 31x made of a silicon oxide film in which the film thickness of the portion corresponding to the opening 43a is reduced from the others is formed (FIG. 7A).

Next, the underlying silicon layer 11x is etched using the mask pattern 31x as a mask. The etching at this time can make the width of the silicon layer portion under the mask pattern portion whose film thickness is smaller than others to a new predetermined width less than the predetermined width W ₁ after etching, and the other silicon layers. The etching is performed under the etching condition of the selection ratio so that the width of the portion can be the width corresponding to the mask pattern. This etching is performed, for example, with Cl ₂ / He.
Reactive ion etching using a mixed gas of
Moreover, the etching is performed under the condition that the mixed gas flow rate ratio, the RF power and the pressure are determined so that the etching selection ratio between the silicon and the silicon oxide film is 2 to 4, more preferably about 2.5. . As an example, Cl ₂ /
The etching conditions include He = 30/50 sccm, RF power-100 W, and pressure 5 Pa. In this etching process, the thickness of the mask pattern 31x is 30 nm.
The silicon layer 11x has the same width as the lateral dimension of the oxide film
Remains, but the selection ratio is insufficient in the thin portion of the mask pattern 31x, so that the silicon layer 11 is formed from the side wall side.
Since x is etched, the silicon layer 11x becomes thinner than the mask pattern 31x. Specifically, the size is about half the size of the mask pattern 31x (width of about 15 nm). Therefore, the thin silicon wire 11z having the constricted portion 11y is formed in part (FIG. 7B). The advantage of setting the etching selection ratio to 2 to 4 will be described in more detail. When a silicon layer is to be etched into a fine line shape using a silicon oxide film as an etching mask and reactive ion etching using a mixed gas of Cl ₂ / He is used as the etching means, an etching mask The film thickness t, the finished dimension W _X of the silicon thin wire, and the selection ratio have a relationship as shown in FIG. That is,
In both the characteristics when the mask film thickness t is 30 nm and the characteristics when the mask film thickness t is 15 nm in FIG. 9, as the etching selection ratio increases, the thinness of the silicon thin wire decreases and becomes close to the design dimension W _0. . However, if the etching selection ratio is too large, the silicon fine line tends to become thick due to the influence of the components deposited on the sample. It can be considered that the characteristics shift to the right as the thickness of the etching mask becomes thinner (the characteristics at t = 30 nm and t in FIG. 9).
= 15 nm). In the second aspect of the invention, the width of the silicon layer 11x is set to be a new predetermined width smaller than the width of the mask pattern below the width of the mask pattern under the thinned mask pattern portion. etching selectivity striking W _0/2 in the characteristic of the t = 15 nm in FIG. 9 (approximately 2.5) it can be seen preferable. Even when the etching selection ratio is 2.5, the film thickness t of the mask pattern is
When the characteristic is 30 nm, the silicon layer 11x is finished according to the design dimension W ₀ . Further, the tendency that the width of the silicon layer below the mask pattern portion with the reduced film thickness can be reduced to less than the mask pattern width is also found under the etching conditions with the etching selection ratio of 2 to 4. Therefore, it is understood that a silicon thin wire having a constricted portion with a desired width can be formed by selecting a selection ratio from the range of the etching selectivity ratios of 2 to 4 depending on the size of the constricted portion.

When the silicon fine wire 11z having a constricted portion 11y is obtained, the sample is thermally oxidized in an O ₂ atmosphere. As shown in FIG. 8, this thermal oxidation causes the width (thickness) W ₃ of the narrowed portion 11y in the silicon thin wire 11z.
However, the thickness is set so that the electron energy level can be quantized. For example, the width (thickness) W ₃ of the constricted portion 11y of the thin silicon wire 11z is set to about 5 nm. Then, the constricted portion acts as a tunnel barrier. Therefore, the portion surrounded by the two constricted portions acts as a Si dot (portion indicated by 11zz in FIG. 8). Here, in FIG. 8, 51 is an oxide film generated by thermal oxidation. Note that the silicon thin wires are thinned by thermal oxidation here, but if the narrowed portion has a desired width (thickness) that acts as a tunnel barrier when the above etching treatment is completed, Oxidation treatment may not be performed.

According to the second aspect of the present invention, it is understood that the silicon thin line having the constricted portion which acts as a tunnel barrier can be easily formed because the silicon layer is etched by using the oxide film having a partially different thickness as a mask.

It is considered that the element capacitance C of the single electron transistor realized by the embodiment of the second invention is estimated as follows.

The size of the silicon dot is 20 nm square, and the thickness of the gate oxide film laminated on the silicon dot is 20 nm.
nm, the dielectric constant of the oxide film is 3.9, and the dielectric constant of vacuum is 8.85 × 10 ⁻¹² (F / m), the gate capacitance C
_g = 8.85 × 10 ⁻¹² × 3.9 × 20 × 10 ⁻⁹ × 20
× the ^{10 -9 / 20 × 10 -9 =} 0.7aF. If the thickness of the tunnel junction (the length of the constricted portion) is 30 nm, the area of the tunnel junction is 20 × 30 nm ² , and the dielectric constant of the oxide film is 3.9, the capacitance C _d (on the source region side and the drain region side) is C _s ) = 8.85 × 10 ⁻¹² × 3.9 × 2
0 x 10 ^-9 x 30 x 10 ^-9 / 30 x 10 ^-9 = 0.7aF
Becomes Therefore, the total capacitance C of the element is 2.1aF.
This is converted to electrostatic energy, E _C = e ² / 2C
Therefore, it becomes 38 meV. This is the heat energy at room temperature
Since the value is larger than (26 meV), it is considered that the single-electron transistor manufactured by using the method of the first invention can be expected to operate at room temperature.

In the embodiment of the second invention described above, an example in which two thin portions having a small film thickness are formed in the mask pattern to form a thin silicon wire having two constricted portions has been described. The second invention can also be applied to a case where three or more thin portions are formed in a pattern to form a thin silicon wire having three or more constricted portions.
In this way, a one-dimensional multiple (3 or more) tunnel junction array can be formed.

[0046]

As is apparent from the above description, according to the first invention of the method for forming a tunnel junction, when forming a tunnel junction having a structure in which an insulating film is sandwiched by conductive layers, a conductive layer is formed. A negative electron beam sensitive second layer is formed on the first layer for use in an electron beam, and at least the first and second regions of the second layer which are close to each other are exposed to the electron beam. The approaching portion is exposed with an exposure amount such that the electron beam energy seeps out around the approaching portion. Next, by developing the second layer, the first region, the second region and the first region of the second layer are developed.
And a third region where the energy bleeding between the second region and the third region overlaps.
Next, using the mask pattern as an etching resistant mask, the first layer is patterned to form the first to third layers.
The first layer is left in the portions corresponding to the respective regions.
Then, after removing the mask pattern, an insulating film serving as a tunnel barrier is formed between the remaining portions of the first layer. According to the first aspect of the present invention, a fine mask pattern can be obtained by positively utilizing the proximity effect of the electron beam exposure, and as a result, it is possible to accurately form a minute tunnel junction, which is difficult to achieve in the past. .

According to the second invention of the method for forming a tunnel junction, a silicon oxide film is formed on a silicon layer in forming a tunnel junction composed of a thin silicon wire partially having a constricted portion. Then, the silicon oxide film is patterned so that a part of the silicon oxide film has a band shape with a predetermined width. Then, a mask pattern made of a silicon oxide film in which the film thicknesses of these regions are reduced by removing a predetermined amount from at least two regions which are arranged at a predetermined interval in the longitudinal direction of the strip-shaped silicon oxide film portion. To form. Next, using this mask pattern as an anti-etching mask, the silicon layer is etched under etching conditions of a predetermined selection ratio to form the constricted portion under the mask pattern portion whose film thickness is reduced from the others. According to the second aspect of the invention, the mask pattern in which a part of the film thickness is reduced functions as a mask pattern capable of forming a fine constriction portion exceeding the processing limit of electron beam exposure. Therefore, it is possible to accurately form a minute tunnel junction, which has been difficult to achieve conventionally.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a structural example of a single electron transistor, in which (A) is a plan view and (B) is a cross-sectional view.

FIG. 2 is a process drawing for explaining the forming method of the first invention.

FIG. 3 is a process chart following FIG. 2 for explaining the forming method of the first invention.

FIG. 4 is a process diagram following FIG. 3 for explaining the forming method of the first invention.

FIG. 5 is a process drawing for explaining the forming method of the second invention.

FIG. 6 is a process diagram following FIG. 5 for explaining the forming method of the second invention.

FIG. 7 is a process chart following FIG. 6 for explaining the forming method of the second invention.

FIG. 8 is a process chart following FIG. 7 for explaining the forming method of the second invention.

FIG. 9 is an explanatory diagram of a forming method of the second invention, and is a diagram illustrating a relationship between a finished dimension of a silicon thin wire, an etching mask film thickness, and an etching selection ratio.

[Explanation of symbols]

11: Silicon substrate 11a: Silicon wafer having an embedded silicon oxide film 11x: Silicon layer (first layer for forming a conductive layer) 11y: Constricted portion 11z: Silicon fine line 11zz: Silicon dot 13: Insulating film 15a : Source region 15b: Drain region 15c: Minute islands (dots, central conductive layer) 17a, 17b: Insulating film 17c serving as a tunnel barrier: Gate insulating film 19: Control gates 21a, 21b: Tunnel junction 31: Oxide film ( Intermediate layer) 31a: Oxide film pattern 31x: Mask pattern (a part of thin silicon oxide film pattern) 31y: Thinned part 33: Negative electron beam exposure resist layer (second layer) Layer) 33a: first region 33b: second region 33c: third region 33x: of electron beam energy Look out region 33y resist pattern (mask pattern) 41: electron beam exposure resist layer 41a: resist pattern 43: resist pattern 51: oxide film

Claims (5)

(57) [Claims] 1. When forming a tunnel junction having a structure in which an insulating film is sandwiched by conductive layers, an electron beam is exposed on the first layer for forming the conductive layer, either directly or through an intermediate layer. Forming a second layer having a property that the exposed portion remains, and the approaching first region and second region in the second layer, respectively, by an electron beam and at least the approaching region. The exposed portion is exposed with an exposure amount such that the electron beam energy is exuded around the exposed portion, and by developing the exposed second layer, the second
Obtaining a mask pattern of the first region, the second region, and the third region of the layer where the energy bleeding between the first and second regions overlaps. And directly or indirectly patterning the first layer using the mask pattern as an etching resistant mask to leave the first layer in a portion corresponding to each of the first to third regions. And a step of forming an insulating film serving as a tunnel barrier between the remaining portions of the first layer after removing the mask pattern. 2. The method for forming a tunnel junction according to claim 1, wherein each of the first region and the second region has a convex shape on the side closer to the other region toward the other region. A method for forming a tunnel junction, characterized in that the region has a flat shape. 3. A step of forming a silicon oxide film on a silicon layer in forming a tunnel junction composed of a silicon thin wire partially having a constricted portion, and the step of forming the silicon oxide film partially in a predetermined width. A step of patterning into a strip shape, and a predetermined amount of at least two regions lined up at a predetermined interval in the longitudinal direction of the strip-shaped silicon oxide film portion are removed from the surface by a predetermined amount to reduce the film thickness of these regions more than others. A step of forming a mask pattern made of the silicon oxide film formed, and the width of the silicon layer portion under the mask pattern portion whose film thickness is reduced from the other can be set to a new predetermined width less than the predetermined width after etching, Moreover, the silicon layer is etched under the etching condition of the selection ratio that allows the width of the other silicon layer portion to be the width corresponding to the mask pattern. The method for forming a tunnel junction, characterized in that it comprises a step of film thickness to form the constricted portion under the mask pattern portion which is reduced than the other. 4. The method for forming a tunnel junction according to claim 3, wherein the selection ratio is a value in the range of 2 to 4. 5. The method for forming a tunnel junction according to claim 4, further comprising an oxidation step for oxidizing the surface layer portion of the silicon layer to further narrow the constricted portion after the etching step of the silicon layer. A method for forming a tunnel junction characterized by the above.