JP3488059B2 - Interrupt address extension circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to an interrupt address extension circuit, and more particularly, to an interrupt address extension circuit which can have a plurality of interrupt addresses for the same interrupt request destination. The present invention relates to an interrupt address extension circuit that can perform another interrupt processing. 2. Description of the Related Art At present, one interrupt request signal is assigned to each functional unit, and an interrupt address is currently one address for each interrupt request signal. Therefore, if a plurality of interrupt addresses can be assigned to one interrupt request signal, it is possible to give an interrupt process for each processing content to a functional unit operating in a time-division manner. FIG. 4 shows an interrupt control circuit described in JP-A-63-142434. In FIG. 4, reference numeral 50 denotes an interrupt mapping register, which shows an example in which the register capacity is 8 bits. _161-164 is an interrupt address register. These registers 50, 1
6 _{1-16 4} is connected to the data bus 21. 24
Is a decoder circuit connected to the 2-bit interrupt line 20,
A selector circuit 52 selects and outputs the contents of the interrupt mapping register 50 based on the output of the decoder circuit 24. Reference numeral 18 denotes an interrupt address selection circuit for selecting one of the interrupt address registers 16 _{1 to} 16 _{4 based on} the output of the selector circuit 52 and outputting the interrupt address. The circuit 18 is connected to an output address bus 22. By configuring the interrupt control circuit in this way, it is possible to variably set the interrupt address 22 for the same interrupt code 24. This is the interrupt code 2 decoded by the decoder circuit 24.
4 in the interrupt mapping register 50 by the selector circuit 52 responding to the 4-bit decode signal 23
This is because _one of the interrupt address registers 16 _{1 to} 16 ₄ is output as the interrupt address 22 by the interrupt address selection circuit 18 in accordance with the 2-bit signal 25. However, as apparent from the above description, the setting of a selectable interrupt address for an interrupt code is handled by having a plurality of interrupt address registers. In this configuration,
A large number of signals (interrupt address register × the number of selections × the number of bits of the interrupt address register) are concentrated in the interrupt address selection circuit, and there is a problem that the wiring area becomes large on the layout. Also, when the number of interrupts increases, each has an interrupt address register, which causes a problem that the scale of the circuit increases. Further, in the conventional example, the interrupt address can be switched but cannot be increased. An object of the present invention is to provide an interrupt address variable setting circuit which has a small circuit size and can set a plurality of interrupt addresses for one interrupt request. An interrupt address extension circuit according to the present invention receives an interrupt request signal and receives an interrupt request signal.
Output the pre-extension interrupt address according to the request signal
Interrupt control means and input from the address / data bus.
Hold part of the pre-extension interrupt address
Output address change data storage means and interrupt before expansion
Lower address bits, address change data
Extended interrupt address with the output from the storage means as upper bits
Address to generate address and output to address / data bus
And a built-in address generation unit . FIG. 1 is a block diagram of an interrupt address extension circuit according to an embodiment of the present invention. Referring to FIG. 1, the interrupt address extension circuit and its peripheral parts
An interrupt control means 101 for generating an interrupt address before expansion corresponding to an interrupt request destination by an external interrupt request signal 109, a command unit 108, and an interrupt address extension from the address / data bus 107 when instructed by the command unit 108 Address change data storage means 102 for inputting and holding bits, an interrupt address before extension output from interrupt control means 101 and an interrupt address extension bit 1 output from address change data storage means 102
05 and synthesized, and the interrupt address request signal 1
The extended interrupt address 106 is set to address /
And an interrupt address generating means for outputting to the data bus 107. These are assumed to be built in the CPU. The address / data bus 107 becomes an address bus or a data bus in a time division manner, and is connected to a register group including an instruction pointer (not shown). The main processing unit of the program performs a time sharing operation. When the processing of the main processing unit of the program is switched, a command for switching the processing or an instruction included in the switched program causes the command unit 10 to execute the command.
8 causes the address change data storage means 102 to fetch an interrupt address extension bit from the address / data bus 107. At this time, the data of the interrupt address extension bit is output from the register having the register group to the corresponding bit of the address / data bus 107 by the above-mentioned instruction. As a result, the address extension bit changes, and a different extended interrupt address 1 is assigned to the same pre-extended interrupt address 104 corresponding to the same interrupt request destination.
06 is generated by the interrupt address generation means 103 and output to the address / data bus 107 in accordance with the request of the interrupt address request signal 110. This extended interrupt address 106 is taken into the instruction pointer, and the extended interrupt request service routine is started therefrom. A CPU instruction for outputting an interrupt address extension bit from a register in a group of registers and, at the same time, loading it into the address change data storage register 102 must be added to the instruction set. FIG. 2 is a block diagram showing an interrupt address extension circuit according to a first embodiment of the present invention. In the present embodiment,
The address / data bus 107 is 8 bits wide, the interrupt request signal is represented by 8 types and 3 bits.
It is assumed that the three bits up to are valid. Although bits 5 to 7 are connected, it is assumed that the interrupt control means 101 sets all the values of these bits to 0 and outputs them. Bits 3 and 4 are interrupt address extension bits. This is because the address change data storage register 10
2A is obtained by taking the values of bit 0 and bit 1 of the address / data bus 107 into the internal latch at the timing specified by the signal WR from the command unit 108. However, bit 0 and bit 1 described above may be bits at other positions. When an interrupt request is issued, the other parts of the CPU operate in the same manner as in the prior art, except that an extended interrupt address is output to the address / data bus 107.
From the extended interrupt address, the extended interrupt request service routine there can be executed. Assuming that the symbols of the interrupt request signal are A to H, the correspondence between the interrupt request signal and the interrupt address is as shown in Table 1 unless the interrupt address is expanded according to the present embodiment. [Table 1] On the other hand, when the extension of the interrupt address according to the present embodiment is performed, the correspondence between the interrupt request signal and the interrupt address is as shown in Table 2. [Table 2] Referring to Table 2, for example, for the interrupt request signal A, the extended interrupt address takes four values of 00H, 08H, 10H, and 18H depending on the value of the address change data storage register. The address change data storage register 1
02A is reset by a RESET signal generated when the CPU is turned on or when the CPU is reset. Therefore, if the instruction for changing the interrupt address according to the present invention is not executed, a conventional interrupt address is generated, so that backward compatibility is maintained. In this embodiment, the interrupt request signal 1
Although the number of bits 09 is eight, if the number of interrupt signals is nine to sixteen, bits 0 to 3 of the input of the interrupt address generation circuit 103A are set as inputs from the interrupt control means 101, and the input of the interrupt address generation circuit 103A is set. The fourth and fifth bits may be input from the address change data storage register 102. If the number of interrupt signals is 17 to 32, bits 0 to 4 of the input of the interrupt address generation circuit 103A are set as inputs from the interrupt control means 101, and the fifth bit of the input of the interrupt address generation circuit 103A is used as the input. The sixth bit may be input from the address change data storage register 102A. In this embodiment, the number of extension of the interrupt address is set to 4. However, if it is desired to increase the number to 8, the number of bits of the interrupt address generation circuit 102A is set to 3
This output is output to the interrupt address generation circuit 103
What is necessary is just to comprise so that it may input to bit 5 of bit A of A. Embodiment 2 FIG. 3 shows Embodiment 2 of the present invention. The difference from the first embodiment is that data for controlling whether or not to change the address is stored in the seventh bit of the address change data storage register 102B. The data holding timing is the same as that of the address change data register 102A in FIG. 2, but the configuration is such that the RESET signal is not input to the bit 1 and bit 0 latches, and the initialization function by the RESET signal is added only to the bit 7 latch. Is done. The RESET signal is generated when the power of the CPU is turned on or when the CPU is reset. The initial value of the bit 7 latch is set to “0”. Next, the interrupt address generation circuit 103B determines whether bit 3 and bit 4 are set to 0 or bit 0 and bit 1 of the address change data register 102B by bit 7 of the address change data register B. . Table 3 shows a correspondence table between the interrupt signals and the interrupt addresses in the circuit of this embodiment. [Table 3] Since it is possible to select whether to generate a new address by using the interrupt address change data based on the value of the seventh bit of the address change data storage register 102B, software resources that have been conventionally used can be effectively used. The configuration of the address change data storage register 102B may be arbitrarily set without following this embodiment. In the present embodiment and the first and second embodiments, the output of the interrupt address generating means is directly used as the interrupt address at which the interrupt service routine starts. Instead, the start address of the 8-bit interrupt service routine is used. Can be used as a vector address for designating the storage area of the above, or this output can be shifted up by one bit to be used as an interrupt vector address for designating the storage area of the 16-bit interrupt start address. As described above, according to the present invention, a plurality of interrupt addresses can be generated for the same interrupt request destination. Further, a signal processing device that performs a time-division process including a CPU having the same up to an interrupt process,
It can be used as an information processing device. In comparison with the conventional example described in JP-A-63-142324, in the conventional example, the interrupt signal 1
Although four registers are required for the book (the number of interrupt signals × 4 registers), the present invention can provide the same effect as that of the known example only by adding one register. Also,
In the present invention, since the number of added circuits (registers) is small, the number of man-hours for improving the circuit can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an address extension circuit and its peripheral configuration according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of an address extension circuit according to the first embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration of an address extension circuit according to a second embodiment of the present invention. FIG. 4 is a block diagram showing a configuration of an interrupt control system according to a conventional example. DESCRIPTION OF SYMBOLS 101 Interrupt control means 102 Address change data storage means 102A, 102B Address change data storage register 103 Interrupt address generation means 103A, 103B Interrupt address generation circuit 104 Pre-extension interrupt address 105 Interrupt address extension bit 106 Extended interrupt address 107 Internal address / data bus 108 Command unit 109 Interrupt request signal 110 Interrupt address output request signal

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Claims (1)

(57) [Claim 1] An interrupt request signal is input and the interrupt
Assignment to output pre-extension interrupt address according to request signal
Interrupt control means, and the pre-expansion interrupt input from an address / data bus.
Address that retains and outputs part of the address
Change data storage means, and the bits of the pre-expansion interrupt address are
The output from the address change data storage means is
To generate an extended interrupt address
/ Interrupt address extension circuit and interrupt address generating means, characterized in that it comprises to be outputted to the data bus.