JP3488631B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having an automatic write function and using a potential obtained by boosting a power supply voltage at the time of writing.

[0002]

2. Description of the Related Art In a semiconductor memory device having an automatic write function, for example, a flash EEPROM, a command for recognizing a write mode is input to a memory cell at an input address, and the input data is set to a predetermined value. It is possible to write while automatically determining the threshold voltage. Here, a memory cell which has been written and has a high threshold voltage is defined as “0”, and a memory cell having a low threshold voltage is defined as “1”.

FIG. 18 is a block diagram showing a schematic circuit configuration of a conventional flash EEPROM having the automatic write function. In FIG. 18, reference numeral 11 denotes a memory cell array. Rows of memory cells in the memory cell array 11 are selected by the row decoder 12, and columns of memory cells are specified by the column decoder 13. The address signal is the address register 14 and the multiplexer 15.
And the command register 16 respectively. The output signal of the address register 14 is the multiplexer 15
The selection signal from the multiplexer 15 is supplied to the row decoder 12 and the column decoder 13. The data of the memory cell selected by the row decoder 12 and the column decoder 13 is stored in the sense amplifier 1
I / O buffer 1 supplied to 7 and sensed and amplified
It is read out via 8. On the other hand, the I / O buffer 1
The write data input to 8 is stored in the data register 19
The data latched in the data register 19 is written into the memory cell selected by the row decoder 12 and the column decoder 13 via the write data generation circuit 20 and the write switch 21. The output signal of the sense amplifier 17 is supplied to the write data generation circuit 20 to control the write data generation.

A control signal and a command are input to the command register 16, and the output signal of the command register 16 is supplied to the data register 19 and the control circuit 22. The control circuit 22 controls the operation mode and various controls of the flash EEPROM according to the control signal and command supplied to the command register 16. The output signal of the control circuit 22 controls the timer 23 and the power supply circuit (the booster circuit). ) 24 and verify circuit 2
5 etc. are controlled. The timed output from the timer 23 is supplied to the control circuit 22. The power supply circuit 24
Supplies a high voltage for writing to the row decoder 12, the column decoder 13, the write data generation circuit 20, the write switch 21, etc. by level shifting (boosting) the power supply voltage. The verify circuit 25 receives the output signal of the write data generation circuit 20 and supplies the verification result to the control circuit 22.

In the above configuration, when a write command is input, the command register 16 recognizes the write mode, the data input to the I / O buffer 18 is input to the data register 19, and the address signal is input to the address register 14. Hold each. Multiplexer 15
Selects the address signal held in the address register 14 and supplies it to the row decoder 12 and the column decoder 13. Then, the row address signal is transferred to the row decoder 1
At 2, the column address signal is decoded by the column decoder 13 to select the memory cell of the input address.

When the command register 16 receives the establishment signal, the control circuit 22 starts the operation, the inside enters the write verify state, and after the setup time set in the timer 23 has passed, the data of the memory cell in which the writing is carried out. Is read and compared with the input data. As a result of this comparison, if the written data and the read data match, it is determined that sufficient writing has been performed, and the write operation ends, and if they do not match, the write data (input data is "0" , And only the bit whose read data is “1” is the target of rewriting), and rewriting is started.

That is, as shown in the flow chart of FIG. 19A, when the write verify operation is started, the write verify setup is performed (step 1), and the write verify read is performed after the power supply setting period of about 1 μS. Is performed (step 2). Next, it is compared whether or not the input data and the read data match (step 3), and if they match, the read setup (step 4) is performed and the process ends.
On the other hand, when they do not match, it is determined whether or not the number of rewriting cycles has reached the limit (step 5). (Step 6). Input data in this step 6,
The read data and the write data have a logical relationship as shown in FIG. Next, writing is performed (step 7). In this writing, the voltage applied to the memory cell is the power supply voltage _VDD (for example, 3V).
It is a high voltage generated by boosting at 4, and as shown in the timing chart of FIG. 20, for example, 10 V is applied to the control gate (word line) and 5 to 6 V is applied to the drain (bit line) of the selected cell transistor. It The method of writing to this cell transistor is hot electron injection, and the drain current is required to be about 500 μA / 1 bit. Writing is continued for a writing time set in the timer 23, for example, about 5 μS. After that, 1 is added to the number of cycles (step 8), and then step 1
Then, the write verify operation is repeated until the input data matches the read data. Then, if the two data do not match even after reaching the preset limit number of times, it is determined to be defective (step 9), the read setup (step 4) is performed, and the process ends.

By the way, all the currents required for the above-mentioned write verification are supplied to the power supply circuit (boosting circuit) 24.
Since it is supplied from the memory cell, a current that is twice as efficient as the current consumed by the memory cell is required. Further, assuming that the output voltage of the power supply circuit 24 is constant, the lower the power supply voltage V _DD boosted by the power supply circuit 24, the lower the boosting efficiency. Normally, the current supply capacity of the power supply circuit 24 is almost proportional to the area of the capacitor of the charge pump circuit provided inside the power supply circuit 24, so the output potential (boosted potential) at the time of writing to the memory cell is changed. Without lowering the power supply voltage _VDD , the area of the capacitor needs to be increased by the amount of decrease in the current supply capability of the power supply circuit 24, which leads to an increase in the chip area.

[0009]

As described above, the conventional semiconductor memory device having the automatic write function and utilizing the high voltage obtained by boosting the power supply voltage at the time of writing, when the power supply voltage is lowered, the high voltage for writing is applied. There is a problem in that the current supply capability of the booster circuit that occurs decreases and the writing time becomes long.

When the power supply voltage is lowered,
There is a problem in that the area of the capacitor needs to be increased by the amount corresponding to the decrease in the current supply capability of the booster circuit, which increases the area occupied by the chip.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device capable of suppressing an increase in write time when the power supply voltage is lowered.

Another object of the present invention is to provide a semiconductor memory device capable of lowering the power supply voltage without increasing the chip occupation area.

[0013]

According to another aspect of the present invention, there is provided a semiconductor memory device having an automatic write function, which boosts the power supply voltage in a semiconductor memory device which uses a potential obtained by boosting the power supply voltage at the time of writing. And a bit line write switch for controlling whether or not input data is supplied to the bit line at the time of writing data by selectively turning on / off the voltage boosting means for generating a high voltage for writing. A write division control means for shifting the selection timing of the lines and performing the write in a plurality of times,
Writing means for writing data by applying the high voltage output from the boosting means to the memory cells connected to the bit line selected by the writing division control means ;
The memory cell to be written by the writing means
Select the first bit line after boosting the voltage
Set for controlling the write division control means to perform
It is characterized in that the up means is integrated in a single chip .

According to a second aspect of the present invention, in the semiconductor memory device of the first aspect, the setup means is used.
Has a timer that measures the set up time.
Including the setup time set in the timer.
The first write operation by the write division control means.
It is characterized in that it is controlled so as to select the input line .

According to a third aspect of the present invention, in the semiconductor memory device according to the first or second aspect, the selection times of the bit lines selected by the write dividing means divided a plurality of times are substantially equal to each other. Is characterized by.

According to a fourth aspect of the present invention, the semiconductor memory device according to any one of the first to third aspects further comprises a power supply voltage detecting means for detecting a power supply voltage boosted by the boosting means. The control method is changed based on the level of the power supply voltage detected by the voltage detection means.

Further, as described in claim 5, in the semiconductor memory device according to any one of claims 1 to 3, a power supply for detecting a power supply voltage boosted by the boosting means before writing data. It is characterized by further comprising voltage detecting means, and increasing the number of divisions by the write division control means when the level of the power supply voltage detected by the power supply voltage detecting means is low, and decreasing the number of divisions when the level is high.

According to a sixth aspect of the present invention, the semiconductor memory device according to any one of the first to third aspects further comprises a power supply voltage detection means for detecting a power supply voltage boosted by the boosting means, and automatic writing is performed. Immediately after the start of, the power supply voltage detection means detects the power supply voltage, the number of divisions by the write division control means is increased when the level of the detected power supply voltage is low, and the number of divisions is decreased when the level is high. .

Further, as described in claim 7, the semiconductor memory device according to any one of claims 1 to 3 further comprises control data storage means for storing a control method, and the control data storage means. The control method is changed based on the control method stored in.

As described in claim 8, in the semiconductor memory device of claim 7, the control data storage means is EE.
A PROM cell is provided, and the control data is stored in this EEPROM cell.

According to a ninth aspect of the present invention, the semiconductor memory device according to any one of the first to third aspects further comprises division number storage means for storing the number of divisions by the write division control means. The number of divisions by the write division control means is changed based on the number of divisions stored in the number storage means.

According to a tenth aspect of the present invention, in the semiconductor memory device of the ninth aspect, the division number storage means is EEP.
The EEPROM cell is characterized in that the number of divisions is stored in this EEPROM cell.

Further, as described in claim 11, in the semiconductor memory device according to any one of claims 1 to 3, the write division control means controls the number of divisions based on a test signal. And

According to the structure of the first aspect, when the power supply voltage drops, the write division control means shifts the bit line selection timing, so that the number of bits to be written at a time can be reduced and the current consumption can be reduced. It is possible to compensate for the decrease in the current supply capability of the boosting means and suppress the increase in the writing time. Further, the power supply voltage can be lowered without increasing the chip occupation area. Further, in order to widen the range of the power supply voltage and shorten the writing time in the acceleration test, the number of bits selected at one time can be increased at the time of high voltage input, so that the writing time can be prevented from increasing. . Also, after boosting the word line is completed,
Select the output line to reduce variations in writing characteristics.
Wear.

Further, as set forth in claim 2, the set
As a means to upgrade, set up time
A timed timer can be used.

As described in claim 3, if the selection time of each bit line is made equal, the variation of the write characteristic can be reduced.

By detecting the power supply voltage and changing the control data as described in claim 4, it is possible to adopt an optimum control method according to the power supply voltage, and it is possible to shorten the write time and the test cost.

Further, as described in claim 5, if the power supply voltage is detected and the number of divisions is changed, an optimum control method according to the power supply voltage can be adopted, and the writing time and the test cost can be reduced. .

By detecting the power supply voltage immediately after the automatic writing as described in claim 6, even if the power supply voltage changes during the writing operation, the optimum control method according to the power supply voltage can be adopted, and the writing operation can be performed. It is possible to reduce time and test cost.

Furthermore, as described in claim 7, if the control method is changed based on the control method stored in the control data storage means, the writing time can be shortened by the optimization of the writing time, and the test cost can be reduced. Also, the yield can be improved by trimming the writing characteristics.

As described in claim 8, the control data is stored in, for example, an EEPROM cell.

If the division method is changed based on the number of divisions stored in the number-of-divisions storage means, the write time can be optimized and the test cost can be reduced.

As described in claim 10, the number of divisions is
For example, it is stored in an EEPROM cell.

Furthermore, as described in claim 11, if the number of divisions is controlled based on the test signal, the write time can be shortened and the test cost can be reduced by optimizing the write time.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is for explaining a semiconductor memory device according to a first embodiment of the present invention, and is a schematic circuit of a flash EEPROM having an automatic write function. It is a block diagram which shows a structure. The row of memory cells in the memory cell array 11 is selected by the row decoder 12, and the column of memory cells is specified by the column decoder 13. The address signal is supplied to the address register 14, the multiplexer 15, the write division control circuit 26, and the command register 16, respectively. The output signal of the address register 14 is supplied to the multiplexer 15, and the address signal selected by the multiplexer 15 is supplied to the row decoder 12 and the column decoder 13. The data of the memory cell selected by the row decoder 12 and the column decoder 13 is supplied to the sense amplifier 17, sensed and amplified, and read via the I / O buffer 18. On the other hand, the I / O buffer 1
The write data input to 8 is stored in the data register 19
The data latched in the data register 19 is written into the memory cell selected by the row decoder 12 and the column decoder 13 via the write data generation circuit 20 and the write switch 21. Further, the write data generation circuit 20 has
The output signal of the sense amplifier 17 is supplied to control write data generation.

A control signal and a command are input to the command register 16, and the output signal of the command register 16 is supplied to the data register 19 and the control circuit 22. The control circuit 22 controls the operation mode and various controls of the flash EEPROM according to the control signal and command supplied to the command register 16. The output signal of the control circuit 22 controls the timer 23 and the power supply circuit (the booster circuit). ) 24 and verify circuit 2
5 etc. are controlled. The time output by the timer 23 is output by the control circuit 22 and the write division control circuit 2
6 is supplied. The output signal of the write division control circuit 26 is supplied to the write data generation circuit 20. The power supply circuit 24 includes a booster circuit, and level shifts (boosts) the power supply voltage to boost the row decoder 1.
2, column decoder 13, write data generation circuit 20
And a high voltage for writing is supplied to the write switch 21. The verification circuit 25 receives the output signal of the write data generation circuit 20 and supplies the verification result to the control circuit 22.

FIG. 2 shows the flash EE shown in FIG.
In the PROM, which shows a main part directly related to the present invention, the memory cell array 11, the row decoder 12, the column decoder 13 in the circuit shown in FIG.
The sense amplifier 17, the write data generation circuit 20, the write switch 21, and the power supply circuit 24 are extracted to partially show the circuit configuration in detail. Power supply circuits 24-1, 24-
Reference numeral 2 corresponds to the power supply circuit 24 in the circuit shown in FIG. 1, and a charge pump circuit is provided in each of the power supply circuits 24-1 and 24-2. The power supply circuit 24
The output voltage of −1 is supplied to the row decoder 12, the column decoder 13 and the write data control circuit 20. As a result, when writing data, the row decoder 1
2, column decoder 13 and write data control circuit 2
The output voltage of 0 is a high voltage, for example, 10V.
Further, the high voltage output from the power supply circuit 24-2 is applied to the MOS transistors S0 to S0 constituting the write switch 21.
It is supplied to one end of the current path of S15. The output signals of the write data control circuit 20 are supplied to the gates of the MOS transistors S0 to S15, respectively, and are selectively turned on / off. The MOS transistor S
Column selection transistors Q0 to Q15 are provided between 0 to S15 and the bit lines BL0 to BL15, respectively, and are selectively turned on / off by an output signal of the column decoder 13. The MOS transistors S0 to S1
The input terminal of the sense amplifier is connected to the connection point between the column selection transistor 5 and the column selection transistors Q0 to Q15, and the data read from the memory cell onto the bit line is supplied through the column selection transistor. Each of the above bit lines BL0-B
A memory cell (EEP) is connected between L15 and the ground point V _SS.
ROM cells) MC, MC, ... Are connected to each memory cell MC, MC ,.
Are connected line by line. The memory cell array 11 is an I / O
It has a 16-bit configuration of 0 to I / O15.

FIG. 3A shows the data register 19, the write data generating circuit 20, the verify circuit 25 and the write switch 2 in the circuits shown in FIGS.
The detailed configuration example of 1 is shown focusing on the i-th bit.
The data register 19 includes NOR gates 30 and 31, inverters 32 and 33, and a P-channel type MOS transistor 3.
4, 35 and N-channel type MOS transistors 36, 3
It is composed of 7. A signal DIN for operation control is supplied from the command register 16 to one input end of the NOR gate 30.
EN is supplied to the other input terminal of the I / O buffer 18
To i-th I / O data IOPADi. The output signal of the NOR gate 30 is the inverter 32.
Is supplied to one end of the current path of the MOS transistors 34 and 36 via. These MOS transistors 34, 36
At the other end of the current path of
One end of the current path of the above is connected to one input end of the NOR gate 31. A reset signal RST is supplied from a power-on reset circuit (not shown) to the other input end of the NOR gate 31, and its output signal is supplied to the other ends of the current paths of the MOS transistors 35 and 37 via the inverter 33. It The data latch signal DL from the control circuit 22 is applied to the gates of the MOS transistors 34 and 37.
And the inverted signal / DL of the data latch signal DL is supplied to the gates of the MOS transistors 36 and 35.

The write data generation circuit 20 includes NOR gates 40 to 43, clocked inverters 44 and 45,
The NAND gates 46 to 48 and the inverters 49 to 51 are included. The output signal DINLATi of the NOR gate 31 in the data register 19 is
0 and 42, and one input terminal of the NAND gate 48, respectively. I of the sense amplifier 17
The output signal SAOi of the bit is supplied to the other input end of the NAND gate 48 and the other input end of the NOR gate 42 via the inverter 50. The output signal of the NAND gate 48 is supplied to one input terminal of the NOR gate 43 through the inverter 51, and the NOR gate 4 outputs the signal.
The output signal of 2 is supplied to the other input terminal of the NOR gate 43. Output signal VERIOK of the NOR gate 43
i is supplied to the other input end of the NOR gate 40. The output signal of the NOR gate 40 is supplied to the input terminal of the clocked inverter 44, and the output signal of the clocked inverter 44 is supplied to one input terminal of the NOR gate 41. The reset signal RST is supplied to the other input terminal of the NOR gate 41, and the output signal is supplied to the input terminal of the clocked inverter 45 and one input terminal of the NAND gate 46. The output signal of the inverter 45 is supplied to one input terminal of the NOR gate 41. The clocked inverters 44 and 45 operate in response to the data latch clock DLK supplied from the control circuit 22 and its inverted signal / DLK. The write division control circuit 2 is provided at the other input terminal of the NAND gate 46.
The i-th bit division control signal PEi output from 6 is supplied. The i-th bit data latch signal DLATi output from the NAND gate 46 is output from the inverter 49.
And is supplied to one input terminal of the NAND gate 47 via. At the other input terminal of the NAND gate 47, a signal P indicating the write mode output from the control circuit 22 is output.
RGMD is supplied.

The verify circuit 25 comprises a NAND gate 60 and an inverter 61. The output signal VERIOKi of the NOR gate 43 is supplied to one input terminal of the NAND gate 60, and the output signal COM of the verify circuit of the "i-1" th bit is supplied to the other input terminal.
P (i-1) is supplied. The output signal of the NAND gate 60 is sent to the comparison result signal COM via the inverter 61.
It is supplied to the control circuit 22 as Pi.

The write switch 21 includes P-channel type MOS transistors 70 to 72 and an N-channel type MO transistor.
It is configured to include S transistors 73 to 77 and an inverter 78. MOS transistors 70, 71, 72
1 supplied from the power supply circuit 24 to one end of the current path of
A boosted potential VSWC of about 0V is applied. Above MOS
The other end of the current path of the transistor 70 is connected to one end of the current path of the MOS transistor 73 and the MOS transistor 71.
Connected to the gate. The other end of the current path of the MOS transistor 71 is connected to one end of the current path of the MOS transistor 74 and the gate of the MOS transistor 70. The other ends of the current paths of the MOS transistors 73 and 74 are connected to the ground point V _SS . The output signal of the NAND gate 47 in the write data generation circuit 20 is the MO signal.
It is supplied to the gate of the S transistor 73 and the input terminal of the inverter 78. The output signal of the inverter 78 is supplied to the gate of the MOS transistor 74. The other end of the current path of the MOS transistor 72 is connected to one end of the current path of the MOS transistor 75, and the other end of the current path of the MOS transistor 75 is connected to the ground point V _SS . The gates of these MOS transistors 72 and 75 are M
The OS transistors 71 and 74 are commonly connected to the connection point of the current paths to form a CMOS inverter. M above
The boosted potential VDOF of about 8V output from the power supply circuit 24 is applied to one end of the current path of the OS transistor 76, and the boosted potential VSWBS is applied to the gate. This boosted potential VSWBS is "6V + threshold voltage of MOS transistor 76". The other end of the current path of the MOS transistor 76 is connected to one end of the current path of the MOS transistor 77.
The gate of 7 is connected to the connection point of the current paths of the MOS transistors 72 and 75. The potential DLINEi at the other end of the current path of the MOS transistor 77 is supplied to the drain of the selected cell transistor.

The signals DINLATi, SAOi, VERIOKi and DL in the circuit shown in FIG.
Each ATi has a logical relationship as shown in FIG. That is, the signal D output from the NOR gate 31
When INLATi and the output signal SAOi of the sense amplifier match, the signal VERIOKi becomes "1" level, and it is detected that the input data and the read data match. Further, the output signal DLAT of the NAND gate 46
i becomes “1” level when the signal DINLATi and the signal SAOi match, and becomes “1” level when the input data and the read data do not match and the input data is “1” level, and rewriting is performed. It is used to control the write switch 21 for.

FIG. 4 shows the entire (16-bit) circuit of the verify circuit 25 shown in FIG. 0-1
The signals VERIOK0 to VERIOK15 supplied from the write data generation circuit 20 of the fifth bit are respectively
It is supplied to one input terminal of the NAND gates 60-0 to 60-15. The power supply voltage _{VDD is} supplied as fixed data of "1" level to the other input terminal of the first-stage NAND gate 60-0, and the output signal of the NAND gate 60-0 is supplied to the NAND gate 60-1 via the inverter 61-0. Is supplied to the other input terminal of the. Below, Nand Gate 60-1
The output signals of 60 to 15-15 are inverters 61-1 to 61-
The signal is sequentially supplied to the next stage via 15 and the coincidence signal VERIOK is obtained from the final stage inverter 61-15. The match signal VERIOK becomes "1" level when all 16-bit signals VERIOK0 to VERIOK15 match the input data.

FIG. 5 is a circuit diagram showing a detailed structure of the write division control circuit 26 in the circuit shown in FIG. This circuit includes NAND gates 81 to 97, inverters 98 to 106, NOR gates 107 to 114, and binary counters 115 to 117. The signal DS0 is supplied to the first input terminal of the NAND gate 81, and the output signals TCUT4, TCUT3, TCUT1 of the timer 23 are supplied to the second to fourth input terminals thereof, respectively. The output of the NAND gate 81 is the NAND gate 8
2 and the output signal of the NAND gate 82 is supplied to one input terminal of the NAND gate 83. At the other input end of the NAND gate 83, a signal PRG indicating the write mode output from the control circuit 22 is output.
MD is supplied, and the output signal of the NAND gate 83 is supplied to the other input end of the NAND gate 82, the input end of the inverter 98, the first input end of the NOR gate 107 and one input end of the NOR gate 111. The output signal of the inverter 98 is supplied to the first input terminal of the NAND gate 84 and one input terminal of the NAND gate 85. The other input end of the NAND gate 85 is connected to the signal PRG.
MD is supplied. The output signal TC of the timer 23 is supplied to the second to fourth input terminals of the NAND gate 84, respectively.
UT5, TCUT3, TCUT2 are supplied respectively,
The output signal of the NAND gate 84 is supplied to one input terminal of each of the inverter 99 and the NOR gate 110. The output signal GCLK of the timer 23 is supplied to the other input terminal of the NOR gate 110, and the output signal of the NOR gate 110 is supplied to one input terminal of the NOR gate 112. The output signal GCLK of the timer 23 is supplied to the second input terminal of the NOR gate 107, and the output signal TCUT of the timer 23 is also supplied to the third input terminal.
1, the output signal of the NOR gate 107 is supplied to one input terminal of the NOR gate 108. The output signal of the NOR gate 108 is supplied to one input terminal of the NOR gate 109. The signal PRGMD is supplied to the other input end of the NOR gate 109 via the inverter 102, and the output signal thereof is supplied to the other input end of the NOR gate 108 and the other input end of the NOR gate 111, respectively. The output signal of the NOR gate 111 is supplied to the other input terminal of the NOR gate 112, and this NOR gate 1
A signal / PTRST is output from 12.

The output signal of the inverter 99 is supplied to the input terminal / CI1 of the binary counter 115 and the input terminal CI1 via the inverter 100. Output terminals CI, / CI of the binary counter 115
Are input terminals CI1, / of the binary counter 116, respectively.
The output terminals CI and / CI of the binary counter 116 are connected to CI1 and the input terminals CI1 and / CI1 of the binary counter 117, respectively. The output signals of the NAND gate 85 are supplied to the reset input terminals RST of the binary counters 115 to 117, respectively. The output signal PECUTO output from the output terminal CI of the binary counter 115 is supplied to one input terminal of the NOR gate 114, one input terminal of the NAND gates 91 and 93, and the input terminal of the inverter 106, respectively. Also,
The output signal PECUT1 output from the output end CI of the binary counter 116 is supplied to one input end of the NAND gates 86 and 88 and the input end of the inverter 104. Further, the output terminal of the binary counter 117 / CI
The output signal / PECUT2 output from is supplied to one input end of the NAND gate 87. The signal DS1 is fed to the inverter 101 at the other input terminal of the NAND gate 86.
The output signal of the NAND gate 86 is supplied to the other input terminal of the NAND gate 87. Then, the NAND gate 87 outputs the signal PETEND.

The output signal of the NAND gate 85 is supplied to one input terminal of the NOR gate 113, and the output signal PTEND of the NAND gate 87 is supplied to the other input terminal thereof. Is supplied to one of the input terminals. The signal DS1 is supplied to the other input terminal of the NAND gate 88, and the output signal of the NAND gate 88 is supplied to the inverter 10
The signal is supplied to the other input terminal of the NOR gate 114 and the input terminal of the inverter 105 via the input terminal 3. Inverter 1
The output signal of 04 is supplied to the other input terminal of the NAND gate 89, and the output signal of this NAND gate 89 is supplied to the other input terminal of the NAND gate 93 and the second input terminal of the NAND gate 92. The output signal of the inverter 105 is supplied to the other input terminal of the NAND gate 91, and the output signal of the inverter 106 is supplied to the third input terminal of the NAND gate 92. The output signals of the NAND gates 90 to 93 are respectively supplied to one input ends of the NAND gates 94 to 97, and the signal DS0 is supplied to the other input ends of the NAND gates 94 to 97. The write data PE is output from the output terminals of the NAND gates 94 to 97.
0 to PE4 are output. The write data PE0 is supplied to I / O0 to I / O3, and the write data PE1 is supplied to I / O8 to I / O11. Further, the write data PE2 is supplied to I / O4 to I / O7, and the write data PE3 is I / O12 to I / O15.
Is supplied to.

FIG. 5B shows the relationship between the signals DS0 and DS1 and the division method in the circuit shown in FIG. 5A. "0" level as signal DS0, signal DS1
When a "0" level is given as, the division is not performed and the 16-bit batch selection state is set. Similarly, when the signal DS0 is given a "0" level and the signal DS1 is given a "1" level, the same division is not performed, and the 16-bit batch selection state is set. On the other hand, when the signal DS0 is given a "1" level and the signal DS1 is given a "0" level, the signal is divided into two, and selection is performed every 8 bits. Furthermore, the signal DS0
When a "1" level is given as a signal and a "1" level is given as a signal DS1, it is divided into four, and selection is performed every four bits.

FIG. 6 is a circuit diagram showing a detailed configuration example of the timer 23 in the circuit shown in FIG. The timer 23 includes delay circuits 120 and 121, NAND gates 122 to 125, inverters 126 to 128, binary counters 130-0 to 130-n, and inverters 131 to 131.
133, 135-0 to 135-n and NAND gate 13
4 is included. The enable signal EN is supplied from the control circuit 22 to one input end of the NAND gate 122, and the output signal of the NAND gate 122 is supplied to one input end of the NAND gate 125 as the clock signal CLK via the inverter 126. Delay circuit 120
The output signal of is supplied to the delay circuit 121, and is also supplied to one input end of the NAND gate 123 via the inverter 127. The output signal of the delay circuit 121 is
It is supplied to one input terminal of the NAND gate 124, and the enable signal EN is supplied to the other input terminal of the NAND gate 124.
Is supplied. The output signal of the NAND gate 124 is
The input terminal of the delay circuit 120 and the NAND gate 12
2 is supplied to the other input terminal. Nand gate 12 above
The output signal of the NAND gate 125 is supplied to the other input terminal of the NAND gate 125, and the output signal of the NAND gate 125 is supplied to the input terminal of the inverter 131 via the inverter 128 as the clock signal GCLK. This inverter 1
The output signal of 31 is supplied to the input terminal CI1 of the binary counter 130-1 and is also supplied to the input terminal / CI1 via the inverter 132. The output terminals CI, / CI and the input terminals CI1, / CI1 of the binary counters 130-0 to 130-n are connected in cascade, and the output terminals / CI of the binary counters 130-0 to 130-n are connected.
Is supplied to the write division control circuit 26 shown in FIG. 15A as the signals TCUT0 to TCUTn via the inverters 135-0 to 135-n. The inverter 13 is connected to one input terminal of the NAND gate 134.
3, the signal TCRST is supplied to the other input terminal, and the output signal / PTRST of the write division control circuit 26 is supplied to the other input terminal. The signal TCRST is a signal for detecting a change in state and resetting the timer 23. The output signal of the NAND gate 134 is supplied to the reset input terminal RST of each of the binary counters 130-0 to 130-n and the timer is reset. 23 is to be reset.

FIGS. 7 (a), 7 (b) and 8 respectively show
The write verify operation in the flash EEPROM shown in FIGS. 1 to 6 is described below. FIG. 7A is a flowchart of the write verify operation, and FIG. 7B is a flow chart of input data, read data and write data. FIG. 8 is a diagram showing a logical relationship, and FIG. 8 is a timing chart thereof.

As shown in the flowchart of FIG. 7A, when the write verify operation is started, write verify setup is performed (step 1), 1 μm.
After a power supply setting period of about S, write verify read is performed (step 2). Next, it is compared whether or not the input data and the read data match (step 3), and if they match, the read setup (step 4) is performed and the process ends. On the other hand, when they do not match, it is determined whether or not the number of rewriting cycles has reached the limit (step 5). (Step 6). The input data, the read data, and the write data in step 6 have a logical relationship as shown in FIG. Next, write setup is performed (step 7). After that, I in the memory cell array
Writing is performed on 4 bits of / O0 to I / O3 (step 8), writing is performed on 4 bits of I / O4 to I / O7 (step 9), and I / O8 to I / O.
Writing is performed on 4 bits of 11 (step 1
0), and writing is further performed for 4 bits of I / O12 to I / O15 (step 11). Step 8 above
In the writing from step 11 to step 11, the voltage applied to the memory cell is the power supply voltage V _DD (for example, 3 V).
This is a high voltage generated by boosting with, and as shown in the timing chart of FIG. 8, for example, 10 V is applied to the control gate (word line) and 5 to 6 V is applied to the drain (bit line) of the selected cell transistor. . The method of writing to this cell transistor is hot electron injection, and the drain current is required to be about 500 μA / 1 bit. Writing is continued for a writing time set in the timer 23, for example, about 5 μS. After that, 1 is added to the number of cycles (step 12), and then the process returns to step 1 and the write verify operation is repeated until the input data matches the read data. If the two data do not match even after reaching the preset limit number of times, it is determined to be defective (step 13), the read setup (step 4) is performed, and the process ends.

In the first embodiment, the signals DS0,
16 bits are collectively selected according to the level of DS1, divided into 2 or 4 and the power supply circuit (boost circuit) 24 is selected by selectively switching the memory cells to be written at once to 16 bits, 8 bits or 4 bits. I am trying to reduce the current consumption. Therefore, when the power supply voltage drops, the pattern occupation area of the booster circuit of the power supply circuit can be minimized by increasing the number of divisions. On this occasion,
To prevent a difference in write characteristics between the memory cell selected first and the memory cell selected last, select the bit line timing after boosting the gate voltage and select the time required for each bit line. Since it is set to be constant, it is possible to reduce variations in write characteristics due to I / O. As a result, the power supply voltage can be lowered without increasing the chip occupation area.

Although the divisions are switched using the signals DS0 and DS1 in the above-described first embodiment, a fixed level potential may be applied as these signals so that the division number is not switched. The circuit can also be configured. Further, although the case where the memory cell array 11 is divided into two and four is described as an example, it is needless to say that the memory cell array 11 may be expanded into eight, sixteen, or the like if necessary.

[Second Embodiment] FIG. 9 is for explaining a semiconductor memory device according to a second embodiment of the present invention, and is a schematic circuit of a flash EEPROM having an automatic write function. It is a block diagram which shows a structure. In the second embodiment, a power supply voltage detection circuit 27 is provided in addition to the circuit configuration shown in FIG. 1, and the operation of the write division control circuit 26 is controlled according to the detection result of the power supply voltage detection circuit 27. I am trying. That is, the power supply voltage detection circuit 27 detects the power supply voltage V _DD at the initial stage of the automatic write operation and holds the detection signals A and B, and according to the levels of these signals A and B (in accordance with the power supply voltage level). ), No division (V _DD high level), 2 divisions (V _DD intermediate level), and 4 divisions (V _DD low level). 9, the same components as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 10A is a circuit diagram showing a configuration example of the power supply voltage detection circuit 27 in the circuit shown in FIG. This circuit 27 includes resistors 140, 141 and 142, operational amplifiers 143 and 144, and registers 145 and 146.
Etc. The resistors 140, 141, 1
42 is directly connected between the power supply V _DD and the ground point V _SS, the voltage between the power supply voltage V _DD and the ground point V _SS resistance division to generate two potential. These potentials are the operational amplifier 14 respectively.
It is supplied to the inverting input terminals (-) of 3,144. The reference potential V _REF is supplied to the non-inverting input terminals (+) of the operational amplifiers 143 and 144, and their comparison outputs are latched in the registers 145 and 146 in response to the enable signal EN. Then, the division operation by the write division control circuit 26 is controlled by the output signals A and B of these registers 145 and 146, for example, as shown in FIG.

That is, for example, the signals A and B are both "0".
When the level is set, 16 bits are selected all at once and signal A
Is "0" level and signal B is "1" level, 8 bits are selected (divided into 2), and when signals A and B are "1" level, 4 bits are selected (divided into 4).

If the signals A and B are used as the signals DS0 and DS1 in FIG. 5A, FIG.
The division operation as shown in FIG.

11 (a), 11 (b) and 12 are the flash EEPRO shown in FIGS. 9 and 10, respectively.
FIG. 11A is a flow chart of the write verify operation, FIG. 11B is a diagram showing the logical relationship between the input data, the read data and the write data.
Is the timing chart.

As shown in the flow chart of FIG. 11A, the power supply voltage detection circuit 27 before data writing.
The power supply voltage is detected by (step 1), and when the write verify operation is started thereafter, write verify setup is performed (step 2), 1 μm.
After a power supply setting period of about S, write verify read is performed (step 3). Next, it is compared whether or not the input data and the read data match (step 4), and if they match, the read setup (step 5) is performed and the process ends. On the other hand, when they do not match, it is judged whether or not the number of rewriting cycles has reached the limit (step 6). (Step 7). The input data, the read data, and the write data in step 7 have a logical relationship as shown in FIG. Next, it is determined whether the output signal A of the power supply voltage detection circuit 27 is at "1" level (step 8),
At the "1" level, a write operation corresponding to four divisions is performed. That is, first, after write setup (step 9) is performed, I in the memory cell array is
Writing is performed on 4 bits of / O0 to I / O3 (step 10), writing is performed on 4 bits of I / O4 to I / O7 (step 11), and I / O8 to I
Writing is performed on 4 bits of / O11 (step 12), and further writing is performed on 4 bits of I / O12 to I / O15 (step 13). In the writing in steps 9 to 13, the voltage applied to the memory cell is a high voltage generated by boosting the power supply voltage V _DD (for example, 3 V) by the power supply circuit 24, and as shown in the timing chart of FIG. 10V to the control gate (word line) of the selected cell transistor,
5 to 6 V is applied to the drain (bit line). The method of writing to this cell transistor is hot electron injection, and the drain current is required to be about 500 μA / 1 bit. Writing is continued for a writing time set in the timer 23, for example, about 5 μS. afterwards,
After adding 1 to the number of cycles (step 14), the process returns to step 1 and the write verify operation is repeated until the input data matches the read data.

On the other hand, if it is determined in step 8 that the level is not "1", the power supply voltage detection circuit 2
It is determined whether the output signal B of No. 7 is at "1" level (step 15). When it is determined to be the "1" level, the write operation corresponding to the two divisions is performed. First, after write setup (step 16) is performed, write is performed on 8 bits of I / O0 to I / O7 in the memory cell array (step 17), and I / O8
Writing is performed on 8 bits of I to O15 (step 18). The voltages applied to the memory cells in the writing in steps 17 and 18 are as shown in the timing chart of FIG. 12, as in steps 10 to 13. Then, after adding 1 to the number of cycles (step 14), the process returns to step 1 and the above-described write verify operation is repeated until the input data matches the read data.

Further, in the above step 15, "1"
When it is determined that the level is not set, the batch write operation is performed and I / O0 to I / O in the memory cell array are performed.
Writing is performed on 16 bits of O15 (step 19). The voltage applied to the memory cell in the writing in step 19 is as shown in the timing chart of FIG. Then, after adding 1 to the number of cycles (step 14), the process returns to step 1 and the above-described write verify operation is repeated until the input data matches the read data. Then, if the two data do not match even after reaching the preset limit number of times, it is determined to be defective (step 20), the read setup (step 5) is performed, and the process ends.

[0062] According to this structure, a wide range (e.g., 1.8 V to 3.6 V) of the power supply voltage V _DD and, like the case of writing an acceleration test or the like at a high supply voltage V _DD, the power supply voltage V _DD The optimum division method can be automatically switched according to the setting, so the write speed can be optimized, write time can be shortened, and test time can be shortened (test cost can be reduced) compared to when the lowest voltage is assumed. Can be expected.

In the second embodiment, an example in which two detection levels are prepared and no division, two divisions or four divisions are switched has been described, but the number of detection levels and the division method are arbitrary. For example, if the power supply voltage detection circuit is configured as shown in FIG. 13A and four detection levels are prepared, no division, two divisions, four divisions, eight divisions, and sixteen divisions can be realized.

FIG. 13A is a circuit diagram showing another configuration example of the power supply voltage detection circuit 27 in the circuit shown in FIG. This circuit is composed of resistors 150 to 154, operational amplifiers 155 to 158, registers 159 to 162, and the like. The resistors 150 to 154 are directly connected between the power source V _DD and the ground point V _SS, and are connected to the power source voltage V _DD and the ground point V _SS.
The voltage between them is resistance-divided to generate four potentials. These potentials are supplied to the inverting input terminals (−) of the operational amplifiers 155 to 158, respectively. The operational amplifiers 155 to 158
The reference potential V _REF is supplied to the non-inverting input terminal (+) of the above, and its comparison output is latched in the registers 159 to 162 in response to the enable signal ENEBLE.
Then, the output signals A of these registers 159 to 162,
The division operation by the write division control circuit 26 is controlled by B, C, and D as shown in FIG.

That is, for example, when the signals A, B, C, D are all at "0" level, 16 bits are selected at once, the signals A, B, C are at "0" level, and the signal D is at "1" level. When 8 bits are selected (divided into 2), signals A and B are at "0" level, and when signals C and D are at 1 level, 4 bits are selected (divided into 4) and signal A is "0".
When the level and the signals B, C and D are "1" level, 2 bits are selected (8 divisions), and the signals A, B, C and D are further selected.
When all are at "1" level, 1 bit is selected (1
6 divisions).

[Third Embodiment] FIG. 14A,
FIGS. 14B and 15 are respectively for explaining a semiconductor memory device according to the third embodiment of the present invention, and FIG. 14A shows a write verify operation in a flash EEPROM having an automatic write function. FIG. 14B is a flowchart showing the relationship between input data, read data, and write data, and FIG. 15 is a timing chart thereof. The basic circuit configuration of the flash EEPROM of the third embodiment is the same as that of the second embodiment.
However, the verify operation is different.

As shown in the flow chart of FIG. 14A, when the write verify operation is started, the write verify setup is performed (step 1), 1 μm.
After a power supply setting period of about S, write verify read is performed (step 2). Next, it is compared whether or not the input data and the read data match (step 3), and if they match, the read setup (step 4) is performed and the process ends. On the other hand, when they do not match, it is determined whether or not the number of rewriting cycles has reached the limit (step 5). (Step 6). The input data, the read data, and the write data in step 6 have a logical relationship as shown in FIG. Next, after the power supply voltage detection circuit 27 detects the power supply voltage (step 7), it is judged whether or not the output signal A of the power supply voltage detection circuit 27 is at "1" level (step 8), and the "1" level. In the case of, the write operation corresponding to four divisions is performed. That is, after write setup (step 9) is performed, write is performed to 4 bits of I / O0 to I / O3 in the memory cell array (step 10), and 4 bits of I / O4 to I / O7 are set. Writing is performed (step 11), and I /
Writing is performed on 4 bits of O8 to I / O11 (step 12), and further writing is performed on 4 bits of I / O12 to I / O15 (step 13). In the writing from step 10 to step 13,
The voltage applied to the memory cell is the power supply voltage _VDD (for example, 3V).
Is a high voltage generated by boosting the
As shown in the timing chart of 5, for example, the control gate (word line) of the selected cell transistor
To the drain (bit line) of 5 to 6V. The writing method to this cell transistor is hot electron injection, and the drain current is 500 μA /
About 1 bit is required. Writing is continued for a writing time set in the timer 23, for example, about 5 μS. Then, after adding 1 to the number of cycles (step 14), the process returns to step 1 and the above-described write verify operation is repeated until the input data matches the read data.

On the other hand, when it is determined in step 8 that the level is not "1", the power supply voltage detection circuit 2
It is determined whether the output signal B of No. 7 is at "1" level (step 15). Then, at the "1" level, the write operation corresponding to the two divisions is performed. First, write setup (step 16) is performed, and thereafter, writing is performed to 8 bits of I / O0 to I / O7 in the memory cell array (step 17), and I / O is continued.
Writing is performed on 8 bits of 8 to I / O 15 (step 18). The voltages applied to the memory cells in the writing in steps 17 and 18 are as shown in the timing chart of FIG. 15, as in steps 10 to 13. Then, after adding 1 to the number of cycles (step 14), the process returns to step 1 and the above-described write verify operation is repeated until the input data matches the read data.

Further, in the above step 15, "1"
When it is determined that the level is not set, the batch write operation is performed and I / O0 to I / O in the memory cell array are performed.
Writing is performed on 16 bits of O15 (step 19). The voltage applied to the memory cell in the writing in step 19 is as shown in the timing chart of FIG. Then, after adding 1 to the number of cycles (step 14), the process returns to step 1 and the above-described write verify operation is repeated until the input data matches the read data. Then, if the two data do not match even after reaching the preset limit number of times, it is determined to be defective (step 20), the read setup (step 4) is performed, and the process ends.

That is, in the second embodiment, the detection of V _DD is operated only at the initial stage of the automatic write operation.
In the third embodiment, V _DD is detected every time immediately before the write operation. Therefore, even if the power supply voltage V _DD changes during the writing, it is possible to obtain the effect that the writing can be performed by the division method according to the power supply voltage V _DD .

In the third embodiment, the number of divisions can be set arbitrarily as in the second embodiment.

[Fourth Embodiment] FIG. 16 is for explaining a semiconductor memory device according to a fourth embodiment of the present invention, and is a schematic circuit of a flash EEPROM having an automatic write function. It is a block diagram which shows a structure. In the fourth embodiment, instead of the detection signals A and B of the power supply voltage V _DD in the above-described second embodiment, a control data storage circuit 28 including a non-volatile memory cell such as an EEPROM cell is used. The control method is determined based on the stored data.

According to such a configuration, the division method can be freely changed by rewriting the storage data of the memory cell in the control data storage circuit 28 according to the application such as the level of the power supply voltage V _DD to be used and the acceleration test. Can be changed. This reduces the write time by optimizing the write time,
It is expected that the yield will be improved by trimming the writing characteristics.

Instead of providing the control data storage circuit 28, a part of the area of the memory cell array 11 may be used to store the control data in this memory cell. Further, instead of the detection signals A and B, other control data, for example, data for controlling the driving capability of the booster circuit in the power supply circuit 24 is stored, and boosted when the power supply voltage drops or the current consumption increases. Increase the current supply capacity of the circuit,
The control method may be changed so that the current supply capability of the booster circuit is reduced when the power supply voltage rises or the current consumption decreases. Furthermore, by combining both the control of the drive capability of this booster circuit and the change of the number of divisions, more precise control becomes possible.

[Fifth Embodiment] FIG. 17 is for explaining a semiconductor memory device according to a fifth embodiment of the present invention, and is a schematic circuit diagram of a flash EEPROM having an automatic write function. It is a block diagram which shows a structure.

In the fifth embodiment, the above-mentioned second
In place of the detection signals A and B of the power supply voltage V _DD in the above embodiment, a test signal TS supplied from the outside of the chip
The control method is determined based on Also in this case, the division method can be changed according to the application such as the level of the power supply voltage _VDD to be used and the acceleration test, and the time can be shortened by optimizing the write time, and the test cost can be reduced.

[0077]

As described above, according to the present invention, it is possible to obtain the semiconductor memory device capable of suppressing the increase of the writing time when the power supply voltage is lowered.

Further, it is possible to obtain a semiconductor memory device capable of lowering the power supply voltage without increasing the chip occupying area.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining a semiconductor memory device according to a first embodiment of the present invention, showing a schematic circuit configuration of a flash EEPROM having an automatic write function.

FIG. 2 shows essential parts of the flash EEPROM shown in FIG. 1 that are directly related to the present invention. The circuit shown in FIG. 1 includes a memory cell array, a row decoder, a column decoder, a sense amplifier, and write data generation. The circuit diagram which extracts a circuit, a write switch, and a power supply circuit, and shows a part of circuit configuration in detail.

FIG. 3A is a circuit diagram showing a detailed configuration example of a data register, a write data generation circuit, a verify circuit, and a write switch in the circuits shown in FIGS. FIG. 6B is a diagram showing the logic level of each signal in the circuit shown in FIG.

FIG. 4 is an overall circuit diagram of the verify circuit shown in FIG.

5 is a circuit diagram showing a detailed configuration of a write division control circuit in the circuit shown in FIG.

6 is a circuit diagram showing a detailed configuration example of a timer in the circuit shown in FIG.

FIG. 7 is a flash EEPRO shown in FIGS. 1 to 6;
FIG. 6A is a flowchart of the write verify operation, and FIG. 6B is a diagram showing the relationship between input data, read data, and write data, for the purpose of explaining the verify operation in M.

FIG. 8 is a flash EEPRO shown in FIGS. 1 to 6;
6 is a timing chart for explaining a verify operation in M.

FIG. 9 is a block diagram for explaining a semiconductor memory device according to a second embodiment of the present invention, showing a schematic circuit configuration of a flash EEPROM having an automatic write function.

10A is a circuit diagram showing a configuration example of a power supply voltage detection circuit in the circuit shown in FIG. 9, and FIG. 10B is a diagram showing a relationship between an output signal of a register and a division operation.

FIG. 11 is a flash EEPR shown in FIGS. 9 and 10;
For the purpose of explaining the verify operation in the OM, (a) is a flowchart of the write verify operation, and (b) is a diagram showing the relationship between input data, read data, and write data.

FIG. 12 is a flash EEPR shown in FIGS. 9 and 10;
6 is a timing chart for explaining a verify operation in OM.

13A is a circuit diagram showing another configuration example of the power supply voltage detection circuit in the circuit shown in FIG. 9, and FIG. 13B is a diagram showing the relationship between the output signal of the register and the division operation.

14A and 14B are diagrams for explaining a semiconductor memory device according to a third embodiment of the present invention, FIG. 14A is a flowchart showing a write verify operation in a flash EEPROM having an automatic write function, and FIG.
The figure shows the relationship between input data, read data, and write data.

FIG. 15: Flash EEP with automatic write function
6 is a timing chart for explaining a write verify operation in a ROM.

FIG. 16 is a block diagram illustrating a semiconductor memory device according to a fourth embodiment of the present invention and showing a schematic circuit configuration of a flash EEPROM having an automatic write function.

FIG. 17 is a block diagram for explaining a semiconductor memory device according to a fifth embodiment of the present invention, showing a schematic circuit configuration of a flash EEPROM having an automatic write function.

FIG. 18 is a block diagram showing a schematic circuit configuration of a conventional flash EEPROM having an automatic write function.

19A and 19B are diagrams for explaining the operation at the time of automatic writing, FIG. 19A is a flowchart, and FIG. 19B is a diagram showing a logical relationship between input data, read data, and write data.

FIG. 20 is a timing chart for explaining an operation during automatic writing.

[Explanation of symbols]

11 ... Memory cell array, 12 ... Row decoder, 13 ...
Column decoder, 14 ... Address register, 15 ... Multiplexer, 16 ... Command register, 17 ... Sense amplifier, 18 ... I / O buffer, 19 ... Data register,
20 ... Write data generation circuit, 21 ... Write switch, 22 ... Control circuit, 23 ... Timer, 24 ... Power supply circuit (boosting means), 25 ... Verify circuit, 26 ... Write division control circuit (write division control means), 27 ... Power supply voltage detection circuit (power supply voltage detection means), 28 ... Control data storage circuit (control data storage means, division number storage means).

Front Page Continuation (72) Inventor Naoto Tomita 580-1, Horikawa-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside Toshiba Semiconductor System Technology Center (56) Reference JP-A-5-28779 (JP, A) JP-A-9-161492 (JP, A) JP-A-6-131879 (JP, A) JP-A-6-84396 (JP, A) JP-A-10-334675 (JP, A) JP-A-8-321193 (JP , A) JP-A-4-38700 (JP, A) JP-A-5-62484 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 16/00-16/34 G11C 29/00

Claims (11)

(57) [Claims] 1. A semiconductor memory device having an automatic write function and using a potential obtained by boosting a power supply voltage when writing, in a semiconductor memory device, a boosting means for boosting the power supply voltage to generate a high voltage for writing, and a data writing step. By selectively turning on / off a bit line write switch that controls whether or not input data is supplied to the bit line, the bit line selection timing is shifted, and writing is performed in multiple steps. write and write division control means, to the write division control means memory cells connected to the selected bit lines, and writing means for writing data by applying a high voltage output from the booster means, by said writing means Memory cell
Select the first bit line after boosting the word lines of
To control the write division control means so that
A semiconductor memory device characterized by integrating a backup means and a single chip in a single chip . 2. The setup means is configured to set
The timer including a timer for measuring the setup time,
First after the set-up time set for
The write division control procedure to select the bit line
The semiconductor memory device according to claim 1, wherein the stage is controlled . 3. The semiconductor memory device according to claim 1, wherein the selection time of each bit line selected by being divided into a plurality of times by the write dividing means is substantially equal to each other. 4. The power supply voltage detecting means for detecting the power supply voltage boosted by the boosting means is further provided, and the control method is changed based on the level of the power supply voltage detected by the power supply voltage detecting means. Any one of claims 1 to 3
A semiconductor memory device according to one of the items. 5. The power source voltage detecting means for detecting the power source voltage boosted by the boosting means before writing data, further comprising: the writing when the level of the power source voltage detected by the power source voltage detecting means is low. 4. The semiconductor memory device according to claim 1, wherein the number of divisions by the division control means is increased and the number of divisions is decreased when the division control means is high. 6. The power supply voltage detection means for detecting the power supply voltage boosted by the boosting means is further provided, and the power supply voltage detection means detects the power supply voltage immediately after the start of automatic writing, and the detected power supply voltage level is 4. The number of divisions by the write division control means is increased when the value is low, and the number of divisions is decreased when the value is high.
A semiconductor memory device according to one of the items. 7. A control data storage means for storing a control method is further provided, and the control method is changed based on the control method stored in the control data storage means. The semiconductor memory device according to one item. 8. The control data storage means is an EEPROM
8. The semiconductor memory device according to claim 7, further comprising a cell, wherein the EEPROM cell stores control data. 9. A division number storage means for storing the division number by the write division control means is further provided, and the division number by the write division control means is changed based on the division number stored in the division number storage means. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. 10. The semiconductor memory device according to claim 9, wherein the division number storage means includes an EEPROM cell, and the division number is stored in the EEPROM cell. 11. The semiconductor memory device according to claim 1, wherein the write division control unit controls the number of divisions based on a test signal.