JP3488655B2 - Multi-select output inhibit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the case where digital output is performed using a controller. The present invention relates to a multiple-selection output prohibiting device that prohibits multiple-selection output when there is a possibility that a large capacity current is generated. 2. Description of the Related Art Conventionally, when digital output is performed by a controller, each digital output is usually arbitrary (simultaneous).
Therefore, when operating with the target device, whether or not digital output can be selected multiplely is left to the judgment of the operator. In addition, there is a risk that multiple selection output is performed for a target device for which multiple selection output is prohibited due to an operator's misjudgment. In the prior art, when digital output is performed by a controller, each digital output can normally (arbitrarily) be output. In addition, the possibility of multiple selection of digital output is left to the discretion of the operator, and there is a danger that multiple selection output will be performed to a target device for which multiple selection output is prohibited due to the operator's misjudgment. According to the present invention, a multi-select output prohibition device having a high reliability is provided by forming a multi-select output enable / disable judgment to be determined by an operator by a logic circuit and adding a function of eliminating an operator's erroneous judgment. It is intended to provide. A multiple selection output prohibiting device according to the present invention is provided with a first adder for inputting and adding a plurality of operation output states, and is connected to the first adder. A first equivalence determiner for determining whether or not an added value of the operation output state is the same as a preset numerical value; and a second adder for inputting and adding a plurality of actual output states. And this second
And the added value of the actual output state is
A second equivalence determiner that determines whether the value is the same as a set numerical value, and outputs of the first equivalence determiner and the second equivalence determiner are integrated, and the result can be output as a digital signal. a logical product operation unit for the condition, and the logic accumulator the digital signal which is an output output condition and flip-flop master relay you set the operating condition by the condition that is not turned on, the flip-flop of this Output signal to the master relay after a certain period of time.
Timer and the output to the master relay by this timer
A delay circuit that to output the reset signal after a predetermined time from the time provided for each of the plurality of operating output, said digital signal
Signal output condition and the condition that the master relay is not turned on.
Actual output set on condition that there is a corresponding operation output
And reset by the output of the delay circuit.
And a number of flip-flops . [0006] multiple selection output disable device of the embodiment of the present invention is to inhibit multiple selection output operations, Misao digital output, Misao produce force (e.g., operated by an operator
Operation command) and the actual output (actual
Considered divided into the output), the ON operation output to multiple selection prohibited in the digital signal by adding a "1", by the result is determined as "1", especially the operation was accepted only one point Become. Similarly, the ON of the actual output is added as "1", and the result is determined to be "0", so that it is determined that the current actual output is not performed. When two conditions, that is, a condition that only one operation output is performed and a condition that the actual output is not performed, are satisfied at the same time, it is determined that the digital signal can be output, and the digital signal is used as the output condition of the actual output. It was configured to be able to. Accordingly, the operation output for prohibiting the multiple selection output is set to O
N, the condition that only one actual output is output is the condition that the operation output is 1
It is a condition for outputting an actual output that only points are present and that no actual output is performed. Further, it is characterized in that the actual output is designed to be turned off after the minimum guaranteed time (for example, 3 seconds), and a process of creating a reset condition using a reset priority flip-flop in the actual output process is added. Next, an embodiment of the multiple selection output prohibiting device of the present invention will be described. In FIG. 1, the adder 1A is in the state of the operation outputs A, B, C, and the adder 1B is the actual outputs D, E,
Ru circuit der to be added by entering the state of F. Equivalence detector 2
A is connected to an adder 1 A, operation output A, B, the sum of the state of C is of the same value as the numerical value "1" set in advance
It is determined whether or not. Similarly, the equivalence determiner 2B is an adder 1B
And the sum of the states of the actual outputs D, E and F is
This is a circuit for determining whether or not the value is the same as the set numerical value “0” . Then, the logic accumulator 3 D Equivalencing determiner 2 A,
Connected to the output side of 2B, equivalence determination unit 2 A, 2B outputs a logically totalized, a circuit for the result with the digital signal output enable condition d. Further delaying the reset priority flip-flop 5 D to set the operating state by the conditions the digital signal output enable condition d and the master relay is not turned ON, the output signal from the reset priority flip-flop 5 D in FIG. 1 O (for 1 second)
And a N delay timer 6 A. This timer 6A
Is output from the rising edge detector 7D as shown in FIG.
Output to the relay and change its signal state. As described above, in the present embodiment, the logic circuit is configured by distinguishing the operation output b and the actual output a of the digital signal for which the multiple selection output is prohibited. That is, A,
B and C belong to the operation output, and D, E and F belong to the actual output a. Next, the operation of the digital output of the present embodiment for inhibiting the multiple selection output will be described. Describe the conditions that compose a logic circuit that prohibits multiple selection of digital output. (1) Multiple selection determination condition When performing an operation of prohibiting multiple selection, since only one operation is accepted, the ON state of the operation output is set to “1”, and the OF is output.
The F state is set to "0" and the adder 1A adds the values to A, B,
It is necessary that the result of adding the state of C is "1" at the same value determiner 2 A. Moreover, since such one of the conditions that are not currently actual output, the actual output likewise the ON state is set to "1", added by the adder 1 B to OFF state as "0",
It is necessary that the result of adding the states of D, E, and F is "0" in the equivalence determination unit 2B . And the result of the logical AND of the two conditions by logic integrator 3 D to a digital signal output enable condition d. (2) Conditions for turning on the real signal The conditions for turning on the real signal are the digital signal output enabling condition d finally created under the multiple selection determination condition of (1).
And the condition that the master relay is not currently ON ( signal
Output of the inverter 9 ) and a rising signal of the operation output (rising detection)
Vessels 7A, 7B, the logic accumulator to 7C of output) Condition 3 A, 3
B, 3C , and the logical product is performed, thereby real signal a
Is turned on. Conditions for turning on this real signal a
To reset priority flip-flop 5 for OFF processing
Set on the set side of A, 5B, 5C , and turn on the actual signal. (3) Conditions for turning off the real signal Since the real signal is not turned off as it is, a condition for turning off the real signal is constituted by two conditions. That is, the condition that the master relay state is ON (the flip-flop 5E
Output ) and the conditions under which the master relay is OFF ( automatic
And it outputs the result of ORing off delay output of the timer) and the at logical adder 4 A reset side of the reset priority flip-flop 5 for OFF processing of the real signal. Sand
The OFF delay circuit 10 and the signal falling detector 8
And flip flop 5E and ON delay timer 6
The real signal is turned off by the output of the delay circuit composed of B or the like . The ON delay circuit 6 B is connected to the output side of the reset priority flip flop 5 E ,
As described above, this is a delay circuit for delaying and outputting an output signal. Each of the signal rise detectors 7 and signal fall detectors 8 is a device for detecting a rise or fall of a signal, and outputs, for example, an operation output rise signal c. Further, the signal inverter 9 outputs the signal "1".
To "0" or the signal "0" to "1". The multiple-selection output prohibiting device of the present invention is constructed and operates as described above, so that the multiple-selection output prohibition of a digital signal can be reliably performed. According to the present invention, digital signal multiple selection output can be reliably inhibited.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of a multiple selection output prohibiting device showing an embodiment of the present invention. [Description of Signs] 1 Adder 2 Equivalence detector 3 Logical accumulator 4 Logical adder 5 Reset priority flip-flop 6 ON delay circuit 7 Signal rising detector 8 Signal falling detector 9 Signal inverter 10 OFF delay circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H02J 1/00 H02H 11/00 H04Q 9/00

Claims (1)

(57) [Claim 1] A first adder for inputting and adding a plurality of operation output states, and a first adder connected to the first adder for adding the operation output states .
A first equivalence determiner for determining whether the calculated value is the same as a preset numerical value, a second adder for inputting and adding a plurality of actual output states, and a second adder Connected to the output unit and adds the actual output status
A second equivalence determiner that determines whether or not the value is the same as a preset numerical value; and outputs of the first equivalence determiner and the second equivalence determiner are integrated, and the result is digitally calculated. a logical product operation unit to the signal output enable condition, and flip-flops you set the operating state the digital signal output condition and the master relay is this logic integrator output by the condition not on, this flip・ The output signal from the flop is delayed and constant
A timer to output to the master relay after a time, and a predetermined time from when the timer outputs to the master relay.
A delay circuit that outputs a reset signal after a while, and a digital signal output circuit that is provided for each of the plurality of operation outputs.
Force condition and the condition that the master relay is not turned on.
Is set on condition that there is an operation output
That are reset by the output of the delay circuit.
Multiple selection output disable device characterized by comprising: a flip-flop, a.