JP3490140B2 - Analog fuzzy processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sweep type fuzzy processor.

[0002]

2. Description of the Related Art In a conventional sweep type fuzzy processor, an input knowledge label is converted into a membership function in which the X axis is time and the Y axis is voltage in synchronization with the sweep waveform by each membership function generating circuit. It was converted and all internal signals were temporally continuous.

FIG. 12 shows the principle of membership function generation in a sweep type fuzzy processor. The knowledge label X given as the voltage shown in FIG. 12A has a membership function μX having a maximum value at the time when the voltage of the sweep waveform shown in FIG. 12B becomes the same as the voltage of the knowledge label X. (FIG. 12C). This conversion is performed symmetrically in the rising portion and the falling portion of the sweep waveform, and is repeated with the repetition of the sweep waveform.

An example of the conventional sweep-type fuzzy processor shown in FIG. 13 has n fact inputs for n fact inputs.
This rule has a function to draw one conclusion within the period of two sweep waveforms. For this function, m × n
+ M + n membership function generators, (m + 1) ×
n product set synthesis circuits, m × n maximum value detection circuits, n
The minimum value detection circuit, the union combination circuit, the analog signal processing part of the centroid determination circuit, and the control circuit are required. It should be noted that n and m described in this specification represent any positive integer greater than 1.

[0005]

In the prior art, all the rules are processed simultaneously in time as described above, so that the circuit scale of the analog part becomes very large. Therefore, it is difficult to reduce the cost and save the power.

[0006]

In order to overcome the above-mentioned problems, the invention according to claim 1 of the present invention provides an n-input 1-output unquantized knowledge label signal input in parallel in time. , Which is input to the MUX multiplexer, and uses one membership function generation circuit to generate n quantized membership functions in time series, MAX_MIN
It is characterized by outputting the inference result by the center of gravity method as a voltage.

In the invention according to claim 2, one temporally continuous membership function and a membership function which is time-divided and has a value only in a certain period have the same non-zero value. Of a set represented by two membership functions, and a window comparator for detecting a thing and a circuit for sampling and holding the value of two or one of the membership functions in synchronization with the output of the window comparator. It is characterized by outputting the maximum value of the membership function that represents the intersection.

Furthermore, the invention according to claim 3 has two peak hold function blocks, which are alternately sampled and held, and only the output voltage in the hold mode of each peak hold function block is output. It is characterized by synthesizing a membership function that represents the union of sets represented by the time-divided membership functions of.

According to the present invention, a multiplexer is used to convert n knowledge labels for one condition into time-divisional (temporally serial) signals, which are converted into membership functions by one membership function generating circuit. By processing this time-division membership signal, processing of n rules for m fact inputs (MIM
The UM combination can be performed by m rule processing sets (1 multiplexer, 2 membership function generating circuits, 1 product set combining circuit, and 1 maximum value detecting circuit) and n minimum value detecting circuits. In the subsequent signal processing (MAX combination and determination of the center of gravity), n post-condition part knowledge labels are similarly subjected to time division processing, and thus 2 multiplexers, 1 membership function generating circuit, 1 product set combining circuit, 1 sum Set synthesis circuit,
It is possible to do it with the 1-centroid decision circuit. It is also possible to draw one conclusion by using one set of circuit blocks in this part.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals denote the same or corresponding ones. FIG. 1 is a block diagram showing an embodiment of the present invention. For m fact inputs, one conclusion (MAX_MIN centroid method) based on n rules is 1.
It is a processor that derives within 5 sweep waveform periods. In the figure, KL0_1 to KL0_n, KL1_1 to KLm
_N is a knowledge label, FL1 to FLm are fact labels, MP
X0_0, MPX0_1, MPX1_1 to MPXm_1
Is a multiplexer, MFC0_1, MFC1_1 to MF
Cm_1, MFC1_0 to MFCm_0 are membership function generation circuits for generating a membership function, AND_
MAX1_1 to AND_MAXm_1 are product set synthesis / maximum value detection circuits, MIN0_1 to MIN0_n are minimum value detection circuits, AND0_1 are product set synthesis circuits, OR is a union set synthesis circuit, and CGD is a centroid determination circuit.

During the up or down period of the first sweep waveform, the knowledge labels KL1_1 to KL1_n are the multiplexer MP.
It is input to the membership generation circuit MFC1_1 via X1_1. The output of the membership function generation circuit MFC1_1 is input to the product set synthesis / maximum value detection circuit AND_MAX1_1 together with the output of the membership generation circuit MFC1_0 corresponding to the fact label FL1. These circuit blocks are required for the number of input fact labels (m). Product set synthesis / maximum value detection circuit AND_M
AX1_1 has n outputs. Knowledge label K in general
If the membership function for Lx_y (x and y are arbitrary numbers) is μx_y and the membership function for the fact label FLx is μx, the product set combination / maximum value detection circuit AN
The first output to the nth output of D_MAX1_1 can be expressed by the following equations in order.

[0012]

[Equation 1]

Similarly, AND_MAXm_1 is expressed as follows.

[0014]

[Equation 2]

Each of the first output, the second output, and the nth output has the same minimum value detection circuit MIN0_1, MIN0_2,
... input to MIN0_n. Minimum value detection circuit MI
N0_1 has m inputs and 1 output, and its output μo1
Is represented as follows.

[0016]

[Equation 3]

MIN0_n also obtains the following outputs.

[0018]

[Equation 4]

The processing up to this point is performed within the up (or down) cycle of the first sweep waveform. The following processing is performed in one cycle of the subsequent sweep waveform.

The n membership functions are input to the multiplexer MPX0_0 (n input 1 output), which is output as a time division signal on one signal line. This membership function μo1 to μon is the knowledge label KL0 of the consequent part.
Membership function μ0_1 corresponding to _1 to KL0_n
~ Μ0_n (which is time-division signalized by the multiplexer MPX0_1) together with the product set combining circuit AND0_1
Entered in. The product set synthesizing circuit AND0_1 outputs the following signal in the time division state on one signal line.

[0021]

[Equation 5]

This time division signal is input to the union combination circuit OR. The union synthesis circuit OR synthesizes the union of all input membership functions. The output of this union combination circuit OR is connected to the input of the center of gravity determination circuit CGD,
It is defuzzified and output as a single voltage.

The internal block can be constructed in principle as follows. For simplification, the following description will be given with m = n = 3. In the voltage waveforms in the figure, the horizontal axis represents time and the vertical axis represents voltage.

FIG. 2 shows an example of the structure of the multiplexer MPX1_1 and the connection with the membership function generating circuit MFC1_1. FIG. 3 shows an example of the voltage waveform of each part, that is, FIG.
Knowledge labels KL1_1 and KL are shown in (b) and (c), respectively.
1_2, KL1_3 voltage waveforms, FIG. 3 (d), (e),
3F shows gate voltage waveforms of the switches SW1, SW2, and SW3, and FIG. 3G shows a multiplexer MPX1_.
1 shows the output voltage waveform of FIG. 1, and FIG. 3 (h) shows the output voltage waveform of the membership function generating circuit MFC1_1. In the figure, SW1 to SW3 represent switches.

Knowledge labels KL1_1, KL1_2, KL
1_3 is input to the membership function generating circuit MFC1_1 only when the gate voltages of the switches SW1, SW2, and SW3 in the multiplexer MPX1_1 are in the H state. The switches are turned on in the order of SW1, SW2, and SW3 without overlapping. After the switch SW3 is in the conducting state, all the switches are in the non-conducting state for a certain period of time, and the operation in which the switch SW1 is in the conducting period is repeated. This cycle is a time division cycle. The membership function generation circuit MFC1_1 continuously outputs the membership function corresponding to the input voltage. This output is time-divided membership functions μ1_1, μ1_2, μ1_
It becomes 3. Membership function generator M shown in FIG.
For the sake of simplification, the output of FC1_1 has a membership function μ1_1, μ1_2, μ1_3 each having a non-zero value for three periods, while one membership function has a non-zero value. Then, it is desirable to take as many periods having this non-zero value as possible.

FIG. 4 shows a product set synthesis / maximum value detection circuit AND.
_MAX1_1 configuration example and the connection with the membership function generating circuit MFC1_0 is shown. FIG. 5 shows voltage waveform examples of each part, that is, FIG. 5A and FIG. 5B show output voltage waveforms of the membership function generating circuits MFC1_1 and MFC1_0, respectively. , (C), (d), and (e) of FIG. 5, gate voltage waveforms of the intersection timing detection circuits XT1, XT2, and XT3, respectively, and switches S in FIGS.
The gate voltage waveforms of W11, SW12, and SW13 are shown.
In the figure, WC1 is a window comparator, SW1
1 to SW13 are switches, and BF1 is a voltage buffer.

The product set synthesis / maximum value detection circuit A shown here.
In the block of ND_MAX1_1, first, the membership function μ1 corresponding to the fact label 1 and generated in time by the membership function generation circuit MFC1_0 is generated.
, The time-division membership functions μ1_1, μ1
_2 and μ1_3 are compared by the window comparator WC1. The window comparator WC1 has a function of setting the output state to L when the IN input is within the set range with respect to the RI input, and to the H state otherwise. The outputs are the intersection timing detection circuits XT1 and XT.
2, input to XT3. Intersection timing detection circuit XT
1, XT2, XT3 are latched until the positive edge of their respective gate voltages. The latched voltage is reset to the L state at the same time when the up period and the down period of the sweep waveform are completed. A pulse is output when the first negative edge occurs in the latch voltage in the rising and falling periods of the sweep waveform. The output pulses of the intersection timing detection circuits XT1, XT2, XT3 are the switches S, respectively.
W11, SW12, and SW13 are closed, and the voltage of the membership function μ1 is output through the switches SW11, SW12, and SW13, respectively, only during the pulse width period. The output voltage levels are as follows.

[0028]

[Equation 6]

Here, for convenience of connection to the next circuit block,
The output part of the voltage buffer BF1 has only current sink capability.

FIG. 6 shows minimum value detection circuits MIN0_1 and MI.
An example of the configuration of N0_2 and MIN0_3 is shown, and FIG. 7 shows an example of the voltage waveform of each part of the minimum value detection circuit MIN0_1, that is, FIG.
(A), (b) and (c) show the product set combination / maximum value detection circuits AND_MAX1_1 and AND_MAX2_, respectively.
1, the gate voltage waveform of the switch SW11 in AND_MAX3_1, the output voltage waveforms of the switches SW11, SW12, and SW13 of the product set combining / maximum value detection circuit AND_MAX1_1 in FIGS. 7D, 7E, and 7F, respectively. 7 (g) shows an output voltage waveform of the voltage buffer BF11. In the figure, C1 to C3 are capacitors, and BF11 to BF
Reference numeral 13 is a voltage buffer, and SW21 to SW23 are switches.

Product set synthesis / maximum value detection circuit AND_MA
X1_1, AND_MAX2_1, AND_MAX3_
The first outputs (outputs of the switch SW11) of the respective 1 are connected to each other and serve as inputs to the minimum value detection circuit MIN0_1. The second and third outputs (outputs of the switches SW12 and SW13) are also input to the minimum value detection circuits MIN0_2 and MIN0_3. The capacitor C1 is charged with the maximum voltage that the membership function can take when the sweep waveform starts to rise or fall,
The input of the minimum value detection circuit MIN0_1 is the product set synthesis / maximum value detection circuits AND_MAX1_1 and AND_MAX2_.
1, the maximum output voltage of AND_MAX3_1 is high impedance in the normal state, so this maximum voltage is held until an input state that is not high impedance occurs. Within the first non-high impedance period, the capacitor C1 is discharged to its input voltage, and that voltage is held thereafter. Next, in the second non-high impedance period, the product set combination / maximum value detection circuits AND_MAX1_1 and AND_MA
Due to the output characteristics of X2_1 and AND_MAX3_1, the capacitance C1 is discharged to that voltage only when the input voltage is equal to or lower than the voltage held in the capacitance C1, and the voltage in the previous state is held otherwise. Similar processing is performed in the third state. As a result, the capacitor C1 holds the following voltage at the end of the rising or falling of the sweep waveform.

[0032]

[Equation 7]

FIG. 8 shows a configuration example of the union combination circuit OR, and FIG.
9A shows an example of the voltage waveform of each part, that is, FIG. 9A shows the output voltage waveform of the product set synthesis circuit AND0_1, and FIGS. 9B and 9C show the gate voltage waveforms of the switches SW31 and SW32, respectively.
9 (d) and 9 (e), the voltage buffer BF22,
Output voltage waveform of BF23, gate voltage waveforms of switches SW33 and SW34 in FIGS. 9 (f) and 9 (g), respectively.
The output voltage waveforms of the switches SW33 and SW34 are shown in (h). In the figure, BF21 to BF23 are voltage buffers,
SW31 to SW34 are switches, and C11 and C12 are capacitors.

The signal input to the union combination circuit OR is 3
It is a time-shared membership function. The voltage buffer BF21 having only current source capability is a switch SW.
31 or SW32, whichever is closed, connects the capacitor C1
Charge 1 or C12 to its input voltage. Switch S
W31 and W32 are alternately turned on every time-division cycle. First, in the initial state, the voltages of the capacitors C11 and C12 are set to zero. Next, during the switch SW31 conduction period, the capacitor C11 is charged with the maximum input voltage within that period, and during the switch SW32 conduction period, that voltage is held. Then, at the same time as the switch SW32 conduction period ends, the voltage is reset to 0 and the conduction period starts again. Capacity C
Similarly, 12 is charged during the conduction period of the switch SW32 and holds the voltage during the conduction period of the switch SW31. The voltages held in the capacitors C11 and C12 are the voltage buffers BF22 and BF23 and the switches SW33 and SW34, respectively.
Is output via. Switch SW33 is switch SW3
2 and the switch SW34 are opened and closed at the same time as the switch SW31, the voltages of the capacitors C11 and C12 in the voltage holding period are alternately output. This output voltage is given by the input / output membership functions μ0_1 ', μ0_2', and μ0_3 '.
The union is as shown below.

[0035]

[Equation 8]

FIG. 10 shows an example of the configuration of the center of gravity determining circuit CGD, FIG. 11 shows an example of the voltage waveform of each part, that is, FIG. 11A shows the output voltage waveform of the union combining circuit OR, and FIG. , FIG. 11 (c), (d) respectively, switch S
Gate voltage waveforms of W41 and SW42, FIG.
(F) shows the potential changes of the capacitors C21 and C22, respectively. In the figure, Gm1 is a voltage-current converter, BF31 is a voltage buffer, C21 to C23 are capacitors, and SW41 to SW4.
3 is a switch, CMP 1 is a comparator, and OPG is a one-shot pulse generation circuit.

The input is a symmetric membership function in the rising and falling of the sweep waveform. At the rising portion of the sweep waveform, the switch SW41 becomes open and the switch SW
42 is closed. In this state, the output voltage of the union combination circuit OR is voltage-current converted by the voltage-current converter Gm1 and both the capacitors C21 and C22 are charged. After that, the switch SW42 is opened at the same time as the end of the sweep waveform rising period, and then the switch SW41 is closed. This state is maintained during the flat period of the sweep waveform. At the start of the down period, the switch SW41 is opened again, and in this state, the voltage-current converter Gm1 charges only the capacitance C21 and the capacitances C21 and C2.
The point where the charging voltages of 2 are the same is detected by the comparator CMP1. The one-shot pulse generation circuit OPG outputs one pulse by the output signal of the comparator CMP1. This pulse causes the switch SW43 to close instantaneously, and the voltage of the sweep waveform at that time is charged in the capacitor C23. The voltage of the sweep waveform at the same time point is output as a conclusion. When processing is performed in the descending and ascending order of the sweep waveform, the same operation can be performed by closing the switch SW42 in the descending period and opening it in the ascending period.

[0038]

As described in detail above, since the present invention uses the multiplexer to perform time-division processing of knowledge labels, the membership function generating circuit can be greatly reduced.
Therefore, the circuit scale of the analog portion can be remarkably reduced, and an analog fuzzy processor that realizes low cost and power saving can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a multiplexer.

FIG. 3 is a diagram showing a timing chart of the multiplexer and the membership function generating circuit shown in FIG.

FIG. 4 is a diagram showing a configuration example of a product set synthesis / maximum value detection circuit.

5 is a diagram showing a timing chart of the product set synthesis / maximum value detection circuit shown in FIG. 5;

FIG. 6 is a diagram showing a configuration example of a minimum value detection circuit.

7 is a diagram showing a timing chart of the minimum value detection circuit shown in FIG.

FIG. 8 is a diagram illustrating a configuration example of a union synthesis circuit.

9 is a diagram showing a timing chart of the union synthesis circuit shown in FIG. 9;

FIG. 10 is a diagram showing a configuration example of a center of gravity determination circuit.

11 is a diagram showing a timing chart of the center-of-gravity determination circuit shown in FIG.

FIG. 12 is an explanatory diagram showing the principle of membership function generation in the sweep type fuzzy processor.

FIG. 13 is a block diagram showing a conventional sweep type fuzzy processor.

[Explanation of symbols]

KL0_1 to KLm_n Knowledge labels FL1 to FLm Factual labels MPX0_0 to MPXm_1 Multiplexers MFC0_1, MFC1_0 to MFCm_1 Membership function generation circuits AND_MAX1_1 to AND_MAXm_1 Product set combination / maximum value detection circuit MIN0_1 to MIN0_n Sum core detection circuit OR Circuit WC1 Window comparators BF1 to BF31 Voltage buffers XT1 to XT3 Crossing point timing detection circuits SW11 to SW43 Switches C1 to C23 Capacitance Gm1 Voltage current converter CMP1 Comparator

Claims (3)

(57) [Claims] 1. A non-quantized knowledge label signal input in parallel in time is input to a multiplexer having n inputs and one output, and one membership function generating circuit is used,
A sweep-type fuzzy processor characterized by generating n unquantized membership functions that are serially connected in time and outputting the inference result by the MAX_MIN centroid method as a voltage. 2. A window comparator that detects that one temporally continuous membership function and a membership function that is time-shared and has a value only for a certain period have the same or very close non-zero values. A circuit for sampling and holding the value of two or one of the membership functions in synchronization with the output of the window comparator, and representing the intersection of the sets represented by the two membership functions. A device that outputs the maximum value. 3. A plurality of time-divided membership functions having two peak hold function blocks, which are alternately sampled and held, and output only the output voltage of each peak hold function block in the hold mode. An apparatus characterized by synthesizing a membership function representing a union of sets represented by.