JP3493931B2 - Method of forming printed circuit board having inspection electrode - Google Patents
Method of forming printed circuit board having inspection electrodeInfo
- Publication number
- JP3493931B2 JP3493931B2 JP02268397A JP2268397A JP3493931B2 JP 3493931 B2 JP3493931 B2 JP 3493931B2 JP 02268397 A JP02268397 A JP 02268397A JP 2268397 A JP2268397 A JP 2268397A JP 3493931 B2 JP3493931 B2 JP 3493931B2
- Authority
- JP
- Japan
- Prior art keywords
- forming
- layer
- resist layer
- conductor layer
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Measuring Leads Or Probes (AREA)
Description
【発明の詳細な説明】
【0001】
【発明の属する技術分野】本発明は、半導体装置や配線
回路基板の導通検査をするために用いられる検査電極を
有する配線回路基板の形成方法に関する。
【0002】
【従来の技術】従来、半導体装置や配線回路基板の導通
検査には、ウェハプローブや布線検査で知られるように
被検査体の電極部に針状の検査電極を接触させ導通テス
トを行っていた。また、比較的配線密度の低い配線回路
基板では電極を有する検査用の配線回路基板を形成し、
異方性導電シートを介して被検査体である配線回路基板
との接触を採り、導通テストを行っている。
【0003】
【発明が解決しようとする課題】従来のウェハプローブ
や布線検査による半導体装置や配線回路基板の導通検査
の方法では、針状の検査電極を接触させるため、被検査
体に検査痕を残し、さらには被検査体に電極の貫通のよ
うな重大な損傷を与える可能性がある。また、配線密度
の増加や高集積化によっては、検査用のプローブの形成
が困難であった。検査基板を用いる方法では、異方性導
電シートの導通ピッチの関係などから200μmピッチ
程度の被検査体には対応できるが、それ以上の微細ピッ
チの検査には対応することが出来ない。また、異方性導
電シートの使用では接触抵抗が高く、また配線抵抗の上
昇を招き導通検査の信頼性を低下させる原因になってい
た。本発明は上記問題を解決するためになされたもの
で、被検査体に検査痕を残さないで、且つ微細ピッチの
検査に対応できる検査電極を有する配線回路基板の形成
方法を提供する。
【0004】
【課題を解決するための手段】本発明において上記課題
を解決するため、下記の一連の工程からなる検査電極を
有する配線回路基板の形成方法としたものである。
(a)ベース基板1上にレジスト層2を形成する工程。
(b)ベース基板1及びレジスト層2に貫通孔3を形成
する工程。
(c)貫通孔3が形成されたレジスト層2a上の貫通孔
3を含む全面にレジスト層4を形成すると同時に凸部5
を形成する工程。
(d)貫通孔3が形成されたレジスト層2a及びベース
基板1a上全面に薄膜導体層を形成する工程。
(e)前記薄膜導体層上にめっきレジスト層6を形成
し、パターニング処理してめっきレジストパターン6a
を形成する工程。
(f)めっきレジストパターン6aをマスクにして薄膜
導体層上に電解めっきによって配線導体層7を形成する
工程。
(g)めっきレジストパターン6a及びめっきレジスト
パターン6a下部の薄膜導体層を除去し配線回路を形成
する工程。
(h)配線導体層7を含む配線回路を形成したベース基
板1a上の、配線導体層7側の全面に絶縁樹脂層8を形
成する工程。
(i)レジスト層4及び貫通孔が形成されたレジスト層
2aを除去し、先端部が半球状の窪みを有する検査電極
9を形成する工程。
上記の形成方法で作製された検査電極を有する配線回路
基板は、今まで対応することが出来なかった微細ピッチ
にも対応することができ、さらに、電極先端部に半球状
の窪みを形成したことで検査時の接触を確実にし、電極
内部に樹脂層を有し、さらに、基板全体で被検査体の凹
凸を吸収するため、被検査体への損傷を防止することが
できる。また、接触抵抗も低くでき、配線抵抗の上昇も
発生せずに検査することができる。
【0005】
【0006】
【発明の実施の形態】本発明の電極を有する配線回路基
板の形成方法は、ベース基板1上にレジスト層2を形成
し、ベース基板1及びレジスト層2に貫通孔3を形成す
る。次に、貫通孔3が形成されたレジスト層2a上にさ
らにレジスト層4を形成すると同時に凸部5を形成す
る。次に、貫通孔3が形成されたベース基板1a及びレ
ジスト層2a上に薄膜導体層を形成し、セミアディティ
ブ法によって配線導体層7及び配線回路を形成する。さ
らに、配線導体層7を含む配線回路基板上に絶縁樹脂層
8を形成し、検査電極内部に樹脂を充填する。レジスト
層4及び貫通孔が形成されたレジスト層2aを除去する
ことにより、先端部が半球状の窪みを有する検査電極9
が形成され、検査電極を有する配線回路基板を作製する
ものである(図1(a)〜(i)参照)。以下、検査電
極を有する配線回路基板の形成方法の詳細について述べ
る。
【0007】ベース基板1は、耐薬品性,耐熱性が高
く、温度変化によって熱膨張や収縮が発生しないものが
望ましい。具体的には、ポリイミドフィルム20〜50
μm を使用する。
【0008】ベース基板1上に形成するレジスト層2
は、一般にエッチングレジストとして知られているドラ
イフィルムレジストを使用することができる。厚みの均
一なドライフィルムの使用によって検査電極高さの制御
が容易になる。検査電極高さに応じてドライフィルムの
厚みを選定する。
【0009】貫通孔3の形成には、レーザ加工を使用す
る。レーザ加工には、エキシマレーザ加工あるいは短パ
ルスの炭酸ガスレーザ加工などが使用できる。これらの
レーザ加工法は形成する検査電極の大きさによって選択
することが望ましい。検査電極径が100〜200μm
の場合には炭酸ガスレーザ加工が、100μm以下の場
合にはエキシマレーザ加工が適している。レーザ加工の
場合、光学系にマスクを入れることにより様々な形状の
貫通孔を形成できるため、各種任意形状の電極が作製可
能である。
【0010】貫通孔3を形成した後、貫通孔3が形成さ
れたレジスト層2a上にレジスト層4を形成する。レジ
スト層4は貫通孔3がレジスト層4と接する部分に凸部
5を形成し、この凸部5によって検査電極の先端部の形
状を制御するものである。この凸部5はレジスト層4を
例えばフイルム貼り合わせ方式で形成する場合貼り合わ
せ時の加熱、加圧条件を調整することにより出っ張り量
と形状を制御する。このレジスト層4はドライフィルム
レジストの貼り合わせにより形成することができる。
【0011】レジスト層4を形成した後、セミアディテ
ィブ法により配線導体層7の形成を行う。セミアディテ
ィブ法は、基板全面に薄膜導体層を形成した後、めっき
レジスト6を形成し、パターニング処理してめっきレジ
ストパターン6aを形成し、電解めっきによって配線導
体層7を形成し、めっきレジストパターン6a及びめっ
きレジストパターン6a下部の薄膜導体層を除去して配
線回路を形成する方法である。めっきレジストパターン
6a下部の薄膜導体層はソフトエッチングによって除去
する。
【0012】配線導体層7を含む配線回路を形成した基
板上の配線導体層7側の全面に絶縁樹脂層8を形成し、
査電極内部に樹脂を充填する。縁樹脂層8は熱硬化型の
エポキシ樹脂やポリイミド樹脂をスクリーン印刷やスピ
ンコートにより形成できる。樹脂特性としては電極の接
触時に基板の凹凸を吸収できるように柔軟性を有したも
のが良い。これにはゴムフィラーを樹脂に分散すること
によって改善することができる。また、ドライフィルム
タイプの永久レジストを用いても良い。
【0013】絶縁樹脂層8を形成した後、レジスト層4
及び貫通孔が形成されたレジスト層2aを除去すること
により、先端部が半球状の窪みを有する検査電極9が形
成された検査電極を有する配線回路基板を形成すること
ができる。
【0014】以下、実施例について図1(a)〜(i)
を用いて詳細に説明する。
<実施例1>ベース基板1には、30μm厚のポリイミ
ドフィルムを用いる。ベース基板1上にドライフィルム
(DFR:日立化成( 株) 製)をラミネータによって貼
り合わせてレジスト層2を形成する。貼り合わせ条件は
ラミネート温度:100℃、ラミネートスピード:1m
/minで行った(図1(a)参照)。
【0015】次に、ベース基板1及びレジスト層2にエ
キシマレーザ加工機を用いて50μmφの貫通孔3を形
成した(図1(b)参照)。エキシマレーザ加工条件
は、エネルギ密度1.0J/cm2 であった。
【0016】貫通孔3が形成されたレジスト層2a 上に
さらにドライフィルム(DFR:日立化成( 株) 製)を
ラミネータによって貼り合わせてレジスト層4及び凸部
5を形成した(図1(c)参照)。このときの貼り合わ
せ条件はロール温度100℃でロール圧:3kg/cm
2 であった。
【0017】貫通孔3が形成されたベース基板1a及び
レジスト層2a上全面にスパッタ法により銅をスパッタ
リングし、薄膜導体層(図示せず)を形成した。薄膜導
体層の膜厚は3000Åであった。さらに、感光性レジ
スト( PMER: 東京応化工業(株)製) をスピンコー
タを用いて塗布し、めっきレジスト6を形成した(図1
(d)参照)。
【0018】次に、めっきレジスト6をパターニング処
理してめっきレジストパターン6aを形成した(図1
(e)参照)。
【0019】次に、電解銅めっきによりめっきレジスト
パターン6aをマスクにして薄膜導体層上に10μm厚
の銅の配線導体層7を形成し(図1(f)参照)、めっ
きレジストパターン6aを除去して、めっきレジストパ
ターン6a下部の薄膜導体層をソフトエッチングにより
除去して、配線回路を形成した(図1(g)参照)。
【0020】次に、熱硬化型のエポキシ樹脂をスクリー
ン印刷によって配線導体層7を含む配線回路基板上にコ
ーティングし、30μm厚の絶縁樹脂層8を形成し、検
査電極内部に樹脂を充填した(図1(h)参照)。さら
に、絶縁樹脂を完全に硬化させた後、アルカリ溶液(5
%水酸化ナトリウム溶液)でレジスト層4及び貫通孔が
形成されたレジスト層2aを除去して、先端部が半球状
の窪みを有する検査電極9を形成された配線回路基板が
得られた(図1(i)参照)。
【0021】<実施例2>
実施例1と同様の工程によりベース基板1上にレジスト
層2を形成した後、炭酸ガスレーザを用いて100μm
φの貫通孔3を形成した。さらに、実施例1と同様の工
程により、レジスト層4、めっきレジストパターン6
a、配線導体層7及び絶縁樹脂層8を形成し、レジスト
層4及び貫通孔が形成されたレジスト層2aを除去し
て、先端部が半球状の窪みを有する検査電極9が形成さ
れた検査電極を有する配線回路基板が得られた。
【0022】
【発明の効果】本発明の形成方法で作製した検査電極を
有する配線回路基板を用いることにより、今まで対応す
ることが出来なかった微細ピッチにも対応することがで
き、電極先端部に半球状の窪みを形成することで検査時
に電極が傾いても被検査体との接触を確実に得ることが
できる。さらに、被検査基板との接触時に被検査基板を
損傷させることなく導通をとることができる。また、本
発明の形成方法では、電極高さのバラツキを低減できる
ため、被検査基板との接触精度を上げることが可能であ
る。配線回路基板自体が被検査体の凹凸を吸収するため
従来のように異方性導電シートを必要としない。これに
よって接触抵抗が低くさらに配線抵抗の上昇も発生せず
に検査することができる。また、電極の形状も比較的自
由に設定できるため、従来よりも基板設計の自由度を向
上することができる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a printed circuit board having test electrodes used for testing the continuity of a semiconductor device or a printed circuit board. 2. Description of the Related Art Conventionally, in a continuity test of a semiconductor device or a printed circuit board, a continuity test is performed by bringing a needle-shaped test electrode into contact with an electrode portion of an object to be inspected as is known from a wafer probe or a wiring test. Had gone. In addition, a wiring circuit board for inspection having electrodes is formed on a wiring circuit board having a relatively low wiring density,
The continuity test is performed by taking contact with the printed circuit board, which is the test object, via the anisotropic conductive sheet. In a conventional method for inspecting the continuity of a semiconductor device or a printed circuit board by means of a wafer probe or a wiring inspection, a needle-like inspection electrode is brought into contact with the inspection mark, so that an inspection mark is formed on the object to be inspected. And may cause serious damage such as penetration of an electrode to the device under test. Also, it has been difficult to form a probe for inspection due to an increase in wiring density and high integration. The method using an inspection substrate can cope with an object to be inspected having a pitch of about 200 μm due to the conductive pitch of the anisotropic conductive sheet and the like, but cannot cope with an inspection with a finer pitch than that. In addition, the use of an anisotropic conductive sheet has a high contact resistance and causes an increase in wiring resistance, which causes a decrease in reliability of a continuity test. The present invention has been made to solve the above problems, without leaving the test marks in the test subject, and to provide a method of forming a wiring circuit board having testing electrodes to accommodate the inspection of fine pitch. [0004] In order to solve the above-mentioned problems in the present invention, a method of forming a printed circuit board having an inspection electrode, comprising the following series of steps, is provided. (A) forming a resist layer 2 on a base substrate 1; (B) forming a through hole 3 in the base substrate 1 and the resist layer 2; (C) At the same time as forming the resist layer 4 on the entire surface including the through hole 3 on the resist layer 2a in which the through hole 3 is formed, the protrusion 5
Forming a . (D) forming a thin-film conductor layer over the entire surface of the resist layer 2a in which the through holes 3 are formed and the base substrate 1a; (E) A plating resist layer 6 is formed on the thin film conductor layer, and is subjected to a patterning process to form a plating resist pattern 6a.
Forming a. (F) A step of forming the wiring conductor layer 7 on the thin film conductor layer by electrolytic plating using the plating resist pattern 6a as a mask. (G) A step of forming a wiring circuit by removing the plating resist pattern 6a and the thin film conductor layer below the plating resist pattern 6a. (H) Base base on which a wiring circuit including wiring conductor layer 7 is formed
Forming an insulating resin layer 8 on the entire surface of the board 1a on the wiring conductor layer 7 side; (I) A step of removing the resist layer 4 and the resist layer 2a in which the through-holes are formed, and forming an inspection electrode 9 having a hemispherical recess at the tip . The printed circuit board having the inspection electrode manufactured by the above-described forming method can cope with a fine pitch that could not be handled until now, and furthermore, a hemispherical recess is formed at the electrode tip. Thus, the contact at the time of inspection is ensured, the resin layer is provided inside the electrode, and the unevenness of the object to be inspected is absorbed by the entire substrate, so that damage to the object to be inspected can be prevented. In addition, the contact resistance can be reduced, and the inspection can be performed without increasing the wiring resistance. A method of forming a printed circuit board having electrodes according to the present invention comprises forming a resist layer 2 on a base substrate 1, and forming through holes 3 in the base substrate 1 and the resist layer 2. To form Next, a resist layer 4 is further formed on the resist layer 2a in which the through holes 3 are formed, and at the same time, a convex portion 5 is formed. Next, a thin-film conductor layer is formed on the base substrate 1a and the resist layer 2a in which the through holes 3 are formed, and a wiring conductor layer 7 and a wiring circuit are formed by a semi-additive method. Further, an insulating resin layer 8 is formed on the printed circuit board including the wiring conductor layer 7, and the inside of the inspection electrode is filled with resin. By removing the resist layer 4 and the resist layer 2a in which the through holes are formed, the inspection electrode 9 having a hemispherical recess at the tip end is formed.
Are formed to produce a printed circuit board having inspection electrodes (see FIGS. 1A to 1I). Hereinafter, we describe details of the method for forming a wiring circuit board having testing electrodes. It is desirable that the base substrate 1 has high chemical resistance and heat resistance and does not undergo thermal expansion or contraction due to a change in temperature. Specifically, polyimide films 20 to 50
Use μm. A resist layer 2 formed on a base substrate 1
Can be used a dry film resist generally known as an etching resist. The use of a dry film having a uniform thickness facilitates control of the inspection electrode height. Select the thickness of the dry film according to the inspection electrode height. Laser processing is used to form the through holes 3. Excimer laser processing or short-pulse carbon dioxide laser processing can be used for laser processing. These laser processing methods are desirably selected depending on the size of the inspection electrode to be formed. Inspection electrode diameter is 100-200μm
In the case of (1), carbon dioxide laser processing is suitable, and in the case of 100 μm or less, excimer laser processing is suitable. In the case of laser processing, various shapes of through-holes can be formed by inserting a mask into the optical system, so that various types of electrodes can be manufactured. After forming the through holes 3, a resist layer 4 is formed on the resist layer 2a in which the through holes 3 are formed. The resist layer 4 forms a convex portion 5 at a portion where the through hole 3 is in contact with the resist layer 4, and controls the shape of the tip portion of the inspection electrode by the convex portion 5. In the case where the resist layer 4 is formed by, for example, a film bonding method, the protrusions 5 control the amount and shape of the protrusion by adjusting the heating and pressing conditions during bonding. This resist layer 4 can be formed by laminating a dry film resist. After forming the resist layer 4, a wiring conductor layer 7 is formed by a semi-additive method. In the semi-additive method, after a thin film conductor layer is formed on the entire surface of a substrate, a plating resist 6 is formed, a patterning process is performed to form a plating resist pattern 6a, a wiring conductor layer 7 is formed by electrolytic plating, and a plating resist pattern 6a is formed. And a method of forming a wiring circuit by removing the thin film conductor layer below the plating resist pattern 6a. The thin film conductor layer below the plating resist pattern 6a is removed by soft etching. An insulating resin layer 8 is formed on the entire surface of the substrate on which the wiring circuit including the wiring conductor layer 7 is formed on the wiring conductor layer 7 side ,
The resin is filled inside the inspection electrode. The edge resin layer 8 can be formed by screen printing or spin coating of a thermosetting epoxy resin or a polyimide resin. As the resin characteristics, those having flexibility so that the unevenness of the substrate can be absorbed when the electrodes are in contact with each other are preferable. This can be improved by dispersing the rubber filler in the resin. Further, a dry film type permanent resist may be used. After forming the insulating resin layer 8, the resist layer 4
By removing the resist layer 2a in which the through-holes are formed, it is possible to form the printed circuit board having the test electrodes on which the test electrodes 9 having the hemispherical recesses are formed. An embodiment will now be described with reference to FIGS. 1 (a) to 1 (i).
This will be described in detail with reference to FIG. Example 1 A 30 μm thick polyimide film is used for the base substrate 1. A dry film (DFR: manufactured by Hitachi Chemical Co., Ltd.) is laminated on a base substrate 1 by a laminator to form a resist layer 2. Lamination conditions: lamination temperature: 100 ° C, lamination speed: 1 m
/ Min (see FIG. 1A). Next, through holes 3 having a diameter of 50 μm were formed in the base substrate 1 and the resist layer 2 using an excimer laser processing machine (see FIG. 1B). Excimer laser processing conditions were an energy density of 1.0 J / cm 2 . A dry film (DFR: manufactured by Hitachi Chemical Co., Ltd.) is further laminated on the resist layer 2a in which the through holes 3 are formed by a laminator to form a resist layer 4 and a projection 5 (FIG. 1 (c)). reference). The bonding conditions at this time are as follows: roll temperature: 100 ° C., roll pressure: 3 kg / cm
Was 2 . Copper was sputtered by sputtering over the entire surface of the base substrate 1a and the resist layer 2a in which the through holes 3 were formed, thereby forming a thin-film conductor layer (not shown). The thickness of the thin film conductor layer was 3000 °. Further, a photosensitive resist (PMER: manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied using a spin coater to form a plating resist 6 (FIG. 1).
(D)). Next, the plating resist 6 is patterned to form a plating resist pattern 6a (FIG. 1).
(E)). Next, a copper wiring conductor layer 7 having a thickness of 10 μm is formed on the thin film conductor layer by electrolytic copper plating using the plating resist pattern 6a as a mask (see FIG. 1 (f)), and the plating resist pattern 6a is removed. Then, the thin film conductor layer below the plating resist pattern 6a was removed by soft etching to form a wiring circuit (see FIG. 1 (g)). Next, a thermosetting epoxy resin is coated on the printed circuit board including the wiring conductor layer 7 by screen printing to form an insulating resin layer 8 having a thickness of 30 μm, and the inside of the inspection electrode is filled with resin ( FIG. 1 (h)). Further, after the insulating resin is completely cured, an alkaline solution (5
% Sodium hydroxide solution) to remove the resist layer 4 and the resist layer 2a in which the through-holes are formed, thereby obtaining a printed circuit board on which the test electrode 9 having a hemispherical recess at the tip is formed (FIG. 1 (i)). <Embodiment 2> After forming a resist layer 2 on a base substrate 1 in the same process as in Embodiment 1, 100 μm was formed using a carbon dioxide gas laser.
A through hole 3 of φ was formed. Further, the resist layer 4, the plating resist pattern 6
a, of forming a wiring conductor layer 7 and the insulating resin layer 8, the resist layer 2a resist layer 4 and the through holes are formed by removing, inspection electrodes 9 the tip portion has a hemispherical recess formed
A printed circuit board having the inspection electrodes obtained was obtained. By using the printed circuit board having the inspection electrodes manufactured by the forming method of the present invention, it is possible to cope with fine pitches which could not be dealt with up to now, and to provide the electrode tip portion. By forming a hemispherical recess in the test piece, contact with the test object can be reliably obtained even if the electrode is inclined during the test. Further , conduction can be achieved without damaging the substrate to be inspected at the time of contact with the substrate to be inspected. Also book
According to the forming method of the present invention, variation in the electrode height can be reduced , so that the contact accuracy with the substrate to be inspected can be increased. Since the printed circuit board itself absorbs the unevenness of the object to be inspected, an anisotropic conductive sheet is not required unlike the related art. As a result, the inspection can be performed without low contact resistance and no increase in wiring resistance. In addition, since the shape of the electrode can be set relatively freely, the degree of freedom in designing the substrate can be improved as compared with the related art.
【図面の簡単な説明】
【図1】(a)〜(i)は、本発明の検査電極を有する
配線回路基板の形成方法の一実施例の形成工程を示す部
分断面図であるBRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to 1 (i) are partial cross-sectional views showing forming steps of one embodiment of a method for forming a printed circuit board having test electrodes according to the present invention.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) G01R 1/06 - 1/073 G01R 31/02 H01L 21/3205 H01L 21/66 H05K 3/00 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) G01R 1/06-1/073 G01R 31/02 H01L 21/3205 H01L 21/66 H05K 3/00
Claims (1)
る配線回路基板の形成方法。 (a)ベース基板(1)上にレジスト層(2)を形成す
る工程。 (b)ベース基板(1)及びレジスト層(2)に貫通孔
(3)を形成する工程。 (c)貫通孔(3)が形成されたレジスト層(2a)上
の貫通孔(3)を含む全面にレジスト層(4)を形成す
ると同時に凸部(5)を形成する工程。 (d)貫通孔(3)が形成されたレジスト層(2a)及
びベース基板(1a)上全面に薄膜導体層を形成する工
程。 (e)前記薄膜導体層上にめっきレジスト層(6)を形
成し、パターニング処理してめっきレジストパターン
(6a)を形成する工程。 (f)めっきレジストパターン(6a)をマスクにして
薄膜導体層上に電解めっきによって配線導体層(7)を
形成する工程。 (g)めっきレジストパターン(6a)及びめっきレジ
ストパターン(6a)下部の薄膜導体層を除去し配線回
路を形成する工程。 (h)配線導体層(7)を含む配線回路を形成したベー
ス基板(1a)上の、配線導体層(7)側の全面に絶縁
樹脂層(8)を形成する工程。 (i)レジスト層(4)及び貫通孔が形成されたレジス
ト層(2a)を除去し、先端部が半球状の窪みを有する
検査電極(9)を形成する工程。(57) [Claim 1] A method for forming a printed circuit board having an inspection electrode, comprising the following series of steps. (A) forming a resist layer (2) on a base substrate (1); (B) forming a through hole (3) in the base substrate (1) and the resist layer (2); (C) Forming a resist layer (4) on the entire surface including the through hole (3) on the resist layer (2a) in which the through hole (3) has been formed, and simultaneously forming the convex portion (5). the step of. (D) forming a thin-film conductor layer on the entire surface of the resist layer (2a) in which the through-holes (3) are formed and the base substrate (1a); (E) forming a plating resist layer (6) on the thin-film conductor layer and patterning to form a plating resist pattern (6a); (F) forming a wiring conductor layer (7) on the thin film conductor layer by electrolytic plating using the plating resist pattern (6a) as a mask; (G) a step of forming a wiring circuit by removing the plating resist pattern (6a) and the thin film conductor layer below the plating resist pattern (6a). (H) base forming a wiring circuit including the wiring conductor layer (7)
Forming an insulating resin layer (8) on the entire surface of the substrate (1a) on the side of the wiring conductor layer (7) . (I) a step of removing the resist layer (4) and the resist layer (2a) in which the through-holes are formed, and forming a test electrode (9) having a hemispherical recess at the tip .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02268397A JP3493931B2 (en) | 1997-02-05 | 1997-02-05 | Method of forming printed circuit board having inspection electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP02268397A JP3493931B2 (en) | 1997-02-05 | 1997-02-05 | Method of forming printed circuit board having inspection electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10221372A JPH10221372A (en) | 1998-08-21 |
| JP3493931B2 true JP3493931B2 (en) | 2004-02-03 |
Family
ID=12089673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP02268397A Expired - Fee Related JP3493931B2 (en) | 1997-02-05 | 1997-02-05 | Method of forming printed circuit board having inspection electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3493931B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102321112B1 (en) * | 2020-05-22 | 2021-11-04 | 리노공업주식회사 | A fabricating method of the test socket |
| KR102321126B1 (en) * | 2020-05-22 | 2021-11-04 | 리노공업주식회사 | A fabricating method of the test socket |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3646720B2 (en) * | 2003-06-19 | 2005-05-11 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
| US8493071B1 (en) * | 2009-10-09 | 2013-07-23 | Xilinx, Inc. | Shorted test structure |
| US8802454B1 (en) | 2011-12-20 | 2014-08-12 | Xilinx, Inc. | Methods of manufacturing a semiconductor structure |
-
1997
- 1997-02-05 JP JP02268397A patent/JP3493931B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102321112B1 (en) * | 2020-05-22 | 2021-11-04 | 리노공업주식회사 | A fabricating method of the test socket |
| KR102321126B1 (en) * | 2020-05-22 | 2021-11-04 | 리노공업주식회사 | A fabricating method of the test socket |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10221372A (en) | 1998-08-21 |
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