JP3495010B2 - Information processing apparatus and calculation method in information processing apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a configuration and a calculation method of an information processing apparatus for dramatically improving processing performance by a parallel processor, and more particularly to speeding up of numerical calculation of differential equations. is there.

[0002]

2. Description of the Related Art In the solution of a differential equation, which is the main field of application of the present invention, the equation of interest is differentiated in an analysis time space that is discretized spatially and temporally, and the interaction between adjacent lattice points is used. Seeking a solution. Conventionally, these problems have been analyzed by the sequential calculation method by Neumann type computer or the parallel calculation method on a multiprocessor.

Further, in recent years, large-scale numerical analysis and prediction of heat and fluid have been performed in, for example, weather forecasts and environmental assessments such as atmospheric and marine pollution. In the weather forecast, the movement of the atmosphere is predicted, and the movement of high / low pressure and the course of a typhoon are predicted based on the atmospheric pressure, wind speed, temperature, and solar radiation, and the weather forecast is issued. In the environmental assessment, how the pollution source is diffused by the atmospheric and ocean currents is estimated by estimating the flow velocity and the pollutant concentration. A large number of super-large-scale computers are put in there, and a great deal of calculation time is spent. Thus, efforts have been made to invest a large amount of computer resources, improve calculation speed and prediction accuracy, prevent disasters caused by wind and rain, and prevent environmental damage. A method of dealing with this kind of problem on a multiprocessor has been tried, and the Japan Society of Mechanical Engineers, Vol. 59, No. 558, PP. 427-432 (reference 1) or the Japan Society of Mechanical Engineers, Volume 60, 569, P.
P. 99-106 (reference 2), a discretized analysis area is divided into blocks, each divided area is assigned to one element processor, and a multiprocessor system composed of a plurality of element processors as a whole. A domain division method that performs parallel processing is used.

FIG. 68 is a block diagram of the entire system for performing the area division method by connecting the element processors shown in Document 1 which is a conventional example with a near neighbor mesh. In the figure, 201 is an element processor that performs the operation of a divided area in charge, 202 is an inter-element processor connection for performing data communication between the element processors 201, 203 is a host computer for centrally managing the element processors 201, and 204 is An interface board for connecting the host computer 203 and the element processor 201, and 205 is an element processor board on which four element processors 201 are mounted.

Further, in the conventional example in Document 2, a general-purpose parallel computer AP1000 is used and an element processor 201 is used.
Are connected by a similar near neighbor mesh.

In the parallel computing method utilizing these general-purpose multiprocessor systems, low-speed communication means such as packet communication is used as the communication method between the processors. Further, since it is necessary to synchronize the processing between the processors, there is an overhead in data transfer between the element processors 201, and the parallelization efficiency decreases as the number of element processors 201 increases. FIG. 69 shows a situation in which parallelization efficiency is lowered with an increase in the number of element processors when the numerical fluid analysis, which is one application example of the partial differential equation solving method shown in Document 2, is performed using the difference method. It is a figure. In the figure, the horizontal axis is the number of element processors 201, the vertical axis is the calculation speed improvement rate, the circle is the calculation speed improvement rate when the MAC method is used, and the triangle is the calculation speed improvement rate when the SMAC method is used. A mark indicates a calculation speed improvement rate when the HSMAC method is used, and a solid line indicates a calculation speed improvement rate proportional to the number of the element processors 201. MAC method, SMAC method, HSM
With the AC method, as the number of element processors 201 increases, the parallelization efficiency decreases due to the increase in the number of element processors 201 due to the overhead of data transfer.

Further, focusing on the parallelism at the operation level in analyzing the partial differential equation, in the conventional numerical solution method using the existing hardware, the hardware architecture attaches importance to versatility. , It was impossible to incorporate into the parallel processing the high level of parallelism that appears at the time of analysis of partial differential equations.

That is, even if a large Neumann type computer or a general-purpose parallel computer is used, a large-scale PDE can be executed at high speed.
Moreover, it was difficult to analyze at low cost.

[0009]

Since the conventional differential equation solving method is the above-described method, nCUBE,
AP-1000, Transputer
er) and other general-purpose parallel processors were used to solve partial differential equations by the domain decomposition method. The communication system between these multiprocessors uses low-speed communication means such as packet communication. As long as the existing hardware architecture is followed, parallel processing between processors and parallel processing must be emphasized. In other words, the solution by the domain division method had some effect on coarse-grain parallel processing in which the calculation time occupies a large proportion of the total calculation time, but the calculation time that appears in the differential equation analysis In the fine-grain parallel processing, which has a large proportion of communication time as compared with, there was a problem that the overhead during data transfer becomes large and the parallelization efficiency decreases.

Various methods have been devised to improve latency tolerance (coping with the data waiting problem) by improving software. However, as long as existing hardware is used, the communication method is drastically changed. However, there is a problem that it is impossible to dramatically reduce the communication synchronization waiting time.

Further, there is a problem that the parallelism at the operation level in the processor depends on the architecture of the hardware and cannot be dealt with at the software level.

The present invention has been made to solve the above problems, and a first object of the present invention is to improve the latency tolerance by asynchronously transmitting a message between element processors. It is to obtain an information processing device capable of performing.

The present invention has been made to solve the above problems, and a second object of the present invention is to provide a memory structure in which processing in the element processor is not hindered by communication. It is to obtain an information processing device capable of performing a memory access method suitable for solving a differential equation.

Further, the present invention has been made to solve the above-mentioned problems, and a third object of the present invention is to arrange an arithmetic unit in which a wiring logic is directly implemented as hardware in a processor. An object of the present invention is to obtain an information processing device capable of maximizing the parallelism at the operation level, which is inherent in the numerical analysis method based on the thermal fluid numerical analysis and other partial differential equation solving methods.

[0015]

An information processing apparatus according to a first invention comprises a plurality of element processors and a plurality of data buses connecting between the element processors adjacent to each other,
A grid-discretized calculation space used when solving a field governing equation that can be described by a predetermined equation is divided into a plurality of regions, and the element processors are assigned to each of the plurality of regions, and parallelized. In the information processing device for performing repetitive arithmetic operations, one of the element processors is adjacent to each other in the iterative operation process regardless of the operation process of the other adjacent element processors. The data of the grid point of the boundary portion between the regions is updated, and the other element processor determines whether the data of the grid point of the boundary portion related to the one element processor is updated by the one element processor. Regardless of the above, the iterative calculation is performed while referring to the data of the lattice points of the boundary portion according to the one element processor via the data bus. The element processor has a processing unit for executing an operation and a data memory for storing various data related to the operation, and the one element processor stores the data of the grid point of the boundary portion in its own Writing to a data memory, the other element processor refers to the data of the grid point of the boundary portion stored in the data memory of the one element processor, and the processing unit,
An inside point bit and an outside point bit indicating whether the position where the grid point exists for all of the grid points is inside the calculation area in the field, or inside or outside the object in the calculation area, and Boundary condition bits that give information of boundary conditions to the grid points located at the boundary of the calculation area are loaded in the data memory of the element processor, and the inner point bits, the outer point bits, and the boundary condition bits are loaded. It is characterized by further comprising a hardware circuit according to the same wiring logic that can change the processing of the data flow graph according to the bit.

An information processing apparatus according to a second aspect of the present invention includes a plurality of element processors and a plurality of data buses that connect the element processors adjacent to each other, and solves a governing equation of a field that can be described by a predetermined equation. In an information processing device that divides a calculation space discretized into a grid used in the case into a plurality of regions, allocates the element processors to each of the plurality of regions, and performs operations in parallel and iteratively. Therefore, the one element processor updates the data of the grid point at the boundary between the adjacent areas in the iterative operation process regardless of the operation process in the other adjacent element processors. In the other element processor, the data of the grid point of the boundary portion related to the one element processor is updated by the one element processor. Regardless of whether or not the element processor executes the operation while referring to the data of the grid point of the boundary portion of the one element processor via the data bus, the element processor executes the operation. A processing unit and a data memory for storing various data relating to operations, wherein the one element processor writes the data at the grid point of the boundary portion in its own data memory, and the other element processor. Refers to the data of the grid point of the boundary portion stored in the data memory of the one element processor, and combines the adjacent element processors with a fine node connection, and one or more of the elements. Having a coarse node connection in which the element processors are skipped over and the element processors are connected to each other by a coarse node connection. And it features.

A calculation method in an information processing apparatus according to a third aspect of the present invention comprises a plurality of element processors and a plurality of data buses connecting the element processors adjacent to each other.
A grid-discretized calculation space used when solving a field governing equation that can be described by a predetermined equation is divided into a plurality of regions, and the element processors are assigned to each of the plurality of regions, and parallelized. And (a) a calculation method using an information processing device for repetitively performing an operation, wherein one element processor has an operation step in another element processor adjacent thereto in the process of iterative operation. Regardless of the above, updating the data of the grid points at the boundary between the adjacent areas, and (b) the other element processor, Regardless of whether the data has been updated by the one element processor, the data of the grid point of the boundary portion of the one element processor is transferred to the data buffer. And performing a repetitive operation, the predetermined equation includes a differential equation, and the element processor is operated asynchronously and independently to obtain a solution of the differential equation by a difference method. Is obtained by using.

A calculation method in an information processing apparatus according to a fourth aspect of the present invention comprises a plurality of element processors and a plurality of data buses connecting the element processors adjacent to each other,
A grid-discretized calculation space used when solving a field governing equation that can be described by a predetermined equation is divided into a plurality of regions, and the element processors are assigned to each of the plurality of regions, and parallelized. And (a) a calculation method using an information processing device for repetitively performing an operation, wherein one element processor has an operation step in another element processor adjacent thereto in the process of iterative operation. Regardless of the above, updating the data of the grid points at the boundary between the adjacent areas, and (b) the other element processor, Regardless of whether the data has been updated by the one element processor, the data of the grid point of the boundary portion of the one element processor is transferred to the data buffer. And performing a repetitive operation, the element processor having a processing unit for executing the operation and a data memory for storing various data related to the operation, and the step (a) In the step (b), the one element processor writes the data of the grid point of the boundary portion to the data memory of its own, and in the step (b), the other element processor writes the data of the one element processor. With reference to the data of the grid points of the boundary portion stored in the memory, whether the position where the grid points exist for all of the grid points is inside or outside the calculation area in the field,
Alternatively, the inside point bit and the outside point bit indicating whether the object is inside or outside the calculation area, and the boundary condition bit that gives boundary condition information to the grid point located on the boundary of the calculation area are the elements. The processing unit is given in advance to the data memory of the processor, and the processing unit is provided to the element processor by using the same calculation program whose processing can be changed by the interior point bit, the exterior point bit and the boundary condition bit. It is characterized by performing a calculation.

A calculation method in an information processing apparatus according to a fifth aspect of the present invention comprises a plurality of element processors and a plurality of data buses connecting the element processors adjacent to each other.
A grid-discretized calculation space used when solving a field governing equation that can be described by a predetermined equation is divided into a plurality of regions, and the element processors are assigned to each of the plurality of regions, and parallelized. And (a) a calculation method using an information processing device for repetitively performing an operation, wherein one element processor has an operation step in another element processor adjacent thereto in the process of iterative operation. Regardless of the above, updating the data of the grid points at the boundary between the adjacent areas, and (b) the other element processor, Regardless of whether the data has been updated by the one element processor, the data of the grid point of the boundary portion of the one element processor is transferred to the data buffer. And performing a repetitive operation, the element processor having a processing unit for executing the operation and a data memory for storing various data related to the operation, and the step (a) In the step (b), the one element processor writes the data of the grid point of the boundary portion to the data memory of its own, and in the step (b), the other element processor writes the data of the one element processor. With reference to the data of the grid points of the boundary portion stored in the memory, the processing unit determines whether the positions where the grid points exist for all the grid points are inside the calculation area in the field. , Or an inside point bit and an outside point bit indicating whether the object is inside or outside the calculation area,
Further, a boundary condition bit that gives boundary condition information to the grid point located on the boundary of the calculation area is loaded in the data memory of the element processor, and the inner point bit, the outer point bit, and the boundary. The information processing apparatus further comprises a hardware circuit according to the same wiring logic capable of changing the processing of the data flow graph according to the condition bit.

A calculation method in an information processing apparatus according to a sixth aspect of the present invention comprises a plurality of element processors and a plurality of data buses connecting between the element processors adjacent to each other,
A grid-discretized calculation space used when solving a field governing equation that can be described by a predetermined equation is divided into a plurality of regions, and the element processors are assigned to each of the plurality of regions, and parallelized. And (a) a calculation method using an information processing device for repetitively performing an operation, wherein one element processor has an operation step in another element processor adjacent thereto in the process of iterative operation. Regardless of the above, updating the data of the grid points at the boundary between the adjacent areas, and (b) the other element processor, Regardless of whether the data has been updated by the one element processor, the data of the grid point of the boundary portion of the one element processor is transferred to the data buffer. And performing a repetitive operation, the element processor having a processing unit for executing the operation and a data memory for storing various data related to the operation, and the step (a) In the step (b), the one element processor writes the data of the grid point of the boundary portion to the data memory of its own, and in the step (b), the other element processor writes the data of the one element processor. Communication for solving the governing equation of the field because the data of the grid point of the boundary portion stored in the memory is referred to and the grid point to be calculated is on the boundary with the adjacent region. It is characterized in that the number of times of communication at all the grid points is leveled by performing dummy communication for the grid points having a small number of times.

A calculation method in an information processing apparatus according to a seventh invention comprises a plurality of element processors and a plurality of data buses connecting between the element processors adjacent to each other,
A grid-discretized calculation space used when solving a field governing equation that can be described by a predetermined equation is divided into a plurality of regions, and the element processors are assigned to each of the plurality of regions, and parallelized. And (a) a calculation method using an information processing device for repetitively performing an operation, wherein one element processor has an operation step in another element processor adjacent thereto in the process of iterative operation. Regardless of the above, updating the data of the grid points at the boundary between the adjacent areas, and (b) the other element processor, Regardless of whether the data has been updated by the one element processor, the data of the grid point of the boundary portion of the one element processor is transferred to the data buffer. And performing a repetitive operation, the element processor having a processing unit for executing the operation and a data memory for storing various data related to the operation, and the step (a) In the step (b), the one element processor writes the data of the grid point of the boundary portion to the data memory of its own, and in the step (b), the other element processor writes the data of the one element processor. An operation for solving the governing equation of the field because the grid point of the boundary part stored in the memory is referred to and the grid point to be calculated is on the boundary with the adjacent area. It is characterized in that the number of calculations at all the grid points is leveled by performing a dummy calculation for the grid points having a small number of times.

A calculation method in an information processing apparatus according to an eighth invention comprises a plurality of element processors and a plurality of data buses connecting the element processors adjacent to each other,
A grid-discretized calculation space used when solving a field governing equation that can be described by a predetermined equation is divided into a plurality of regions, and the element processors are assigned to each of the plurality of regions, and parallelized. And (a) a calculation method using an information processing device for repetitively performing an operation, wherein one element processor has an operation step in another element processor adjacent thereto in the process of iterative operation. Regardless of the above, updating the data of the grid points at the boundary between the adjacent areas, and (b) the other element processor, Regardless of whether the data has been updated by the one element processor, the data of the grid point of the boundary portion of the one element processor is transferred to the data buffer. And performing a repetitive operation, the element processor having a processing unit for executing the operation and a data memory for storing various data related to the operation, and the step (a) In the step (b), the one element processor writes the data of the grid point of the boundary portion to the data memory of its own, and in the step (b), the other element processor writes the data of the one element processor. To refer to the data of the grid points of the boundary part stored in the memory, and when the adjacent grid points are allocated to the different element processors, both element processors transmit to each other. If there are two sets of data in time series and the data for these grid points are updated, the updated data Characterized in that but not the rewriting of the other party of the data if the predetermined value or less displacement compared to the time-series manner before the set of data.

A calculation method in an information processing apparatus according to a ninth aspect comprises a plurality of element processors and a plurality of data buses connecting the element processors adjacent to each other,
A grid-discretized calculation space used when solving a field governing equation that can be described by a predetermined equation is divided into a plurality of regions, and the element processors are assigned to each of the plurality of regions, and parallelized. And (a) a calculation method using an information processing device for repetitively performing an operation, wherein one element processor has an operation step in another element processor adjacent thereto in the process of iterative operation. Regardless of the above, updating the data of the grid points at the boundary between the adjacent areas, and (b) the other element processor, Regardless of whether the data has been updated by the one element processor, the data of the grid point of the boundary portion of the one element processor is transferred to the data buffer. And performing a repetitive operation, the element processor having a processing unit for executing the operation and a data memory for storing various data related to the operation, and the step (a) In the step (b), the one element processor writes the data of the grid point of the boundary portion to the data memory of its own, and in the step (b), the other element processor writes the data of the one element processor. By referring to the data of the grid points of the boundary portion stored in the memory, a fine node connection in which the adjacent element processors are connected to each other, and one or more of the element processors are skipped and the element processors are roughly connected to each other. It is characterized in that the information processing apparatus having the coarse node connection connected by the node connection connection is used.

[0024]

According to the first aspect of the present invention, data communication is performed between the adjacent element processors by the data bus, and the element processors operate asynchronously and independently using the data to perform calculation. Communication time can be shortened.

Further, the data communication between the adjacent element processors in the first aspect of the invention is performed asynchronously and repeatedly for each element processor, so that the operation performed on each element processor is performed by the adjacent element processors. It is possible to continue the processing completely asynchronously without hindering the processing. That is, it is possible to communicate between the adjacent element processors without hindering the operation of the adjacent element processors.

Further, the element processor according to the first aspect of the present invention directly refers to the data memory of the adjacent element processors to facilitate data communication between the element processors adjacent to each other, asynchronously for each processing unit. And can be repeated.

Furthermore, in the processing unit according to the first aspect of the present invention, the existence of grid points for all grid points allows the calculation by a hardware circuit according to the same wiring logic regardless of the kind of grid points. The inside point bit and the outside point bit indicating whether the position to be calculated is inside the calculation area in the field, or inside or outside the object in the calculation area, and the boundary condition of the grid point located on the calculation area boundary. Boundary condition bits that provide information are loaded into the data memory of the element processor, and the processing of the data flow graph is changed according to the inside point bits, outside point bits, and boundary condition bits.

According to the data bus of the second invention,
Data communication is performed between adjacent element processors, and by using the data, the element processors operate asynchronously and independently of each other to perform calculation, whereby the communication time between the element processors can be shortened.

Further, the data communication between the adjacent element processors according to the second aspect of the present invention is performed asynchronously and repeatedly for each element processor, so that the operation performed on each element processor is performed by the adjacent element processors. It is possible to continue the processing completely asynchronously without hindering the processing. That is, it is possible to communicate between the adjacent element processors without hindering the operation of the adjacent element processors.

Further, the element processor according to the second aspect of the present invention, by directly referring to the data memory of the adjacent element processor, facilitates data communication between the element processors adjacent to each other, asynchronously for each processing unit. And can be repeated.

Furthermore, in the second invention, a fine node connection in which adjacent element processors are connected to each other, and a coarse node connection in which one or more element processors are skipped and the element processors are connected to each other by a coarse node connection connection. With the above, it is possible to proceed with the calculation by using the coarse node connection and the fine node connection, and to reduce the calculation time without lowering the accuracy.

According to the data bus of the third invention,
Data communication is performed between adjacent element processors, and by using the data, the element processors operate asynchronously and independently of each other to perform calculation, whereby the communication time between the element processors can be shortened.

The data communication between the adjacent element processors according to the third aspect of the present invention is performed asynchronously and repeatedly for each element processor, so that the operation performed on each element processor is performed by the adjacent element processors. It is possible to continue the processing completely asynchronously without hindering the processing. That is, it is possible to communicate between the adjacent element processors without hindering the operation of the adjacent element processors.

Further, the predetermined equation in the third invention is a differential equation, and when the solution of the differential equation is obtained by using the difference method, the lattice points adjacent to the lattice point to be calculated are Since the influence of the grid points other than is extremely small, it is possible to obtain a highly accurate analytical solution.

According to the data bus of the fourth invention,
Data communication is performed between adjacent element processors, and by using the data, the element processors operate asynchronously and independently of each other to perform calculation, whereby the communication time between the element processors can be shortened.

The data communication between the adjacent element processors according to the fourth aspect of the invention is performed asynchronously and repeatedly for each element processor, so that the operation performed on each element processor is performed by the adjacent element processors. It is possible to continue the processing completely asynchronously without hindering the processing. That is, it is possible to communicate between the adjacent element processors without hindering the operation of the adjacent element processors.

Furthermore, the element processor according to the fourth aspect of the present invention directly refers to the data memory of the adjacent element processor to facilitate data communication between the element processors adjacent to each other, asynchronously for each processing unit. And can be repeated.

Furthermore, in the processing unit according to the fourth aspect of the present invention, the positions where the grid points exist for all the grid points so that the same calculation program can be used regardless of the kind of the grid points. The inside point bit and the outside point bit indicating whether is inside or outside the calculation area in the field or inside or outside the object in the calculation area. Boundary condition bits giving information are given in advance in the program memory of the element processor, and the processing is changed by the inner point bit, the outer point bit and the boundary condition bit in the element processor.

According to the data bus of the fifth invention,
Data communication is performed between adjacent element processors, and by using the data, the element processors operate asynchronously and independently of each other to perform calculation, whereby the communication time between the element processors can be shortened.

Further, the data communication between the adjacent element processors according to the fifth aspect of the present invention is performed asynchronously and repeatedly for each element processor, whereby the operation performed on each element processor is performed by the adjacent element processors. It is possible to continue the processing completely asynchronously without hindering the processing. That is, it is possible to communicate between the adjacent element processors without hindering the operation of the adjacent element processors.

Further, the element processor according to the fifth aspect of the present invention directly refers to the data memory of the adjacent element processors to facilitate data communication between the element processors adjacent to each other, asynchronously for each processing unit. And can be repeated.

Furthermore, in the processing unit according to the fifth aspect of the present invention, the existence of grid points for all grid points allows the calculation by a hardware circuit according to the same wiring logic regardless of the kind of grid points. The inside point bit and the outside point bit indicating whether the position to be calculated is inside the calculation area in the field, or inside or outside the object in the calculation area, and the boundary condition of the grid point located on the calculation area boundary. Boundary condition bits that provide information are loaded into the data memory of the element processor, and the processing of the data flow graph is changed according to the inside point bits, outside point bits, and boundary condition bits.

According to the data bus of the sixth invention,
Data communication is performed between adjacent element processors, and by using the data, the element processors operate asynchronously and independently of each other to perform calculation, whereby the communication time between the element processors can be shortened.

The data communication between the adjacent element processors according to the sixth aspect of the present invention is performed asynchronously and repeatedly for each element processor, so that the operation performed on each element processor is performed by the adjacent element processors. It is possible to continue the processing completely asynchronously without hindering the processing. That is, it is possible to communicate between the adjacent element processors without hindering the operation of the adjacent element processors.

Further, the element processor according to the sixth aspect of the present invention directly refers to the data memory of the adjacent element processors to facilitate data communication between the element processors adjacent to each other, asynchronously for each processing unit. And can be repeated.

Furthermore, the element processor according to the sixth aspect of the present invention performs dummy communication with respect to a grid point with a small number of times of communication, thereby increasing the number of times of communication of a grid point with a small number of times of communication, and Equalize the number of communication of.

According to the data bus of the seventh invention,
Data communication is performed between adjacent element processors, and by using the data, the element processors operate asynchronously and independently of each other to perform calculation, whereby the communication time between the element processors can be shortened.

The data communication between the adjacent element processors according to the seventh aspect of the invention is performed asynchronously and repeatedly for each element processor, so that the operation performed on each element processor is performed by the adjacent element processors. It is possible to continue the processing completely asynchronously without hindering the processing. That is, it is possible to communicate between the adjacent element processors without hindering the operation of the adjacent element processors.

Further, the element processor according to the seventh aspect of the present invention directly refers to the data memory of the adjacent element processor to facilitate data communication between the element processors adjacent to each other, asynchronously for each processing unit. And can be repeated.

Furthermore, the element processor according to the seventh aspect of the present invention increases the number of times of calculation of the grid points having a small number of calculations by performing a dummy calculation even for the grid points having a small number of calculations so that all the grid points can be calculated. Equalizes the number of calculations of.

According to the data bus of the eighth invention,
Data communication is performed between adjacent element processors, and by using the data, the element processors operate asynchronously and independently of each other to perform calculation, whereby the communication time between the element processors can be shortened.

Further, the data communication between the adjacent element processors according to the eighth aspect of the present invention is performed asynchronously and repeatedly for each element processor, whereby the operation performed on each element processor is performed by the adjacent element processors. It is possible to continue the processing completely asynchronously without hindering the processing. That is, it is possible to communicate between the adjacent element processors without hindering the operation of the adjacent element processors.

Further, the element processor according to the eighth aspect of the present invention directly refers to the data memory of the adjacent element processors to facilitate data communication between the element processors adjacent to each other, asynchronously for each processing unit. And can be repeated.

Furthermore, in the element processor according to the eighth aspect of the invention, when adjacent lattice points are allocated to different element processors, two sets of data transmitted from each other by the other element processors are arranged in time series. If the data for these grid points is updated,
Unnecessary communication between the element processors can be omitted by not rewriting the other party's data if the updated data is displaced by a predetermined value or less compared with the previous set of data in time series. .

According to the data bus of the ninth invention,
Data communication is performed between adjacent element processors, and by using the data, the element processors operate asynchronously and independently of each other to perform calculation, whereby the communication time between the element processors can be shortened.

Further, the data communication between the adjacent element processors in the ninth aspect of the invention is performed asynchronously and repeatedly for each element processor, so that the operation performed on each element processor is performed by the adjacent element processors. It is possible to continue the processing completely asynchronously without hindering the processing. That is, it is possible to communicate between the adjacent element processors without hindering the operation of the adjacent element processors.

Furthermore, the element processor according to the ninth aspect of the present invention directly refers to the data memory of the adjacent element processors to facilitate data communication between the element processors adjacent to each other, asynchronously for each processing unit. And can be repeated.

Furthermore, in the ninth aspect of the invention, a fine node connection in which adjacent element processors are connected to each other and a coarse node connection in which one or more element processors are skipped and the element processors are connected to each other by a coarse node connection connection. With the above, it is possible to proceed with the calculation by using the coarse node connection and the fine node connection, and to reduce the calculation time without lowering the accuracy.

[0059]

BEST MODE FOR CARRYING OUT THE INVENTION <First Embodiment> A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an overall configuration diagram of a multiprocessor according to a first embodiment of the present invention. In FIG. 1, 1 is a host computer that controls arithmetic processing, 2 is an information processing apparatus main body that performs arithmetic processing under the control of the host computer 1, 3 is a spatially arranged element processor that constitutes the information processing apparatus 2, Reference numeral 4 is a network for connecting the host computer 1 and the information processing apparatus 2 to exchange information, 5 is a processing unit provided in each element processor 3 for performing calculation, and 6 is provided in each element processor 3. A memory unit 7 for storing information is an inter-element processor connection for connecting the spatially arranged element processors 3 and exchanging information.

In the information processing apparatus 2 shown in FIG. 1, the connection state of the element processors 3 is shown in the case of a near neighbor mesh arranged in a lattice, but for example, a linear array, ring, star, tree, systolic array, complete array. Other coupling methods such as coupling may be used.

Next, the operation will be described. The host computer 1 sets initial conditions and boundary conditions to the information processing device 2 via the network 4, and sets the information processing device 2
The convergence determination of the internal calculation, the output of the calculation result in the information processing device 2, etc. are performed. The respective element processors 3 are connected to each other via an inter-element processor connection 7 so as to be able to exchange information with each other, and in accordance with a control command sent from the host computer 1 to the information processing apparatus 2 via the network 4, initial conditions and boundary conditions. Is set, information for determining the convergence of calculation is transmitted, and the calculation result is transmitted. A personal computer, a workstation, or the like is used as the host computer 1, and is connected to the information processing device 2 via the network 4.

Each element processor 3 comprises a processing unit 5 and a memory section 6, and stores in the memory section 6 initial conditions and boundary conditions sent from the host computer 1 via the network 4 and the connection 7 between the element processors. Then, after receiving the calculation start token from the host computer 1, the processing unit 5 immediately and independently performs a predetermined arithmetic processing and writes the processed data in the memory unit 6 or the memory unit 6 of the adjacent element processor 3. It has a function to write in and continue calculation.

The element processors 3 are roughly classified into three types according to the hardware configuration method. 2 to 4 are block diagrams showing examples of hardware configuration methods of various element processors 3a to 3c.

In each drawing, 8 is a data memory provided in the memory section 6, 9 is a processor internal data bus provided in the element processor 3 for connecting the processing unit 5 and the data memory 8 and exchanging information. ,
Reference numeral 10 is a floating-point arithmetic unit provided inside the processing unit 5, 11 is a program memory provided inside the processing unit 5, 12 is a functional module also provided inside the processing unit 5, 13
Is a data flow graph-shaped hardware circuit provided in the processing unit 5 in accordance with the wiring logic, 14 is an arithmetic unit arranged according to the data flow graph 13, 1
Reference numeral 5 is a data line connecting the arithmetic units 14 according to the data flow graph 13.

The maximum degree of parallelism at the instruction level can be realized by implementing all the operations necessary for the solution of the differential equation by hardware. In the multiprocessor solution based on the domain decomposition method, the parallelism at the instruction level of each processor depends on the architecture of the processor and does not correspond to the parallelism of the solution of the differential equation itself. FIG. 2 is a block diagram of an element processor that realizes the flow of data processing with a data flow graph based on the wiring logic.

<Second Embodiment> A second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing an element processor constituting an information processing apparatus according to the second embodiment of the present invention. 2, in the processing unit 5, for example, the respective arithmetic units 14 are arranged along the data flow graph 13 according to the wiring logic shown in FIG. 5, and are connected by the data lines 15. FIG. 5 is a data flow graph showing the flow of basic processing. In the figure, reference numeral 16 denotes an operation node, which performs a predetermined operation on the data input along the arc 17 and outputs the operation result to the next operation node along the arc 17.

The arithmetic unit 14 has a function of executing, for example, four arithmetic operations, a logical operation, a memory read / write instruction, an absolute value, and an exponential operation.

The token (node address or message for calling calculation start) sent from the host computer 1 via the network 4 is further processed via the in-processor data bus 9 to the processing unit 5.
Upon entering, the processor element 3a first detects the data memory 8,
For example, DRAM (Dynamic Randum Access Memory), S
By accessing a RAM, a flash memory, or the like, and sucking up the stored state quantity of its own processing unit 5 and the state quantity of the adjacent processing unit 5, the necessary data is prepared. Each data is arithmetic unit 1
The columns of 4 are sequentially processed from the upper part of the data flow graph 13 to be subjected to arithmetic processing one after another, and reach the final arithmetic unit 14 automatically.

Each data is sequentially processed from the upper part of the data flow graph 13 through the column of the arithmetic unit 14, and when a series of arithmetic operations that automatically reach the final arithmetic unit 14 are completed, the processing unit 5 calculates. At the same time as writing the result to the data memory 8 via the in-processor data bus 9, the result is written to the data memory 8 of the adjacent element processor 3a through the inter-element processor connection 7 to complete a series of arithmetic processing. In this case, the processing unit 5 becomes a dedicated computer that executes only the series of processes described in the data flow graph 13, and a high arithmetic processing speed can be obtained.

<Third Embodiment> Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows the third aspect of the present invention.
It is a block diagram showing an element processor which constitutes an information processor by an embodiment. By placing a rewritable program memory in each element processor,
The function as a dedicated computer can be made flexible. The processing unit 5 shown in FIG. 3 includes a floating point arithmetic unit 10 and a program memory 11 instead of the arrangement of the arithmetic units 14 according to the data flow graph 13. The calculation is performed by further loading a program sent from the host computer 1 via the network 4 into the program memory 11 of each element processor 3b via the inter-element processor connection 7.

The contents of the program memory 11 can be rewritten, and the program can be changed by loading a new program from the host computer to the program memory 11 in the processing unit 5 via the network 4. Therefore, when changing the algorithm for solving the differential equation or adding a function, it is possible to simply load a new program into the program memory 11.

As described above, even a multiprocessor having a dedicated structure for speeding up operations can have flexible functions such as changing algorithms and adding functions by rewriting the program. According to the processing unit shown in FIG. 3, as compared with the processing unit shown in FIG. 2, the solution algorithm can be freely selected and changed by changing the program, and the application range of the computer is greatly expanded.

When a program memory whose contents can be rewritten is provided in the element processor, the program is changed by rewriting the contents of the program memory to change the algorithm or scheme for solving the differential equation or add a function. It is possible to implement the same with the same hardware. 1 and 3 respectively show the configuration of an information processing device and the configuration of an element processor for loading a new algorithm, scheme or model into the program memory of each element processor in the first embodiment of the present invention. .

In FIG. 3, the contents of the program memory 11 can be rewritten, and the program can be changed by loading a new program from the host computer 1 to the program memory 11 in the processing unit 5 via the network 4. . In each element processor 3b, the floating point arithmetic unit 10 is operated according to the software written in the program memory 11 to perform the arithmetic operation. When a program written by a new algorithm, scheme, or model for the element processors 3b is input from the host computer 1, the program memories 11 on all the element processors 3b are reset, and the programs are connected to the network 4 and the connection between the element processors 7 Is allocated to each element processor 3b via the, the program of the program memory 11 is rewritten, and each element processor 3b is ready to start calculation as soon as it is completed.

As described above, even in the multiprocessor having a dedicated structure for speeding up the operation, the model, algorithm,
The scheme can be reconfigured and flexible functions can be provided.

If a data memory whose contents can be rewritten by a command from the host computer is provided in the element processor, boundary conditions are changed by rewriting the contents of the data memory, and various analysis model calculations can be performed by the same hardware. Can be achieved with.

Each element processor 3 of FIG.
Has a hardware circuit in the form of a data flow graph 13 connected by a data line 15 or the floating point arithmetic unit 10 according to software written in the program memory 11.
Can be operated to perform the calculation. Further, the host computer 1 is equipped with an initial condition setting program, and the boundary condition can be freely set by this setting program. When the calculation boundary conditions are input to the host computer 1, the initial condition setting program is started, the data memories 8 on all the element processors are reset, and the calculation initial conditions and boundary conditions are set to the network 4 and the connection between the element processors. 7 is assigned to each element processor 3 via 7, and upon completion, each element processor 3 enters a waiting state for starting calculation.

Therefore, by using the information processing device 2 having the same multiprocessor configuration, calculations for various boundary conditions and initial conditions can be realized by a simple procedure of inputting conditions to the host computer.

<Fourth Embodiment> Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 4 shows the fourth aspect of the present invention.
It is a block diagram showing an element processor which constitutes an information processor by an embodiment. The processing unit 5 shown in FIG. 4 has a combined function of the configurations of the processing units shown in FIGS.
In the processing unit 5 shown in FIG. 1, the arithmetic processing function that frequently appears in the solution of the differential equation is the functional module 12
It is configured as a hardware circuit. When performing the calculation, a command for calling the functional module 12 is described in the program, and the functional module 12 is called and made to function as necessary. Therefore, as compared with the case where the software functions the floating-point arithmetic unit 10 for all the arithmetic processing as in the processing unit shown in FIG. 3, the calculation time during that time can be significantly reduced.

Each element processor 3c having the above function
Are connected to the adjacent element processors 3c in a grid pattern by the inter-element processor connection 7 for data communication, and the data communication between the adjacent element processors 3c is performed via this inter-element processor connection 7. Also,
A network 4 is provided between all the element processors 3c or peripheral element processors 3c and the host computer 1 to communicate the convergence determination flag or the calculation result.

<Fifth Embodiment> Next, a fifth embodiment of the present invention will be described with reference to FIG. It is also possible to expand to three-dimensional calculation by connecting three-dimensionally a two-dimensional calculation board composed of the element processors 3 arranged on the two-dimensional plane described in the first embodiment. FIG. 6 is a diagram showing a configuration of an element processor for performing three-dimensional calculation by connecting two-dimensional calculation boards in three dimensions.

In the figure, 1 is a host computer and 3
Is a three-dimensionally arranged element processor, 5 is a processing unit provided in the element processor 3, 6 is a memory section provided in the element processor 3, 4 is a network, 18 is a two-dimensional element processor 3 It is a two-dimensional calculation board configured by connecting to. In this case, unlike the case where the two-dimensional calculation board 18 is pipelined in the time direction,
The network 4 provided between the dimensional calculation boards 18 is used for exchanging data for spatial integration. Further, the connection state of the element processors 3 with each other in a three-dimensional array can be freely changed to a lattice type topology, a hypercube, a pipeline or the like by changing the wiring of the network 4.

In the above embodiment, the case where the element processors 3 are connected to each other in the form of a near neighbor mesh arranged in a lattice has been described. The same effect can be obtained even in the case of the coupling method.

<Sixth Embodiment> Next, a sixth embodiment of the present invention will be described with reference to the drawings. A method of using the information processing device 2 having the configuration according to the above-described embodiment will be described. 1 and 6 show an information processing apparatus having a multiprocessor structure for sending initial conditions and boundary conditions to each element processor 3 according to the first embodiment of the present invention.

In each of the element processors 3 of the information processing device 2, as shown in FIG.
A floating point arithmetic unit 10 is operated according to the software written in the program memory 11 as shown in FIG. 3 and FIG. It is configured to be implemented. When the initial conditions for calculation and boundary conditions for the element processors 3 are input in the host computer 1, the data memories 8 on all the element processors 3 are reset, and the initial conditions for calculation and boundary conditions are the network 4 and the connection between the element processors. 7 is assigned to each element processor 3 via 7, and upon completion, each element processor 3 enters a waiting state for starting calculation.

Therefore, in the information processing apparatus 2, using the same multiprocessor configuration, operations for various boundary conditions and initial conditions can be realized by a simple procedure of inputting conditions to the host computer.

As a usage example of the information processing apparatus 2, a fluid numerical analysis based on the area division method will be described. A fluid that is a continuum is generally described by a continuous equation and an equation with strong nonlinearity called Navier-Stokes equation. When solving the field governing equation described by these partial differential equations by the finite difference method, first, the target phenomenon and region are divided into minute elements (lattices) having a finite size spatially and temporally. A solution is obtained by discretizing the governing equation represented by a partial differential equation on this lattice, transforming it into a difference equation, and solving the difference equation. In the difference decomposition method, the state quantity of a minute spatial element is affected only by the state quantity of an element in the immediate vicinity, but this effect is realized by calculating the state quantity of an adjacent element in the calculation. It That is,
Small elements that are spatially separated do not affect each other, and only consider the effects of adjacent minute elements.
It turns out that it can be calculated independently.

For example, SIMPLE (Se
mi-Implicit Method for Pressure-Linked Equatiens)
Method (a method of solving the equation of motion under an assumed pressure and finally obtaining a solution that satisfies the continuity law while correcting the pressure and velocity by the amount that does not satisfy the continuity, for example, SVPatankar, Numer
ical Heat Transfer and Fluid Flow, (1980), McGRAW-HI
It is described in LL BOOK COMPANY. ) To solve.

FIG. 70 shows a conventional SIMP.
It is a flow chart which shows a calculation procedure of fluid numerical analysis by LE method. In the figure, 211 is a group of routines for solving Navier-Stokes equations of motion, 212 is a group of routines for solving pressure correction equations, 213 is a routine for correcting velocity / pressure, 214 is an iterative cycle for nonlinear convergence,
Reference numeral 15 represents a calculation cycle for time progress. That is, the procedure of thermofluid analysis by the SIMPLE method is as follows: Solving the discretized Navier-Stokes equation of motion by the routine group 211, solving the pressure correction equation by the routine group 212, and solving the velocity / pressure determining equation by the routine 213. Is sequentially performed, and the calculation cycle 215 for time progress is repeated to obtain a numerical analysis solution.

In the parallel solution method using a multiprocessor which has been actively used recently, the entire calculation space is divided into a plurality of areas, and element processors are allocated to each area,
The area division method, in which only the state quantity at the boundary is communicated between element processors, is the mainstream method.

The problem here is the synchronization waiting for communication between the element processors 3. In the current general-purpose parallel processors, data communication between processors is realized by low-speed remote memory access such as packet communication.Therefore, use a large-scale calculation algorithm that minimizes the amount of communication with the number of element processors. , It is necessary to have a technique to avoid waiting for communication synchronization as much as possible. However, when the element processors are configured in a massively parallel fashion, a sharp increase in synchronization waiting is unavoidable, and parallelism proportional to the number of processors cannot be expected.

Therefore, even if both the motion equation and the pressure correction equation are solved only by referring to the state quantities of the adjacent grid points, the solution has sufficient accuracy, and each grid point is uniquely identified. New S to calculate state quantity
The IMPLE method will be described. FIG. 7 shows an arithmetic algorithm in which the lattice points = 1, = 2, ..., = n in this embodiment independently calculate the state quantity without interrupting other lattice point calculations. It is a flowchart.

In the figure, 20 is a routine group for solving the Navier-Stokes equation of motion, 21 is a routine group for solving a pressure correction equation, 22 is a routine for correcting velocity / pressure,
23 is an iterative cycle for convergence of nonlinearity, 24 is a calculation cycle for time progression, 25 is a grid point = 1, = 2
..., = A group of routines of the element processor 3 assigned for each n.

Here, a specific algorithm will be shown by taking the numerical analysis of fluid of incompressible two-dimensional laminar flow as an example. Without considering the temperature field, the fluid is described by the following three dimensionless equations.

The continuous equation is shown in equation 1, and the momentum conservation equation is shown in equations 2 and 3.

[0096]

[Equation 1]

[0097]

[Equation 2]

[0098]

[Equation 3]

Here, in each symbol, u is a velocity component in the x direction, v
Is the velocity component in the y direction, p is the pressure, and Re is the Reynolds number. The numbers 1 to 3 can be uniquely expressed by the number 4. Here, φ is an arbitrary variable, Γ is a diffusion term, and Su and Sp are generation terms, and take the values shown in Table 1 below.

[0100]

[Equation 4]

[0101]

[Table 1]

FIG. 8 shows the control volume required when the equation 4 is differentiated. An arbitrary variable φ is placed at the center point P27 of the control volume 26, and the adjacent positions of φ are E (East) 28, W (west) 29, N.
(North) 30 and S (South) 31 are defined, and their center points (intersection points of the boundaries of the control volume 26 and the grid lines) are displayed in lower case (e, w, n, s). Since it is a staggered grid, the scalar quantity is placed in the uppercase position, and the vector quantity (velocity) is placed in the lowercase position. By the way, using Equation 4 as a time difference scheme, Euler exponential
icit method is applied and discretized considering the flow velocity entering and exiting the control volume 26, the result is as shown in Formula 5.

[0103]

[Equation 5]

Φ is linearly distributed between the lattices, and e, w,
Assuming that n and s are the midpoints of P and E, P and W, P and N, and P and S, the following equations 6 to 9 can be assumed.

[0105]

[Equation 6]

[0106]

[Equation 7]

[0107]

[Equation 8]

[0108]

[Equation 9]

Integrating equation 5 over the control volume yields equation 10.

[0110]

[Equation 10]

Here, with respect to the convection term C and the diffusion term D,
It is defined as 1 and Equation 12. Here, the subscript indicates the position of the boundary surface of the control volume 26.

[0112]

[Equation 11]

[0113]

[Equation 12]

Using the definitions of the equations 11 and 12, the equation 10
Is like Equation 13.

[0115]

[Equation 13]

Applying the hybrid scheme as the spatial difference scheme to this equation 13 and rearranging with respect to φ,
It becomes like the number 14.

[0117]

[Equation 14]

Although various methods such as an explicit method, an implicit method, and a semi-implicit method can be considered as the time difference method, the goal here is to finally obtain a stationary solution, and the convergence acceleration calculation technique is included in the right side of Equation 13. If φ _p is evaluated by the next time value φ _p ^{n + 1} , the discretization equation of Equation 15 can be obtained from Equation 14.

[0119]

[Equation 15]

The velocity and pressure, which are unknown values of the discretized equation derived by the SIMPLE method, are related. First, the discretized equations of the equations of motion 2 and 3 are derived. The variables φ are u and v, and when the equations 16 to 19 are defined for the velocity u, the discretization equation becomes as shown in the equation 20, and the velocity v
When the equations (21) to (24) are defined for, the discretization equation becomes as shown in equation (25).

Equation 16 shows the coefficient of the w plane for the velocity u.

[0122]

[Equation 16]

Equation 17 shows the coefficient of the e-plane for the velocity u.

[0124]

[Equation 17]

Equation 18 shows the coefficient of the s-plane for the velocity u.

[0126]

[Equation 18]

Equation 19 shows the coefficient of the n-plane for the velocity u.

[0128]

[Formula 19]

[0129]

[Equation 20]

Equation 21 shows the coefficient of the w plane for the velocity v.

[0131]

[Equation 21]

Equation 22 shows the coefficient of the e-plane for the velocity v.

[0133]

[Equation 22]

Equation 23 shows the coefficient of the s-plane for the velocity v.

[0135]

[Equation 23]

Equation 24 shows the coefficient of the n-plane for the velocity v.

[0137]

[Equation 24]

[0138]

[Equation 25]

By solving the equation 20, the assumed flow velocity u ^* at the point P can be obtained. By solving the equation 25, the assumed flow velocity v ^* at the point P can be obtained. Number 2
The coefficient of the pressure correction equation is determined by using the assumed values u ^* , v ^* obtained from Equation 0 and Equation 25 and F _p necessary for deriving the equation, and the pressure correction value p ′ is obtained. Equation 26 shows a pressure correction equation. However, the subscripts e and n in the formula are respectively on the East side,
Indicates that the value has been transferred from the element processor on the North side.

[0140]

[Equation 26]

Speed and pressure are on the West side and South
Pressure correction value p ′ transferred from the element processor on the side
Is calculated by the equations 27 to 29.

[0142]

[Equation 27]

[0143]

[Equation 28]

[0144]

[Equation 29]

Various types of calculation grid points are generally considered, such as discrete points inside the object, near the wall, and inflow / outflow points. Calculation program (software) or arithmetic circuit (hardware)
Providing many types according to the types of points makes programming very complicated. Therefore, the position information of each point is given in the form of inner and outer point bits and boundary condition bits as an initial condition on the memory of each element processor, so that the calculation itself can execute exactly the same program.

A bit is also used to distinguish between the inside point and the outside point of the calculation area. When the discretized point is inside the object, it is defined as the outer point, and when it is located in the fluid part, the inner point is defined. The interior and exterior points bits are defined for each of the variables u, v, p, and the interior point is 1 (o
n), and the outer point is 0 (off). For example, if the flag for u is bit (u), the following arithmetic processing is performed before determining the coefficient of the discretization equation of u.

[0147]

[Equation 30]

Regarding the boundary conditions, the following types of boundary conditions can be set. Each of the variables u, v, and p has a flag indicating whether or not to use a wall function. However, a bit is set for each direction of w, e, s, and n in order to determine which surface the wall surface is on. Before determining the coefficients of the discretization equations of u and v, the arithmetic processing of Expressions 31 to 33 is performed.

Wall Function (Wall Functio
The wall surface condition using n) is shown in Equation 31.

[0150]

[Equation 31]

The outflow condition with a gradient of 0 is shown in equation 32.

[0152]

[Equation 32]

The boundary value fixing is shown in equation 33.

[0154]

[Expression 33]

By combining the equations 32 and 33, the variable φ _p is the equation 3
It can be described as 4.

[0156]

[Equation 34]

Focusing on the necessary calculation in each calculation cell, almost the same calculation is performed due to the characteristics of the governing equations of the fluid, although the boundary conditions are different. According to the above boundary condition setting, if the boundary conditions are initially mapped on the data memory 8 by setting various bits,
The same program can be used regardless of whether the calculation cell is located at the boundary of calculation space, inside point, or outside point. Therefore, 1 is stored in the program memory 11 of the element processor 3.
All you have to do is load a program that describes the sequence of operations required to calculate the physical quantity of the grid points. In order to perform the calculation by sequentially sweeping the calculation grid using the one type of calculation program, first, the grid type number of the calculation grid (or the base address in the data memory 8) is used as an input token to make the cyclic type in the element processor 3. Pipeline (8 in FIG. 21)
4) If the lattice point number which is the input token, for example, is 2, the arithmetic unit accesses the memory area allocated to the second lattice point and starts calculation. Since there is no order restriction on the input of tokens, it is possible to input the lattice numbers randomly as well as to sequentially proceed with the calculation such as 1, 2, 3 ...

FIG. 9 is a diagram showing the data structure inside the data memory provided in the element processor. As shown in the figure, the inside of the data memory 8 provided in the element processor 3 is divided into the same number of partitions 32 as the number of grid points handled by one processor, and each partition 32 is required to calculate one grid point. The following data is mapped.

FIGS. 10 and 11 are flowcharts showing the flow of the algorithm described above. In the figure, reference numerals 33 to 63 denote respective calculation functions of A to I shown below.

(A) The element processor 3 has a function of solving the x-direction equation of motion to obtain the predicted value u ^* . In the figure, 33 is a calculation for the w plane of u, a function A (u) for obtaining the coefficient F _w of the equation of motion in the x direction, and 34 is a calculation for the e plane of u, a function for obtaining the coefficient F _e of the equation of motion for the x direction. B (u), 35 is a calculation of u on the s plane, and the function C (u), 36 for obtaining the coefficient F _s of the equation of motion in the x direction is u
Is a function D (u) for obtaining the coefficient F _n of the x-direction equation of motion, 37 is a function E (u) for obtaining the generating term G of the x-direction equation of motion, and 43 is a coefficient F of the x-direction equation of motion. _This is a function G (u) that obtains _p and obtains a predicted value u ^* from various coefficients and the generated term.

(B) The element processor 3 has a function of solving the equation of motion in the y direction to obtain the predicted value v ^* . In the figure, reference numeral 38 denotes a calculation of v on the w plane, which is a function A (v) for obtaining the coefficient F _w of the y-direction motion equation, and 39 is calculation for v on the e surface, which is a function of obtaining the coefficient F _e of the y-direction motion equation. B (v), 40 is a calculation of v on the s-plane, and a function C (v) for obtaining a coefficient F _s of the equation of motion in the y-direction is denoted by C (v), 41 is a calculation of v on the n-plane, and a coefficient F _n of the equation of motion of the y-direction is calculated. The function D (v), 42 to be obtained is the generation term G of the equation of motion in the y direction.
The seek function E (v), 44 obtains a coefficient F _p in the y direction the equation of motion is a function determining the more product terms with various coefficient prediction value v ^* G (v).

(C) The element processor 3 uses the pressure correction value p
It has the function of seeking ´. In the figure, 51 is a function F for finding the generating term G of the p ′ equation, and 52 is a solution of the equation p ′ based on the coefficient of the equation of motion and the generating term found by F to solve p ′.
Is a function G (p) for obtaining

(D) The element processor 3 has a function of correcting the flow velocity and the pressure. In the figure, 55 is a function H for obtaining u, v, p based on p '.

(E) The element processor 3 has a function of setting boundary conditions. In the figure, 45, 46, 57-
Reference numeral 59 is a function I for setting the boundary condition based on the bit data given by the initial value.

(F) The element processor 3 has a function of transferring the set boundary condition. In the figure, 47, 4
Reference numerals 8, 53, 56, and 60 to 62 each have a function of transferring the boundary condition set in the previous step to the adjacent element processor 3.

(G) The element processor 3 has a function of determining whether or not the calculated boundary condition has converged. Four
9, 50, 54, 63 are the previous functions I45,
This is a function of determining whether or not the boundary conditions set by 46 and 57 to 59 have converged.

By connecting these functions according to the flow charts shown in FIGS. 10 and 11, the calculation code for one grid point is completed.

Next, the algorithm for calculating one grid point is mapped on the program memory 11 of the element processor 3. The mapped program is activated by using the lattice point number information tag sent from the host computer 1 via the network 4 and the inter-element processor connection 7 as an input token. When a plurality of lattice points are mapped on one element processor 3, the data transferred between the element processors 3 via the inter-element processor connection 7 is the outermost portion of each divided area formed by the plurality of lattice points. This is the information held by the grid point located at. Therefore, data is transferred between processors by directly accessing the data memory on the adjacent element processors via the inter-element processor connection 7 arranged between the element processors 3, and the data transfer overhead between lattice points can be eliminated and asynchronous. High-speed analysis by control becomes possible.

Further, one grid point is mapped on one element processor, at least as many element processors 3 as the number of calculation grid points are used, and a multiport memory described later is arranged between the element processors 3 and these elements are arranged as elements. A massively parallel system connected by the inter-processor connection 7 is constructed, and data is exchanged without obstructing the processing of the mutual element processors 3 while asynchronously performing dense data communication between the adjacent element processors 3 to obtain a converged solution. It is also possible.

Further, by mapping a plurality of grid points on one element processor 3 and setting the communication method between the element processors to be a synchronous method, it is possible to perform an analysis with the element processors 3 synchronized. Also in this case, since the processing unit 5 inside the element processor 3 has a dedicated high-speed arithmetic function suitable for solving partial differential equations, it is possible to significantly improve the processing speed as compared with the conventional synchronous solving method using a general-purpose processor. Become.

In the above-described embodiment, the element processor 3 uses an algorithm for calculating one grid point.
However, it is needless to say that the same effect can be obtained even if the arithmetic unit 14 is connected by the data line 15 to form a hardware circuit in the form of the data flow graph 13.

Communication between adjacent element processors is a message communication in which a message (data) is sent from one process to another process by the address code of the message and the message is sent to an appropriate process. On the other hand, by executing a plurality of different (may be the same) instructions in parallel, efficient parallel processing becomes possible.

<Seventh Embodiment> Next, a seventh embodiment of the present invention will be described. Due to the difference in the time step of the state quantity to be referred to the approximation method of time differentiation, the Euler forward method,
Euler backward method, second-precision crank = Nicholson method,
There is a Richardson method with third-order accuracy. For example, considering the third-order Richardson method, when the current time is n, the state quantity required to obtain the value at the next time n + 1 is determined by the values at the times n-1 and n. In the conventional method using the Neumann type computer, time n−1, n
Since it was necessary to store the extra value in common memory, the calculation scale was limited due to insufficient memory capacity.

Such a memory shortage problem can be easily solved by using a plurality of two-dimensional calculation boards composed of the element processors 3 arranged on the two-dimensional plane described in the first embodiment. . FIG. 12 is a diagram showing a configuration of an information processing apparatus for approximating a time derivative in a two-dimensional space. In the figure, reference numerals 65 to 67 each denote a two-dimensional calculation board configured by connecting the element processors 3 in a two-dimensional manner, and 65 denotes a two-dimensional calculation board that is in charge of calculation of a value corresponding to time n-1. Is a two-dimensional calculation board in charge of calculation of a value corresponding to time n, and 67 is a two-dimensional calculation board in charge of calculation of a value corresponding to time n + 1. Also, 4
Is a network for connecting the two-dimensional calculation boards in a pipeline and connecting with the host computer 1 to exchange information.

For example, in the case of Richardson's method, time n
The values of time n-1 and n required to obtain the value of +1 are calculated from the data memory of each element processor 3 on the time n-1 two-dimensional calculation board 65 and the time n two-dimensional calculation board 66.
It is transferred to each element processor 3 on the two-dimensional calculation board 67 for time n + 1 via the network 4. When the calculation is completed, the calculation result is automatically saved in the data memory of each element processor 3 on the two-dimensional calculation board 67. Then, in order to calculate the value of n + 2, the data memory of each element processor 3 on the two-dimensional calculation board 65 for time n-1 in which the value of time n-1 is stored is reset, and the value for time n is newly added. Two-dimensional calculation board 66 and two-dimensional calculation board 6 for time n + 1
7 from the values at time n and n + 1, respectively.
The data is transferred to the two-dimensional calculation board 65 for time n−1 via the to perform calculation, and is stored in the data memory of each element processor 3 as the value at time n + 2.

As described above, according to the information processing apparatus of the third embodiment, it is possible to solve the memory shortage and to perform the calculation at high speed.

This pipeline along the time axis is 2
In the solution of a differential equation, which contributes to speeding up the convergence determination of the dimensional analysis solution, the calculated value at the current time n and the previous time n
When the difference from the calculated value of -1 reaches a certain reference range or less, it is determined that the convergence has occurred. However, if the time direction is pipelined, the values between adjacent two-dimensional calculation boards are compared. It is possible to judge the convergence by a simple operation.

<Eighth Embodiment> Next, an eighth embodiment of the invention will be described. The main application of the present invention is the solution of differential equations, but this kind of problem ends by iteratively calculating the interaction between adjacent grid points and converging all grid points to a stable state. That is, the data exchange between the non-adjacent grid points hardly occurs, and the data exchange between the adjacent grid points is exclusively required. In addition, generally, after dividing the target system into grid points, one element processor 3 is caused to share the operation related to one or a plurality of adjacent grid points, and further the grid points adjacent to these grid points. The calculation related to is also shared by the adjacent element processors 3.

Focusing on such a feature of the problem to be addressed, the efficiency of calculation can be improved by sharing the same memory between the adjacent element processors 3 and directly accessing each other's memories. Can be significantly improved, and the desired calculation can be completed in a short time.

FIG. 13 shows a part of a multiprocessor in which the element processors 3 are connected by an inter-element processor connection 7 and arranged in a square lattice. 14 is a diagram showing the internal configuration of one of the element processors shown in FIG. In the figure, the processing unit 5 is connected to a data memory 8 incorporated in the same processor, and the data memory 8 can be accessed. Further, the processing unit 5 is connected to an adjacent element processor via an input / output control circuit (hereinafter also referred to as I / O) 71.

Adjacent element processor 3d via I / O 71
By connecting with, the data memory 8 in the adjacent element processor 3d can be directly accessed as if it were a memory in the same element processor.
On the contrary, the data memory 8 shown in the figure can be similarly accessed from the adjacent element processors.

In order to mutually access the memories between the adjacent element processors, the I / O 71 in the figure sends data to the data bus 73 between the processing unit 5 and the data memory 8 from the adjacent element processors. It must fulfill the function of arbitration for memory access requests. However, arbitration with respect to the data bus is a technique used in a general processor, and can be realized by using a VME bus, for example, and is well known, so description thereof will be omitted here.

As described above, in the element processor shown in FIG. 14, the processing unit 5 is connected to the data memory 8 incorporated in the same processor so that the processing unit 5 can access the data memory 8. Furthermore, since the processing unit 5 is connected to the adjacent element processors 3d via the I / O 71, the overhead for data communication between the element processors 3d can be reduced and the efficiency of calculation can be improved.

Although the general case has been described in the above description of the configuration of the element processor, if it is limited to the solution of the differential equation, the data at the adjacent grid points may be referred (that is, read out) and updated. (Ie,
Writing) is not required. It is apparent that if only reference is made, update requests for the same memory address do not collide, and arbitration of the data bus for memory access is simplified.

<Embodiment 9> However, it is expected that a plurality of memory reference requests for the same memory will occur at a high frequency. In this case, there is a concern that processing will be stagnated in the single-port memory, resulting in a long calculation time. In order to avoid such a problem in advance, a multiport memory may be adopted so that a plurality of memory references can be processed at the same time.

A ninth embodiment of the present invention for that purpose will be described. FIG. 15 shows a case where a memory is shared with six adjacent element processors. In the figure,
Reference numeral 3 is an element processor, and 7 is a network.

FIG. 16 shows the internal structure of one element processor, and the data memory 8 has seven ports. The data memory 8 is connected to the data memory 6 via the data bus 75.
The individual input / output control units 71 and the processing unit 5 are connected. With such a configuration, it is possible to simultaneously process memory reference requests from the element processor and six adjacent element processors.

If only reference is made, it can be realized by a relatively simple control circuit. However, when the information processing device is used for general purpose, the adjacent element processors 3
It may be required that the memory of e also has a writing function. By adopting such a configuration, the same data is stored in the data memory 8 of the element processor 3e.
At the same time that the data is written in, the data can be written in parallel to the data memory 8 of the adjacent element processor 3e, which greatly contributes to the reduction of the calculation time in the processing in which the references to the same memory address collide.

<Embodiment 10> Furthermore, the shared memory unit does not necessarily have to be provided in the element processor. Therefore, a tenth embodiment of the present invention in which the memory section is devised will be described with reference to the drawings. FIG. 17 shows the configuration of an information processing apparatus in which the shared memory unit is arranged outside the element processor. Further, FIG. 18 shows the configuration of the element processors forming the information processing apparatus shown in FIG. 17 and the connection relationship with the memory section. In the figure, reference numeral 76 is a memory provided outside the element processor 3f, 5 is a processing unit connected to the external memory 76 by the input control unit 71, and 8 is provided inside the element processor 3f and directly connected to the processing unit 5. The data memory is connected to the processing unit in the element processor 3 via the input / output control unit 71. That is, as shown in FIG. 17, the memory 76 is arranged on the data path between the element processors. By arranging in this way, the four memories 76 shared with the adjacent element processors 3f can be directly referenced and updated via the input / output control unit 71 shown in FIG.

The following method is an example of a method of exchanging data between the adjacent element processors 3f via the memory 76.

That is, an address or an address range when each element processor 3f performs writing is set in advance, and the element processor on the data output side is the memory 7
Data is written in a predetermined address area 6 and the element processor 3f on the data receiving side reads the above-mentioned address area to complete the data transfer between the element processors 3f.

In FIG. 17, the symbol "P" described in the memory 76 indicates the address range to be written by the element processor 3, and the symbols "S", "N", "E", "W".
Indicates an address range to which each adjacent element processor 3f should write.

In the present embodiment, the element processor 3
Although the example in which the data memory 8 is included in f has been described, if the data to be stored in the data memory 8 is stored in the memory 76 connected between the element processors, the element processor does not have the data memory 8. It is obvious that the same effect can be obtained.

In the above description, the case where a single port memory is used as the memory 76 has been described. However, like the case where the data memory 8 described in FIG. 16 is built in the element processor 3f, it is arranged on the data path. Even in the case of the memory 76, the calculation time can be shortened by using the multiport memory.

However, even when the multi-port memory is adopted, if update requests for the same memory address collide, the processing is interrupted and the calculation time is increased. In order to avoid this, it is effective to introduce a buffer mechanism for temporarily storing the reference / update request to the memory. FIG. 19 shows a multi-port memory in which a buffer mechanism for this purpose is introduced, and only the portion corresponding to the memory 76 in the information processing apparatus of FIG. 17 is shown.

In the figure, 76a is a multi-port memory with a buffer mechanism, 79 is a 2-port memory, and 80 is a buffer mechanism. The buffer mechanism 80 can temporarily store the data input from the two-port memory 79 via the inter-element processor connection 7 or the data to be written to the two-port memory 79.

As described above, the adjacent element processors 3
Since the buffer mechanism 80 is arranged at each port of the 2-port memory 79 arranged between f, the processing will not be interrupted even when the update requests for the same memory address collide. In addition, it is possible to avoid an increase in calculation time that occurs as a result.

In the multiport memory shown in FIG. 19,
Although the example in which the buffer mechanism 80 is arranged at each port of the 2-port memory 79 has been described, the buffer mechanism may be provided for each port of the multiport, or one buffer may be provided for a plurality of ports or all ports. It is clear that the provision of the effect is effective.

<Embodiment 11> Next, the first embodiment of the present invention
One embodiment will be described. By providing a buffer memory for holding communication data for each element processor, it is possible to prevent the operation of each element processor from being interrupted by data communication between the element processors.

FIG. 20 is a block diagram showing the structure of an element processor having a buffer memory for holding communication data. In the figure, 5 is a processing unit provided in the element processor 3g, and 7 is an element processor 3g.
A data bus between the element processors connecting between the two, a buffer memory 82 provided in the element processor 3g and connected to the data bus 7 between the element processors and the processing unit 5, and a reference numeral 8 connected to the processing unit 5 provided in the element processor 3 It is a data memory that has been stored.

Each element processor 3g writes the data sent from the adjacent element processor 3g to the buffer memory 82 via the inter-element processor data bus 7 as data with an object name, and each element processor 3g reads from this buffer memory 82. The adjacent element processor 3 is searched for data with an object name at an arbitrary timing.
Complete data acceptance from g. According to the information processing apparatus formed of the element processors having the configuration shown in FIG. 20, the data communication between the adjacent element processors 3g prevents the processing unit 5 in each element processor 3g, for example, the operation of the floating point arithmetic unit. Without
Higher speed processing is possible.

<Embodiment 12> Next, the first embodiment of the present invention
Two embodiments will be described. FIG. 21 is a block diagram showing an example of the configuration of the element processor of the information processing apparatus according to the twelfth embodiment of the present invention.

In the figure, 3h is an element processor, 10
Is a floating-point arithmetic unit provided in the element processor 3h, 83 is a matching memory (data pool) provided in the element processor 3h, and 11 is the element processor 3h.
8 is a data memory provided in the element processor 3h, and 84 is a floating point arithmetic unit 10, a matching memory 83, and a program memory 1.
1 is a pipeline for connecting the data memory 8 and exchanging information, and 7 is an inter-element processor connection for connecting the element processors 3 and exchanging information.

Between the adjacent element processors 3h,
There is a wide variety of data that needs to be exchanged by communication.
In this embodiment, each data is given an object name which can identify what kind of processing is to be performed next. The data to which the object name is attached is input in the form of a data packet in a pipeline 84 provided with a matching memory (data pool) 83 and circulates, and further, in the adjacent element processors 3h via the inter-element processor connection 7. Are sent to the matching memory 83. The floating-point arithmetic unit 10 searches the inside of the matching memory 83 at an arbitrary timing, and starts the arithmetic operation as soon as the data with the object name necessary for performing an arbitrary process are prepared.

At this time, since the degree of parallelism of the program of the partial differential equation tends to temporarily increase in time series, it is necessary to secure a sufficient storage capacity of the matching memory 83.

In the above description, the element processor 3
The case where the processing unit of h is composed of the floating point arithmetic unit 10 has been described, but the arithmetic unit 14 shown in FIG.
Even in the case where the circuit is structured like three hardware, FIG.
The same effect can be obtained even if the floating point arithmetic unit 10 is operated in accordance with the instructions of the program memory 11 except that the frequently appearing portion during the operation is circuitized in the functional module 12 as shown in FIG.

As described above, by automatically synchronizing the data, it is possible to perform processing at higher speed and with less communication overhead.

<Embodiment 13> Next, the first embodiment of the present invention
The third embodiment will be described. As I mentioned earlier,
In the solution of the Navier-Stokes equation by the SIMPLE method, the first input and the second input, the third input and the fourth input, the fifth input and the sixth input, and the seventh input are applied to eight inputs.
An operation for cumulatively adding the multiplication results of the input and the eighth input frequently appears, and speeding up this processing is one of the decisive factors for reducing the calculation time. FIG. 5 is a flow graph that graphically represents the operation of Expression 35.

[0209]

[Equation 35]

FIG. 22 shows a hardware implementation of this processing. In the figure, reference numeral 85 denotes a multiplier, which executes multiplication of two data input from the input end and outputs the result to the output end. Reference numerals 86 and 87 denote adders, which execute addition of two data input from the input end and output the data to the output end. The output end of the multiplier 85 and the input end of the adder 86 are connected by a data line 88. The output end of the adder 86 and the input end of the adder 87 are connected by a data line 89. By connecting the adder and the multiplier with the above configuration, the operation shown in FIG. 5 is executed on the data input to each input terminal of the multiplier, and the result is output to the output terminal of the adder 87. Is output.

As described above, the element processor having the so-called macro function block, in which the arithmetic units are connected by the data lines, greatly contributes to the speeding up of the solution of differential equations such as the solution of the Navier-Stokes equation.

<Fourteenth Embodiment> Next, the first embodiment of the present invention will be described.
Four embodiments will be described. FIG. 23 is a block diagram showing a configuration of a communication circuit for realizing data communication between adjacent element processors asynchronously and repeatedly for each element processor.

In the figure, 3i is an element processor, and 70
Is a processing unit which is provided in the element processor 3i and performs arithmetic operation; 8 is a data memory which is provided in the element processor 3i and which stores data required for the processing of the processing unit 70; and 90 is a data memory of the element processor 3. 8 is a data bus for exchanging the information described in 8 between adjacent element processors 3i.

Next, the operation will be described. In the processing in the processing unit 5, when the information of the adjacent element processor 3i is necessary, the element processor 3i
Performs a memory access operation of repeatedly referencing the necessary information described in the partner data memory 8 completely asynchronously with the adjacent element processor 3i. In the solution of the partial differential equation, the calculation performed by each element processor 3i depends only on the information held by the adjacent element processors 3 rather than the information held by the element processors 3i far away from each other, and therefore has extremely high locality. Therefore, it is desirable that the communication between the adjacent element processors 3i be performed completely asynchronously and repeatedly via the data bus 90 without hindering the processing of the processing unit 70.

By configuring the memory access between the element processors 3i adjacent to each other to be performed completely asynchronously without hindering the processing of the adjacent element processors 3i, the communication between the element processors 3i adjacent to each other can be performed. Since the processing is performed completely asynchronously and repeatedly without interfering with the processing of the processing unit 70 via the data bus 90, the arithmetic processing performed on each element processor 3i can be continued completely asynchronously between the adjacent element processors 3i. It will be possible.

In this embodiment, the processing unit 70 and the data memory 8 use the memory-referable data bus 90 without hindering the operation of the other party to perform data communication between the respective element processors 3i. , The adjacent element processor 3i for accessing the data memory 8
When a synchronous operation for interrupting the operation of the processing unit 70 in the internal processor is required, the data communication method between the element processors is a synchronous type, and communication overhead increases, but there is no hindrance in obtaining an analytical solution. .

<Fifteenth Embodiment> Next, the first embodiment of the present invention will be described.
A description will be given of an element processor according to the fifth embodiment for obtaining an output in which data can be easily sorted and classified even if data is asynchronously downloaded. FIG. 24 is a block diagram showing the configuration of an element processor for attaching an identifier to each state quantity in the memory and obtaining an output in which data can be easily sorted and classified even if data is asynchronously sucked.

In the figure, 3i is an element processor, and 70
Is a processing unit which is provided in the element processor 3i and performs an operation, 8 is a data memory which is provided in the element processor 3i for storing calculation data including output data, 90 is an inter-element processor data bus, and 91 is an element processor 3i An I / O unit for assigning an identifier in accordance with the type of state quantity provided inside and outputting the data to the outside of the element processor 3i, and 92 for the I / O unit 9
1 is an output data bus for transferring the data output via 1 to the host computer.

Next, the operation will be described. The calculation result obtained by the series of processes of the processing unit 70 is composed of a plurality of kinds of state quantities, and since the purpose is high-speed calculation, the sampling time interval of the output data becomes very short. Therefore, the output data is I / O
In the unit 91, an identifier that can identify what the state quantity is is added to the beginning or the end of the unit 91. The output data is asynchronously and in large quantities and continuously output to the outside of its own element processor 3i in a packet communication mode in which a plurality of state quantities are mixed, and is sent to the host computer via the I / O unit 91. Post processed.
At this time, since the output data bus 92 is installed for each element processor 3i, the data output via the I / O unit 91 is output asynchronously without disturbing the output of the adjacent element processor 3i. It is transferred to the host computer. Further, since the output data is provided with an identifier capable of determining the state quantity, even if the host computer sends a plurality of output data of a plurality of state quantities in a packet format, they are sorted and classified separately. Post processing can be applied.

Therefore, according to this embodiment, the intermediate result of the non-steady state calculation can be output without disturbing the calculation of the element processor 3i, and the high speed calculation can be achieved.

Of course, the following synchronous output method is also possible. An output command is sent from the host computer to each element processor 3i via the output data bus 92, and the element processor 3i executes the reference function of the data memory 8 provided in the I / O unit 91 according to the received instruction.
The output data of the required state quantity is sucked in the order described in the command, and the output data string is created. The output data string created by the I / O unit is sent to the host computer via the data bus 92. Therefore, by adjusting the timing at which the host computer sends an output command to each element processor 3i, it is possible to output at any time.

Sixteenth Embodiment Next, the first embodiment of the present invention
Six embodiments will be described. FIG. 25 is a configuration diagram of the entire computer system for collecting data output asynchronously from each element processor and performing visualization in real time according to the sixteenth embodiment of the present invention.

In the figure, 3j is an element processor for performing arithmetic operation, and 93 is an output I / O provided in each element processor 3j for performing data conversion when outputting the operation result to the outside.
Unit, 94 is an output I / O on each element processor 3j
An output data bus for transferring the data output via the O unit 93, 95 is at least the same number of parallel data as the element processors 3j transferred from each element processor 3j via the output data bus 94 into serial data. A data output control unit for conversion, 96 is a serial data bus for transferring the data converted into the serial type through the data output control unit, and 97 is data transmitted via the serial data bus 96 for each type. Post processing unit for performing post processing such as classification, gradation inversion, gradation conversion, averaging, color tone correction, contour display, contour line processing, fringe processing, or vector display, 9
Reference numeral 8 is an image output data bus for transferring the image data created by the post-processing unit 97, and 99 is a display for displaying the image data transferred via the image output data bus 98.

Next, the operation will be described. The output data bus 94 is directly connected to the element processors 3j, and external output data of each element processor 3j is asynchronously output I / O.
It is output from the unit 93. The output data is a data string including a plurality of types of state quantities when output from the element processor 3j. In addition, at the time of output, in order to clarify which element processor 3j is the output, an identifier representing the element processor number is attached to the head or tail of the data string to form a packet-like data structure.
This data string is collected in the data output control unit 95 via the output data bus 94, and is converted into one serial data from the parallel data of the number equal to or more than the number of element processors. Further, the data sent to the post processing unit 97 via the serial data bus 96 is sorted according to the element processor number identifier, and further divided according to the state quantity identifier. The arranged data is subjected to post-processing for visualization such as contour line processing, fringe processing, and vector display, and the image output data bus 98
The image is visualized on the display 99 via the. Therefore, according to this embodiment, the intermediate result of the unsteady calculation can be output without hindering the calculation of the element processor 3j, and the high-speed calculation can be achieved.

Of course, the data output asynchronously from the output I / O unit may be output via the post processing unit 97, and the sampling time may be set in the post processing unit 97 to freely control the visualization time interval. Is also possible.

When the output data bus 94 is connected from each element processor 3 to the data output control section 95 as shown in FIG. 25, the wiring becomes complicated, and it becomes difficult to downsize the device or the manufacturing trouble easily occurs. There is a nature.

<Seventeenth Embodiment> A seventeenth embodiment for solving the problem will be described with reference to the drawings. FIG. 26
FIG. 3 is a configuration diagram of the entire computer system for solving the above-mentioned problems by minimizing the output data bus 94. The output data bus 94 is one data bus that connects the all-element processor 3j and the data output control unit 95. Also, 10
Reference numeral 0 is a host computer, 101 is a network connecting the host computer 100 and the output data bus 94. Others are the same as in FIG.

Next, the operation will be described. The output data is a data string including a plurality of types of state quantities. The host computer 100 controls the timing of outputting the output data from each element processor 3j to the output data bus 94. Each element processor 3j sends the output data to the output data bus via the output I / O unit 93 at the timing from the host computer 100. At this time, in order to clarify from which element processor 3j the output is made, an identifier representing the element processor number is attached to the head or tail of the data string to form a packet-like data structure. The data output control unit 95 rearranges the output data input via the output data bus 94 according to the element processor number identifier and converts the output data into one serial data. Further, the data sent to the post processing unit 97 via the serial data bus 96 is classified and arranged according to the state quantity identifier. The organized data is subjected to post-processing for visualization such as contour line processing, fringe processing, and vector display, and becomes a visualized image on the display 99 via the image output data bus 98. Therefore, with the minimum output data bus configuration, it is possible to output the intermediate results of the non-steady state calculation without hindering the operation of the element processor 3j, and it is possible to achieve high-speed operation.

<Embodiment 18> Next, the first embodiment of the present invention
The eight embodiments will be described. In conventional parallel computers, the focus is on speeding up calculations,
When displaying the calculation results of steady-state calculations or chasing changes in the calculation results of non-steady-state calculations, display the results of all element processors until the results of all element processors are complete or other elements are interrupted. Since the calculation of the processor is stopped and made to wait, there is a problem that speeding up the calculation does not lead to the speeding up of the whole. FIG. 27 is a block diagram of an element processor showing an embodiment for speeding up the entire calculation by parallelizing the calculation result display, and FIG. 28 is an overall block diagram of a multiprocessor having the element processor of FIG. 27 as a component. is there.

In the figure, 3s is an element processor, and 70
Is a processing unit formed in the element processor 3s for performing calculation, 8 is a memory unit formed in the element processor 3s and storing calculation information necessary for the calculation of the processing unit 70, 107 is formed in the element processor 3s Then, the calculation information stored in the memory unit 8 in the element processor 3s to which it belongs is received without interrupting the operation of the processing unit 70, and when one calculation lattice point is assigned to one element processor, When a plurality of calculation grids are convoluted in one element processor, an output information processing unit for processing the information of the grid points, 104 is an operation between the memory units 6 in the element processors 3s in the row direction. A row-direction calculation information bus for exchanging data required for data, 105 is a column-direction element processor 3s , A column-direction calculation information bus for exchanging data necessary for calculation between the processing units 70, and 106, an internal calculation information bus for exchanging data necessary for calculation and calculation result data between the processing unit 70 and the memory unit 8. Reference numeral 108 denotes an output processing information bus for transmitting the calculation information stored in the memory unit 8 to the output information processing unit 107. Reference numeral 110 denotes conversion of the calculation information into light transmittance as in a liquid crystal display device, or magnetic field. An element using the Kerr effect that changes the distortion into light reflection, a display element such as a color liquid crystal display element for converting into color change, and if 111 is a light transmissive type, it may be a light reflective type from the back side of the display element 110. For example, a lamp for emitting light from the front side of the display element,
Reference numeral 112 is a reflecting mirror for converting the light of the lamp 111 into parallel rays, and 109 is the output information processing unit 1 of each element processor 3s.
An output processing information bus for transmitting output processing information from 07 to the display element 110.

The memory unit 8 of each element processor 3s stores the calculation information necessary for the calculation of the processing unit 70, and is required for the calculation between the processing unit 70 and the memory unit 8 via the internal calculation information bus 106. Data (input data) and operation result data (output data) are exchanged. Therefore, in order to display the time until the calculation converges or the change in the calculation result of the non-stationary calculation every moment, the calculation of the processing unit 70 is stopped and the memory unit 8 is accessed, or the calculation result after the convergence is displayed. In order to do so, there is no choice but to interfere with the whole calculation by waiting until the calculation of all the element processors 3s converges. In this embodiment, the memory unit 8 is asynchronously connected (the communication information of the memory unit 8 and the processing unit 70 is not disturbed, and the calculation information sent from the memory unit 8 can be received without matching with the memory unit 8). ) Output information processing unit 107
In the case where a plurality of calculation grids are convoluted in the one-element processor, the calculation information provided in the inside of the Is processed by processing the information of its grid points, and it is digital /
Digital data is converted into analog data via the analog conversion circuit and sent to the display element 110 via the output processing information bus 109. The display element 110 converts calculation information into light transmittance, such as a liquid crystal display element, or changes magnetostriction into light transmission (element using Kerr effect),
It is converted into a color change of transmitted light (color liquid crystal display element). At this time, if the display element 110 is a light transmissive type, light from the back side of the display element 110, and if it is a light reflective type, from the front side of the display element, the light from the lamp 111 converted into parallel rays by the reflecting mirror 112. Since the light is emitted, the output processing information can be visually displayed without disturbing the operation of the output information processing unit 107.

As described above, according to this configuration, it is possible to visually observe the progress of the calculation and the final calculation result and use the result for control without disturbing the high-speed processing of the calculation.

<Embodiment 19> Next, the first embodiment of the present invention
9th Embodiment is described. If the output processing information bus 109 is individually wired from each element processor 3s to the display element 110 as shown in FIG. 28, the wiring becomes huge and the distance between the computer system and the display device cannot be increased.
FIG. 29 is a configuration diagram of the entire computer system for solving the above-mentioned problems by using a single serial data bus between the computer system and the display device.

In the figure, 1 is a host computer and 1
Reference numeral 14 is a data output control unit for changing the order of output data sent at random and converting it into serial data. Reference numeral 113 is one output processing information bus connecting all the element processors 3s and the data output control unit 114. Is a network that connects the host computer 1 and the output processing information bus 113; 116 is a display data control unit that decomposes serial data and distributes the display data to each display element 110; 115 is a data output control unit 114 and display data control unit Reference numeral 116 denotes a serial data bus connecting the display data control unit 116 to each display element 110. Others are the same as in FIG.

Next, the operation will be described. The output information processing unit 107 in the element processor 3s keeps the calculation information transmitted from the memory unit as it is when one calculation grid point is assigned to one element processor, and the one element processor has a plurality of calculation grids. If is convoluted, processing is performed on the information of the grid point. The host computer 1 controls the timing of outputting the output processing information from each element processor 3s to the output processing information bus 113. Each element processor 3s sends the output processing information from the output information processing unit 107 to the output processing information bus 113 in synchronization with the timing from the host computer 1. At this time, in order to clarify from which element processor 3s the output is made, an identifier representing the element processor number is attached to the head or tail of the data string to form a packet-like data structure. The data output control unit 114 rearranges the output processing information input via the output processing information bus 113 according to the element processor number identifier and converts it into one serial data. Further, the data sent to the display data control unit 116 via the serial data bus 115 is again displayed according to the element processor number identifier.
After being sorted by 0, digital data is converted into analog data through a digital / analog conversion circuit and sent to each display element 110 through a display data bus 118. The display element 110 converts calculated information into light transmittance, such as a liquid crystal display element, changes magnetostriction into light transmission, and converts color change of transmitted light. At this time, if the display element 110 is a light transmissive type, light from the back side of the display element 110, and if it is a light reflective type, from the surface of the display element, the light from the lamp 111 converted into parallel rays by the reflecting mirror 112. Is output, the output information processing unit 1
The output processing information can be visually displayed without disturbing the operation of 07.

As described above, according to this configuration, the distance between the computer system and the display device can be increased with the minimum data bus configuration, and the progress of the calculation and the final calculation result can be achieved without hindering the high-speed processing of the calculation. Can be visually observed and used for control.

<Embodiment 20> Next, the twentieth embodiment of the present invention will be described.
An embodiment will be described. This embodiment will be described, for example, in fluid analysis. If the calculation target is an external flow, the external surface of the object with a complicated curved surface shape is used. If the internal flow is a flow along an inner wall surface with a complicated curved surface shape, a grid along the surface of the object is used. If the body-fitted coordinate system that is used is a locally complex structure, a complex coordinate system that uses a combination of a coarse grid and a fine grid, or the phenomenon is locally severe. In the case of a change, the accuracy of analysis is improved by using a solution adaptive coordinate system or the like that automatically makes the grid of the part that changes a lot. However, in order to use these coordinate systems, complicated coordinate conversion between the physical coordinate system and the calculation coordinate system must always be performed. In this embodiment,
A coordinate conversion dedicated unit that handles the coordinate conversion function is provided between the physical coordinate space and the calculation coordinate space to facilitate grid generation, increase the calculation speed of fluid analysis, and further shorten the display time of calculation results. FIG. 30 shows an overall configuration diagram of the multiprocessor.

In the figure, 1 is a host computer and 3
Is an element processor, 7 is an inter-element processor connection for connecting the element processors 3 and exchanging information, 18
Is the element processor 3 and the inter-element processor connection 7
A two-dimensional calculation board connected in a two-dimensional plane by means of a network 4 for connecting the host computer 1 and element processors in the two-dimensional calculation board 18 for exchanging information,
Reference numeral 20 denotes a coordinate conversion dedicated unit that is provided in the middle of the network 4 and performs coordinate conversion.

When initial conditions and boundary conditions are loaded from the host computer to the multiprocessor, the coordinates are first converted from the physical coordinate system to the calculation coordinate system in the coordinate conversion unit 120, and only information regarding the calculation coordinate system is input to the multiprocessor. It Therefore, the element processor 3
With this, complicated coordinate transformation calculation is separated, and the original fluid calculation can be speeded up. Also, when outputting the calculation result,
It is necessary to convert the conversion calculation result to a physical coordinate system that is easy to understand visually, but conversion to the physical coordinate system that hinders the calculation in the element processor 3 is performed while being transmitted from the element processor 3 to the host computer 1. Dedicated unit 120
Done by. Therefore, the output time of the calculation result is shortened, and the element processor can maintain high-speed calculation without being disturbed by the calculation result output.

As described above, according to this embodiment, the coordinate conversion required for calculation is facilitated, and the coordinate conversion dedicated unit for preprocessing and postprocessing of the coordinate system is supported by hardware or software. Lattice formation is facilitated and the solution accuracy is improved. Also in the visualization of the calculation result, the display time can be shortened by processing the conversion from the calculation coordinate to the physical coordinate at high speed using the coordinate conversion dedicated unit.

<Twenty-first Embodiment> Next, the second embodiment of the present invention will be described.
One embodiment will be described. FIG. 31 shows calculation grid points in the vicinity of the calculation area boundary showing an embodiment for leveling the load of each element processor and improving efficiency in parallel calculation. In the figure, 125 is a grid point on the boundary of the calculation area, 126 is a grid point inside the calculation area, and 127 is a virtual grid point adjacent to the grid point 125 on the boundary outside the calculation area. The element processors have a one-to-one correspondence.

The grid point 125 on the boundary has a smaller number of adjacent grid points than the internal grid point 126, and therefore has a smaller amount of communication and calculation than the internal grid point 126. For this reason, when it is necessary to perform a time synchronization process with another internal lattice point 126 that shortens the processing time for the lattice point 125 on the boundary, the overhead due to the synchronization is avoided and the asynchronous calculation is performed. In order to avoid the bias of the calculation load and to level the processing of all the grid points, a virtual grid point 127 is provided outside the boundary, and dummy grid communication with the grid point 125 on the boundary is performed to reduce the processing amount. It is the same as the internal grid point 125.

In the above embodiment, the calculation grid points and the element processors correspond one-to-one. However, even when a plurality of calculation grid points correspond to one element processor, Since the processing time of the element processor including the grid point 125 on the boundary is shortened, the virtual grid point 127 is connected to the grid point 125 on the boundary to provide the same calculation load as that of the element processor including only the internal grid point 126. By giving it, the same effect as that of the above-described embodiment can be obtained.

Therefore, according to this embodiment, it is possible to equalize the load of each element processor and improve the efficiency when parallelized.

<Embodiment 22> Next, the second embodiment of the present invention will be described.
Two embodiments will be described. When the element processor is a so-called Neumann type processor, when the calculation of a plurality of grid points is assigned, the time division processing is performed. This is because in the Neumann type, a single processor cannot perform parallel processing.

On the other hand, if instruction-level parallel processing is possible, for example, if a data flow processor is used, it is possible to execute calculations for a plurality of grid points simultaneously in parallel. For the data flow processor, see, for example, Mitsubishi Electric Technical Report, Vol. 66, No. 2,1992, pp24〜
It is shown in pp25. As can be seen from the above description, instruction level parallel processing is possible in the data flow processor.

As described above, in the data flow (data driven) system, simultaneously executable instructions can be independently executed.

A method of realizing a differential equation solving program based on the difference method on the data flow processor having such characteristics will be described. For example, when applied to the element processor shown in FIG. 21, a calculation program is assigned to the program memory 11 and the floating point arithmetic unit 1
At 0, the operation according to the data flow graph is performed.

FIG. 32 is a diagram showing a program memory in which a part of the program for solving the partial differential equation is written.

As shown in FIG. 32, the program memory 1
Grid points No. 1 and grid points N in different areas 131 and 132
The calculation program for o.2 is assigned. An instruction code, a destination node address, and the like are given in advance to the initial packet input from the outside in order to execute the instruction without passing through the program memory 11. When the waiting is completed in the matching memory 83,
An execute packet is generated. In the data memory 8, memory access is performed according to the instruction code. Of the fields that make up the packet output from the data memory, the destination node address is the program memory 11,
The instruction code and operand data are processed by the arithmetic processing unit 10. That is, the program memory 11 updates the destination node address of the input packet to the next destination node address read, and the arithmetic processing unit 10
Then, the result of the operation is set in the first operand data field of the packet. The result packet is processed again or output as the final result to the outside. Different areas 131, 132 of the program memory 11
Each of the two programs stored in 1 gives an instruction code and a destination node address to the result packet, and at the same time, the arithmetic processing proceeds. On a data flow type processor, these two programs are simultaneously processed in parallel while coexisting at the instruction level.

<Embodiment 23> Next, the second embodiment of the present invention will be described.
The third embodiment will be described. By performing processing using the identifier on the dynamic data flow type processor, the same program can be simultaneously executed for a plurality of sets of input data. Regarding such a dynamic data flow, for example, J. A.
It is shown in "Data Flow Computing" by Sharp, Science, Inc. (1986).

As shown in FIG. 33, two lattice points (No. 1 and No. 2) are assigned to the element processor, and the program memory 11 has a small number for the lattice points No. 1 and No. 2. Main programs 131 and 132 are stored respectively. The function of the main programs 131 and 132 is to add an identifier number (color identifier) unique to each grid point to the data, and then give these data to the calculation kernel unit 133. Calculation kernel unit 13
In the process No. 3, the processes 131 and 132 for the grid points No. 1 and No. 2 are performed at the same time. However, since the data are provided with the identifiers, the two processes are performed completely independently.

As described above, in the case of data flow processing which does not require memory access, the same program can be executed simultaneously for a plurality of sets of data by introducing a color identifier. However, data memory access cannot be controlled exclusively by the color identifier. It is the programmer's responsibility to avoid this problem. As one workaround, the color identifier and the data memory address can be converted by a program to obtain a different data memory address for each color identifier.

FIG. 34 shows an example of a function for storing the contents of the color identifier in the operand data field (hereinafter referred to as a color acquisition function). FIG. 34 is a data flow graph showing the color acquisition function. Also, the transition of the data packet is described on the right side of the figure. For the sake of simplicity in the figure, the color identifier is used as the packet format,
Only left data (first operand) and right data (second operand) are described. In the figure, reference numerals 135 to 138 are nodes for sequentially processing data. The node 135 has a PC instruction, the node 136 has an OR instruction, and the node 137.
Then, the PC instruction is executed, and at the last node 138, the SWAP instruction is executed. The functions of the instructions used in the flow graph in FIG. 34 will be described below.

(1) PC is an instruction for exchanging a color identifier and left data.

(2) OR is an instruction to perform bitwise OR operation of left data and right data and store the result in the left data.

(3) SWAP is an instruction for exchanging and outputting left data and right data.

Next, the operation of the color acquisition function will be described. In the input data packet, C1 is stored as the color identifier, 5 is stored in the left data, and DR1 is stored in the right data.

In the input data, the color identifier and the left data are exchanged by the PC command at the node 135. Next, the data is subjected to an OR operation with a constant value "0" at the node 136, and as a result, a data packet having a color identifier of 5, left data, and right data of C1 is output. Further, at node 137, a PC instruction is executed on this data packet and the color identifier is changed to C.
The packet is 1, the left data is 5, and the right data is C1.
Finally, in the node 138, the left data and the right data are exchanged by the SWAP instruction, and the same color identifier as the input data packet is stored, and the left data stores and outputs its own color identifier. The output packet from the color acquisition function could acquire its own color identifier as left data.

Next, a method of calculating the address of the data memory using the result calculated by the above color acquisition function will be described. FIG. 35 is a conceptual diagram showing an example of a method of assigning a color identifier to each grid point. In the figure, 139 is a grid point. A two-dimensional analysis in which the lattice points 139 are arranged in a mesh will be described. Here, grid points 139 arranged in a mesh of N rows and N columns are arranged.
In addition, the color identifier 0 is assigned to the upper left corner, and the color is assigned to each grid point so that the color number increases in the rightward and downward directions.

In the conceptual diagram shown in FIG. 35, each grid point 1
The code at the upper left of 39 is the color identifier assigned to each grid point. Since the above-described allocation is performed, the color identifier (CN) assigned to the neighboring grid points is set as shown in the following formula 36 using the color identifier assigned to the own lattice point acquired by the color acquisition function. Can be calculated.

As a directional term, the upper part is north,
The lower part is called south, the right part is called east, and the left part is called west. Number 3
Equation (6) of 6 shows the color identifiers assigned to the neighboring grid points in the north direction of the grid point. Similarly, Equations (2) to (4) of Equation 36 show color identifiers assigned to neighboring grid points in the south, west, and east directions of the grid point, respectively.

[0263]

[Equation 36]

As shown in FIG. 36, the Y word of the data memory 8 is assigned to each grid point, and the address of the data memory assigned to the grid point having the color identifier Z is Z × Y to Z × Y + Y. Memory allocation is performed so that the area becomes -1.

Therefore, the address of the memory assigned to the lattice point whose color identifier is CN is given by equation 37.

[0266]

[Equation 37]

However, k is a predetermined number and means that the kth word of the Y word data memory element assigned to the grid point whose color identifier is CN is accessed.

As described above, since the color identifier and the data memory address are converted by the program to access different data memory areas for each color identifier, the data can be stored without using special hardware. Even in the flow method, by asynchronously referring to the memories of the element processors 3, it is possible to equivalently realize asynchronous communication between lattice points.

<Twenty-fourth Embodiment> Next, the second embodiment of the present invention will be described.
Four embodiments will be described. In this type of information processing apparatus for solving a differential equation, the target equation is differentiated, that is, space (including time in some cases)
Is divided into grids, and in order to obtain various quantities at each grid point (representative point of the divided space), convergence calculation is executed using the calculation results at neighboring grid points. In this embodiment, a memory for storing the calculation result at each grid point is assigned to each grid point, and data is transferred between the grid points by referring to the above memory. An embodiment showing a method of exchanging data between grid points will be described below.

FIG. 37 shows the area of the data memory allocated to store the calculation result at one grid point.
In the figure, 140 is an area allocated to one grid point in the data memory 8 for storing the calculation result at the grid point, and 141 to 144 are allocated to the area 140,
This is an area in which data of communication necessity flags at grid points in the east, west, south, and north directions are stored.

As shown in FIG. 37, in the area of the data memory assigned to each grid point, (1) the data referred to by the adjacent grid point among the calculation results at the grid point,
And (2) direction of communication (here, assuming two dimensions,
(East, west, south, north direction) each of two types of flag indicating whether communication is required, whether the communication is grid point processing allocated in the same processor, or whether communication is via a network. The data of is stored.

FIG. 38 is a flow chart showing the flow of processing when communication is performed between grid points. Hereinafter, description will be given along the flowchart of FIG. 38. First, when communication is performed between grid points, the data stored at a predetermined address in the data memory area assigned for each communication direction is read (step ST1). Next, step ST
At 2, the necessity of communication is determined. That is, when the read data is "1", it means that there are adjacent grid points in the direction in which communication is to be performed, and processing for communication is performed. On the other hand, when the read data is “0”, this grid point is located on the boundary of the system, and communication is not required in this direction, and processing for communication is not performed. .

Next, in step ST3, the data stored in another predetermined address of the data memory in which the flag indicating the type of communication is stored is read according to the direction of communication and read in the same manner as above. Test the data value you made.

When the value of the read data is "0", it means that communication is performed with the lattice point allocated in the same processor, and the method shown in the 23rd embodiment of the present invention. The address calculation is performed by, and the communication between the grid points is performed by referring to and updating the data memory area allocated to the adjacent grid points.

On the other hand, when the read data is other than "0", it means that the lattice point for communication is assigned to another processor, and at the same time, the read 32-bit data is stored. The upper 8 bits are the number of the processor to which the lattice point of the communication partner is assigned, and the lower 2
The base address of the data memory assigned to the lattice point of the communication partner is stored in 4 bits. As shown in the twenty-second embodiment, the offset address is added to the above 32-bit data to calculate the address of the data memory in which the desired data is stored. When distributed shared memory access is executed using the above data as an address, the data packet is transferred via the network to the processor to which the grid point that needs to be communicated is assigned, the desired data is read, and communication is performed again with that data. Return to the original processor and continue calculation of grid points.

As described above, in a multiprocessor that communicates between grid points, information indicating whether or not communication is possible for each direction at each grid point, communication availability such as communication through a network, and a method. The field to store is allocated in the data memory, and the distributed shared memory access is used for the communication through the network.
The distributed shared memory access mechanism is disclosed in detail in Japanese Patent Application Laid-Open No. 3-122338.

Therefore, the processing of the grid points on the boundary and the processing of the grid points on the boundary can be realized by the same program, and the program size can be reduced.

Further, when each grid point is allocated over a plurality of processors, communication between grid points across the processors can be easily realized regardless of the grid point allocation method.

In the twenty-fifth, twenty-sixth, twenty-seventh and twenty-eighth embodiments of the present invention described below, processing programs for a plurality of grid points are assigned to the same element processor. It is premised that data is exchanged between grid points via a data memory in the same element processor. Below, each embodiment will be described in detail.

<Twenty-fifth Embodiment> Next, the second embodiment of the present invention will be described.
Five embodiments will be described. In a multiprocessor which allocates a memory for each grid point and communicates between adjacent grid points via this memory, a calculation method having a table showing a memory area in each direction to be communicated for each grid point will be described.

FIG. 39 is a diagram showing division of the data memory area. In the figure, 145 is an area assigned to one grid point in the data memory 8 in order to obtain the calculation result at an adjacent grid point, and 146 to 149 are assigned to the area 145, respectively in the east, west, south and north directions. This area stores the start address of the memory area of the grid point.

As shown in FIG. 39, the start address of the memory area of the grid point in each direction requiring communication is stored in the memory allocation for each grid point. In the case of this embodiment, for each grid point, east direction, west direction, south direction,
The four data areas 146 to 149 in the north direction are used to store the start addresses of the memory areas of the grid points in the communication direction.

FIG. 40 is a flow chart showing the flow of processing for communication. When performing communication, the top address of the memory area of the communication destination is read according to the communication direction (step ST6). The direction you are trying to communicate
In the case of the communication impossible direction, -1 is stored in advance in the area for storing the start address of the memory area of the grid point in the communication direction. If the read data is -1, communication processing is not performed (step ST7). If it is confirmed that the communication is not possible, the address offset of the data to be communicated is added to the head address of the communication destination, the address for actual communication is obtained, and actual communication is performed (step ST8).

In the above embodiment, an example of storing the start address of the memory area in each direction to be communicated is shown. However, for example, when the memory areas are arranged in the order of the grid point numbers, the grid points are The present invention can be applied to an embodiment in which a number is stored.

Further, in the above-mentioned embodiment, an example of storing the head address of the memory area in each direction to be communicated is shown. However, an identifier capable of specifying the memory area to be communicated,
For example, the difference between the start address of the memory area of the grid point of the communication source and the start address of the memory area of the communication destination, or the distance between grid points, which is the value obtained by dividing the value by the size of the memory used by one grid point, The present invention can be applied to all embodiments in which a pointer is stored.

Further, in the above-mentioned embodiment, the case where four directions are set as the communication directions has been described. However, six directions and eight directions (northeast, northwest, southwest, southeast, or a part thereof is included). In the case of), the present invention can be applied.

Further, in the above embodiment, in the case of the incommunicable direction, the case where -1 is stored has been described, but any value not used as the identifier is used as the identifier indicating the incommunicable direction. The present invention can also be applied to the embodiments described above.

Even in the case of the processing in which the lattice points to be communicated are changed, such as the neighboring lattice points to be communicated are a little apart in the coarse node processing, and the neighboring lattice points are in the fine node processing. , It is possible to perform processing with exactly the same program simply by rewriting the area of the identifier indicating the memory area of the grid point in the communication direction.

Further, conventionally, when a region having unevenness as shown in FIG. 41 is to be processed, a square or a rectangle including the uneven region is to be processed. Therefore, it is necessary to process grid points that do not need to be processed originally. However, when the present invention is applied, a grid point that cannot communicate with any grid point in any direction is recognized. Since it is possible to perform the processing, it is possible to perform processing with the uneven area as it is. As a result, the memory area of the grid points outside the uneven area, which has been wastefully processed in the past, becomes unnecessary, and the memory size can be compressed. Further, it is not necessary to process the grid points outside the uneven area, and the processing speed can be increased. Both memory size compression and processing speed can be realized.

As an identifier used as an identifier in the communication direction of this embodiment, a grid point number or the difference between the start address of the memory area of the grid point of the communication source and the start address of the memory area of the communication destination is one grid. When the value divided by the size of the memory used by the point is used, the number of bits required as the memory is smaller and the used memory size is compressed, as compared with the case of using the address or the address difference itself.

The above embodiment provides a memory area access method when a large number of lattice points are convoluted in one element processor. Regarding the communication between the element processors, the following embodiment is provided. This makes it possible to simplify communication.

When the element processors are connected to the lattice type topology, communication with the element processors in the diagonal direction becomes a problem. FIG. 42 is a diagram showing a communication system with diagonal element processors. In the figure, 151 is an NW direction element processor, 152 is an N direction element processor, and 153.
Is an element processor in the NE direction, 154 is an element processor in the W direction, 155 is an element processor being calculated,
6 is an element processor in the E direction, 157 is an element processor in the SW direction, 158 is an element processor in the S direction,
Reference numerals 159 denote SE-direction element processors, respectively.

In the figure, 160 is a virtual communication path in the NW direction, 161 is a virtual communication path in the SE direction, and 162 is a virtual communication path.
Is a network between element processors, 163 is a virtual communication path in the SW direction, and 164 is a virtual communication path in the NE direction. When the element processors 155 communicate with the element processors 151 and 159 in the NW direction and the SE direction, in the conventional method, the virtual communication paths 160 and 161 are directly connected between the element processors 151 and 155 and between the element processors 155 and 1.
Communication is performed by laying between 59 or data communication is performed via the element processor 152 or 158. However, in these communication methods, there are many problems such as the communication network being too complicated in the former case and the communication synchronization waiting time being large and the speed performance of the entire system being deteriorated in the latter case. Therefore, each element processor duplicately holds the data of the upper and lower element processors in the memory, so that, for example, communication with the element processor 151 is performed by the data of the element processor 151 stored in the memory of the element processor 154. The communication method is simplified by referring to. However, the duplicated data must be rewritten every time the original data is updated.

Further, instead of the data of the upper and lower element processors, the data of the left and right element processors are double held,
For example, when communicating with the element processor 151, the same effect can be obtained by accessing the data of the element processor 151 stored in the memory of the element processor 152.

<Twenty-sixth Embodiment> Next, the second embodiment of the present invention will be described.
Six embodiments will be described. In a multiprocessor that allocates a memory for each grid point and communicates between adjacent grid points via this memory, holds information indicating the memory area in each direction to be communicated for each grid point, and communication is not possible Information indicating a common dummy area is held in the direction.

FIG. 43 shows a memory allocation diagram used in the twenty-sixth embodiment. In FIG. 43, 170 is a memory area allocated to a grid point to be processed in the data memory 8, 171 is a memory area allocated to one grid point in the memory area 170, and 172 is a grid point to be processed. This is a memory area for one grid, which is allocated as a dummy area for the incommunicable direction, which is allocated in the data memory 8 separately from the allocated memory area 170. In addition to the memory area for the grid points to be actually processed, a memory area for one grid is secured as a dummy area for the incommunicable direction. As an identifier indicating an incommunicable area in an area storing an identifier indicating a memory area of a grid point in each communication direction of a memory area assigned to a grid point to be actually processed,
The identifier indicating the dummy area is stored.

The processing flow of this embodiment is shown in FIG. When performing communication processing, an identifier indicating a memory area of a grid point in the communication direction is read (step ST1).
0). Then, whether or not the identifier is a dummy area, communication processing is performed for that area (step S
T11).

When the communication processing includes reading from the communication destination area, a value that does not adversely affect the processing is also stored in advance in the dummy area. However, in the communication, it is possible to limit the processing from the communication source to the communication destination to only writing, by processing so that the data necessary for the processing of each grid point is always passed from the adjacent grid point in advance.

Since the same processing is performed regardless of whether communication is possible or not, the program of the determination part is unnecessary and the program size can be compressed.

Since the same processing is performed regardless of whether communication is possible or not, it is possible to suppress variations in calculation load for each grid point, and to avoid excessive progress of processing only for grid points with many directions where communication is impossible. Even if synchronization processing between grid points is required, the program size can be reduced and the processing speed can be increased.

<Twenty-seventh Embodiment> Next, the second embodiment of the present invention will be described.
Seven embodiments will be described. When adjacent grid points are allocated across element processors, it is effective to double hold the other party's data in both element processors in order to reduce the delay time of data transfer. In this case, it is necessary to send the new data to the adjacent program whenever the data for these grid points is updated to ensure the consistency of the data of both element programs.

However, transmitting the data to the adjacent element processor each time the data is updated results in unnecessarily increasing the inter-processor communication when the difference between the updated data is small, and the original processing is performed. Adversely affect. FIG. 45 is a conceptual diagram showing the state of communication between adjacent processors. In the figure, the left element processor 3
Calculates the grid points No. 0 to No. n, and the element processor 3 on the right side calculates the grid points No. n + 1 to No. m. As shown in FIG. 45, for example, the element processor 3 on the left side is the grid point No. n.
When the calculation result data of is sent to the adjacent element processor 3,
Such adverse effect can be avoided by comparing the data A to be transmitted to the adjacent element processor 3 with the data B of the previous generation and not transmitting the same if the displacement is equal to or less than a certain value. .

Data B is now the previous generation (ie,
Although the previous calculation result data) has been used, if "Don't send if the displacement is less than a certain value", there is concern that a difference may be accumulated even if the change is small each time. May be the data transmitted to the adjacent element processor 3 last time.

<Twenty-eighth Embodiment> Next, the second embodiment of the present invention will be described.
Simplification of the program for solving the equations according to the eight embodiments will be described. FIG. 46 is a plan view showing the relationship between the calculation area for analysis of equations and the grid points assigned to the calculation area. Consider a grid point for one round outside a grid point surrounded by a solid line and requiring processing. A memory area for each grid point for one outer circle is allocated, and the numbers below each grid point are set as grid point numbers.

When the grid point number of the communication source is n, the grid point number in each direction can be obtained by the calculation of Expression 38, and no special processing is required for the end grid points.

[0306]

[Equation 38]

Assuming that the data for the grid point is secured from the address S for each grid point in order of R entries for each grid point, and if the grid point number of the communication destination obtained by the above calculation is D, then At 39, the start address of the data area of the lattice point of the communication destination can be obtained. The communication process is the same as in the 25th and 26th embodiments.

[0308]

[Formula 39]

When the communication processing includes reading from the communication destination area, a value that does not adversely affect the processing is stored in advance in each dummy area. This can be realized by, for example, omitting a large influence by providing the dummy area with the same data as the neighboring grid points that have the same data as the wall. If there is a value that is the unit element of each calculation, it can be realized by setting that value.

In this embodiment, the grid point number in each direction is obtained by calculation. However, as in the twenty-fifth embodiment, the grid point identifiers in the communication direction are stored in the memory as described above. The method can be applied.

In the twenty-fifth to twenty-seventh embodiments, description has been given of the case where the memory of the area gathered into one is assigned to each grid point, but the area is secured by each element such as pressure value and speed. However, it is also applicable to the embodiment in which each element is stored in the order of the grid point number, and the area is secured for each element.

In the calculation method in which the data memory area is allocated to each grid point and the data of the adjacent grid points can be obtained by referring to the memory, the grid points outside the boundary grid points are simulated. By allocating the virtual data area to be used, the processing program can be simplified, the program size can be reduced, and the processing speed can be increased.

When the area is secured by storing each element, the cache hit rate can be improved and the processing can be speeded up by storing the elements that are frequently accessed.

<Twenty-ninth Embodiment> Next, the twenty-ninth embodiment of the present invention will be described.
An embodiment will be described. In the solution of the differential equation, the target system is divided into fine grid points.In this case, the state of the grid points determined by the boundary conditions propagates to all grid points, and until the stable state is reached, There is a concern that it takes time proportional to the number of points to the grid point node and the time to reach convergence is long.

In order to avoid such inefficiency, it is conceivable to use coarse nodes and fine nodes alternately to improve convergence. FIG. 47 shows calculation grid points near the boundary of a calculation region showing an embodiment for improving convergence by alternately using coarse nodes and fine nodes. In the figure, 125 is a grid point on the boundary of the calculation area, 126a is a grid point inside the calculation area at the time of fine node connection, 126b is a grid point inside the calculation area at the time of coarse node connection, and 7a is an element for the fine node connection. An inter-processor connection, 7b is an inter-element processor connection for coarse node connection, and these lattice points and each element processor have a one-to-one correspondence.

In this embodiment, the grid points 126a and 126b inside all calculation areas are connected by the inter-element processor connection 7a at the time of the fine node connection at the time of the fine node connection, and a plurality of internal grids at the time of the coarse node connection. The points are jumped and the internal lattice points 126b at the time of the coarse node connection are connected by the inter-element connection 7b at the time of the coarse node connection. Here, since the internal grid point 126b at the time of coarse node connection plays the role of a calculation grid point both at the time of the fine node and at the time of the coarse node, the internal grid point 126 at the time of the coarse node.
The internal data memory of b plays a role of passing information at the time of the coarse node and the time of the fine node. Then, in the calculation, the fine node coupling and the coarse node coupling are alternately used. In such a configuration, the boundary condition that the grid point 125 on the boundary has by the inter-element connection 7b at the time of coarse node connection is transmitted to the inside of the calculation area three times faster than at the time of fine node connection, and then becomes closer by the fine node connection. The detailed calculation is carried out by being transmitted to the internal lattice point 126a at the time of the fine node combination of.

Therefore, according to this embodiment, by using the coarse node, the boundary condition is immediately permeated into the calculation region to improve the convergence, and thereafter, by using the fine node, a calculation result with high calculation accuracy can be obtained. As a result, highly accurate and high-speed operation can be achieved.

In this embodiment, an example is shown in which the grid points in the fine node connection are connected every two points at the time of coarse node connection, but it is needless to say that the same effect can be expected at any number of points. Further, in this embodiment, the roughness of the lattice is set to two levels, that is, fine node coupling and coarse node coupling.
Further, the same effect can be obtained by using a grid having a plurality of stages of roughness. Furthermore, in this embodiment, the case where the calculation at the time of coarse node connection and the calculation at the time of fine node connection are alternately performed once has been described, but the calculation at the time of coarse node connection and the calculation at the time of fine node connection are alternately performed a plurality of times. You may go to

In the above embodiment, the case where the coarse node and the fine node are alternately used has been described. However, after the convergence at the coarse node, the precision of the solution is gradually improved by using the finer node. You can take the way you want to.

That is, in FIG. 47, until a convergent solution is obtained using the internal grid points 126b and the grid points 125 on the boundary at the time of coarse node connection, which are connected by the inter-element processor connection 7b at the time of coarse node connection. Iterative calculation is performed, and thereafter, internal grid point 126b at the time of coarse node connection
Is given as the initial condition, or the solution of the internal grid point 126b at the time of coarse node connection is proportionally distributed according to the spatial distribution of the fine nodes and given as the initial condition, and the connection between the element processors at the time of fine node connection is performed. Using the internal grid point 126a connected by 7a, the internal grid point 126b at the time of coarse node connection, and the grid point 125 on the boundary,
Repeated calculations are performed until the accuracy of the solution increases, and the convergent solution is used as the final solution.

By adopting this method, it is possible to greatly accelerate the calculation time until global convergence. That is, wasteful local calculation can be avoided, stable convergence can be achieved, and at the same time final convergence can be reached earlier.

Further, in this embodiment, the case where the lattice points and the respective element processors have a one-to-one correspondence has been described, but the case where the spatial region in which a plurality of lattice point groups exist corresponds to the respective element processors ( The same effect can be obtained even in the case of allocation).

<Embodiment 30> Next, the third embodiment of the present invention will be described.
An embodiment will be described. In the twenty-ninth embodiment, the case where the coarse node coupling is realized by skipping the coupling connection between the adjacent element processors by the jumper wiring has been described. In this embodiment,
A case where this coarse node is realized only by S / W will be described.

As described in the twenty-fifth embodiment of the present invention,
A method for realizing an area of data memory for each grid point and performing data communication between grid points by mutually accessing the area of the data memory reserved for each grid point between grid points that require communication. In, there is a table indicating the data memory area in each direction to be communicated for each grid point, and the address of the data memory area reserved for the grid points skipped by the desired number of grid points is stored in each entry of this table. As a result, data communication can be performed with grid points other than adjacent grid points, that is, coarse node coupling can be realized only by S / W.

Therefore, at the stage where the solution of the field equation is started, the table indicating the data memory area in each direction to be communicated is set so as to realize the coarse node processing, and after the processing converges, the above table is set. The fine node processing can be performed by changing to point to the data memory area secured at the adjacent grid point so as to realize the fine node processing.

The coarse node processing and the fine node processing can be executed alternately by rewriting the table appropriately in the same manner as described above.

Further, there are two tables for the data memory areas in each direction to be communicated, one for coarse node connection processing and one for fine node connection, and a program for coarse node processing and a program for fine node processing. It is also possible to execute the processing of the coarse node and the processing of the fine node in parallel by executing in parallel.

Even in the case of processing in which the grid points to be communicated are changed, such as the neighboring grid points to be communicated are a little apart in the coarse node processing, and the neighboring grid points are in the fine node processing. , It is possible to perform processing with exactly the same program simply by rewriting the area of the identifier indicating the memory area of the grid point in the communication direction.

In the above embodiment, the case where the convergence is improved by simultaneously executing the coarse node and the fine node has been described, but the algorithm of the coarse node processing and the algorithm of the fine node processing do not have to be the same. By having the programs for the coarse node and the fine node separately, different algorithms can be used as the algorithm for the coarse node processing and the algorithm for the fine node processing.

For example, it is possible to further improve the convergence of the entire system by using an algorithm that has good convergence but lacks accuracy in the coarse node.

In the above-mentioned embodiment relating to the SIMPLE method, the calculation for the corresponding grid point is performed with reference to the current data of the adjacent grid points. However, if there are two or more generations of data related to adjacent grid points and the variation between generations is less than a certain amount, the calculation of the corresponding node is omitted to reduce the total calculation amount and significantly reduce the calculation time. You can Further, there is also an effect that the calculation resource obtained by omitting the calculation of the grid points whose intergenerational variation is less than a certain value can be used for processing other grid points. The "2nd generation data" referred to here is "data based on the calculation result of one step before the iterative calculation" regarding the adjacent grid points.
And "data based on the calculation result two steps before the repeated calculation".

In the SIMPLE method described above, a condition for omitting the calculation at each grid point is given. The data difference between the generations of adjacent grid points was a constant value. However, in the process of convergence calculation, the tolerance for the difference in data between generations, which is a condition for omitting the calculation, is first increased and then gradually reduced until global convergence is reached. The calculation time of can be greatly accelerated. By applying this method, it is possible to avoid wasteful local calculation and reach the final convergence earlier.

<Thirty-first Embodiment> Next, the third embodiment of the present invention will be described.
One embodiment will be described. In a conventional parallel computer, the focus was on minimizing the number of calculations.Therefore, the presence or absence of convergence is determined when the calculation of all grid points at a certain time is completed. Since there is a sequential means of advancing and restarting the calculation of each grid point, there is a drawback in that the convergence process limits the whole rate.

Generally, in fluid simulation, (computation cost CA at each grid point)> (convergence determination processing cost C
Since the relationship of C) is established, this configuration can be adopted by preparing some buffer devices. Also,
This buffer can be small if partial convergence is determined. Letting N be the number of repeated calculations until convergence, N · (CA + CC + α) is reduced to N · CA + α in execution time. However, α is a communication cost.

FIG. 48 is a block diagram of a multiprocessor showing an embodiment of the present invention for cutting off the interdependence between the simulation and the convergence judgment processing and improving the speed of the simulation.

In the figure, 3k is an element processor for performing calculation, and 180 is each element processor 3k arranged in each column.
A convergence determination unit for determining the convergence status for each column based on the information of the convergence flag output by 1; 1 is a host computer for centrally managing the element processors 3k and the convergence determination unit 180; and 104 is an operation between the element processors 3k in the row direction. , A row-direction calculation information bus for exchanging data for, a column-direction calculation information bus 105 for exchanging data for calculation between the column-direction element processors 3k, and 181 output by each element processor 3k. A convergence flag information bus for transmitting the convergence flag to the convergence determination unit 180, and a convergence information bus 182 for transmitting the convergence information of each convergence determination unit 180 to the host computer.

Next, the operation will be described. Each element processor 3k judges the convergence of the calculation for each internal calculation result or for each certain number of calculation repetition steps with respect to its own internal calculation result. For example, if it converges, the convergence judgment flag is set to 1 and the convergence flag information bus It is outputting to 181. The convergence determination unit 180 is each element processor 3k
The convergence determination flag information output from the above is collected, and if it is determined that all the element processors 3k under the control of each convergence determination unit 180 have converged, the convergence information is individually output to the convergence information bus 182. Then, finally, the host computer 1 judges the overall convergence from the convergence information of all the element processors 3k sucked from the all-convergence information bus 182, and ends the calculation.

With this configuration, each element processor 3k can execute operations in parallel without hindering each operation, and the operation speed can be increased.

In this embodiment, the convergence judgment unit 180 groups the rows of the element processors arranged in a grid and manages the convergence information of this group, but the groups are grouped by the columns. Needless to say, the same effect can be obtained by randomly grouping.

<Thirty-second Embodiment> The thirty-second embodiment of the present invention will now be described.
An embodiment will be described. FIG. 49 is a block diagram of a multiprocessor showing an embodiment for further cutting off the interdependence between the simulation and the convergence determination processing and improving the speed of the simulation.

In the figure, 3k is an element processor for performing calculations, 180 and 180a are convergence determining units for determining the convergence status for each column based on the convergence flag information output from each element processor 3k arranged for each column. A host computer for centrally managing the element processor 3k and the convergence determination unit 180, 104 a row direction calculation information bus for exchanging data for calculation between the row direction element processors 3k, and 105 a column direction element processor A column-direction calculation information bus for exchanging data for computation between three, a reference numeral 181 is a convergence flag information bus for transmitting a convergence flag indicating the convergence status of each element processor 3k to the convergence determination unit 180, and 182 is an adjacent The convergence determination unit 180 and the host computer 1 are connected to each other. It is a convergence information bus for transmitting the 80 convergence information.

In this configuration, the convergence judgment unit 1
80 is a convergence information bus 18 so that information can be transmitted only in one direction to the convergence determination units adjacent to each other.
I have two. Then, when the calculation of all the element processors 3k under the control of the convergence determination unit 180a farthest from the host computer 1 has converged, the transmission of the convergence information is started. When the convergence information from the adjacent convergence judgment unit 180 and the judgment by the convergence flag that the calculation of all the element processors 3k under its control have converged, the other convergence judgment unit 180 makes the convergence information adjacent. To the convergence determination unit 180.

In this way, when the convergence judgment unit 180 closest to the host computer 1 sends the convergence information to the host computer 1, the host computer 1 can immediately judge the end of the calculation, so that the element processors 3k and The calculation speed can be further increased without disturbing the processing of the host computer 1.

In this embodiment, the convergence judgment unit 180 groups the rows of the element processors arranged in a grid and manages the convergence information of this group, but the groups are grouped by the columns. However, it goes without saying that the same effect can be obtained by randomly grouping. The same effect can be expected even if the convergence determination units 180 are connected regardless of the distance from the host computer 1.

<Thirty-third Embodiment> Next, the third embodiment of the present invention will be described.
The third embodiment will be described. As shown in the thirty-second embodiment, transmitting the convergence flag via the convergence flag information bus configured outside the element processor causes a loss of communication time. FIG. 50 is a block diagram showing the configuration of an element processor according to the 33rd embodiment for shortening the transmission time of the convergence flag. Further, FIG. 51 is a block diagram showing the configuration of a multiprocessor having the element processor of FIG. 50 as a component.

In FIG. 50, 3m is a main body of an element processor, 5 is a processing unit formed in the element processor 3m for executing calculation, and 6 is calculation information necessary for calculation of the processing unit 5 formed in the element processor 3m. And a memory unit 183 formed in the element processor 3m to which the element processor 3m belongs.
State of the processing unit 5 in the inside, the state of convergence in the adjacent element processor 3m, and all the element processors 3
A convergence determination unit for determining the convergence state of m, 104 is a row direction calculation information bus for exchanging data necessary for calculation between the memory units 6 in the element processors 3m in the row direction, 105
Is a column-direction calculation information bus for exchanging data necessary for the calculation between the processing units 5 in the element processors in the column direction, and 181 is a convergence determination unit 183 in each element processor connected in a ring shape to set a convergence flag. A convergence flag information bus for transmission to a convergence determination unit 183 in an adjacent element processor, and 182 connects at least one or more convergence determination units 183 of the convergence determination units 183 of all the element processors to the host computer. Convergence information bus for transmitting the convergence information to the host computer 1, 184 is an internal information flag bus for transmitting the convergence flag output from the processing unit 5 to the convergence determination unit 180, and 106 is between the processing unit 5 and the memory unit 6. In exchanging data necessary for calculation and calculation result data Calculation information, which is the bus.

In FIG. 51, 1 is the element processor 3
This is a host computer for centrally managing m and 3k. In each processing unit 5, the convergence of the calculation is judged for each calculation repeating step or for each certain number of calculation repeating steps. For example, if the calculation converges, the internal information flag is set to 1 and the convergence judgment is made via the internal information flag path 184. It is sent to the unit 183. The convergence determination unit 183 of each element processor 3k is connected in a ring shape via the convergence flag information bus. The convergence determination is started from a predetermined specific element processor 3m. At the same time that the convergence determination unit 183 of the element processor 3m receives the internal information flag indicating that the processing unit 5 therein has converged, for example, if it has converged, the convergence flag is set to 1 and the adjacent element processor 3k.
Is transmitted to the convergence determination unit 183 through the convergence flag information bus. Here, it is assumed that the convergence information flag bus 181 connected in a ring shape has a function of transmitting information in one direction. The convergence determination unit 183 of the adjacent element processor 3k described above receives the internal information flag (= 1) from the processing unit of the element processor 3k to which it belongs and the convergence flag (=) from the convergence determination unit 183 of the adjacent element processor 3m. True (= 1) by taking the logical product (AND) of 1)
If so, the convergence flag is set to 1 and is sent to the convergence determination unit 183 of the adjacent element processor 3k via the convergence flag information bus 181.

[0348] Each convergence determination unit 183 connected in a ring shape
Is the logical product (AND) of the internal information flag (= 1) from the processing unit of the element processor 3k to which it belongs and the convergence flag (= 1) from the convergence determination unit 183 of the adjacent element processor 3k If so, the procedure of setting the convergence flag to 1 and sending it to the convergence determination unit 183 of the adjacent element processor 3k via the convergence flag information bus is sequentially performed in the connection order of the convergence flag information bus 181. Finally, when the convergence flag (= 1) is returned to the convergence determination unit 183 of the element processor 3m that first transmitted the convergence flag as 1, all the element processors 3k, 3
It is determined that m has converged, the convergence information (= 1) is sent to the host computer 1 via the convergence information bus 182, and the calculation is ended.

In this way, the internal information flag bus 1
Since 81 is provided inside each of the element processors 3k and 3m, it is possible to shorten the transmission time of the information regarding the convergence and to achieve the speeding up of the calculation.

Although the internal information flag, the convergence flag information, and the convergence information have been described as logical values of 0 or 1 in the above embodiment, any value may be used as long as it can be determined whether convergence or non-convergence. Further, the convergence information bus 182 need only be provided in one element processor 3m, and need not be provided in all element processors.

Further, the specific element processor 3m may be any of all element processors.

<Embodiment 34> Next, the third embodiment of the present invention will be described.
Four embodiments will be described. FIG. 52 shows a multiprocessor configuration showing an embodiment for dividing all element processors into a plurality of groups, forming an information transmission link of a convergence information flag path for each group, and realizing parallelization of convergence determination. It is a block diagram shown.

In FIG. 52, 181 divides all the element processors into a plurality of groups, connects the convergence determination units 183 in the respective element processors 3k and 3m in the group in a ring shape, and sets the convergence flag to the adjacent element processors 3k and 3k. A convergence flag information bus for transmission to the convergence determination unit 183 in 3 m, and 182 is provided in one specific element processor 3 m in each group and connects the convergence determination unit 183 and the host computer 1 to transfer the convergence information of each group. This is a convergence information bus for

Within each group, the convergence information bus 182
Convergence determination unit 1 of specific element processor 3m provided with
At 83, at the same time as receiving an internal information flag indicating convergence from the processing unit 5 inside thereof, for example, if it converges, the convergence flag is set to 1 and the convergence determination unit 183 of the adjacent element processor 3k receives it via the convergence flag information bus. To send. Here, it is assumed that the convergence flag information bus 181 connected in a ring shape between the convergence determination units 183 of the element processors in the group has a function of transmitting information in one direction. The convergence determination unit 183 of the adjacent element processor 3k described above receives the internal information flag (= 1) from the processing unit of the element processor 3k to which it belongs and the convergence flag (=) from the convergence determination unit 183 of the adjacent element processor 3m. AND of 1)
If the result is true (= 1), the convergence flag is set to 1 and is sent to the convergence determination unit 183 of the adjacent element processor 3k via the convergence flag information bus 181.

Convergence determining units 183 connected in a ring shape
Is the logical product (AND) of the internal information flag (= 1) from the processing unit of the element processor 3k to which it belongs and the convergence flag (= 1) from the convergence determination unit 183 of the adjacent element processor 3k If so, the procedure of setting the convergence flag to 1 and sending it to the convergence determination unit 183 of the adjacent element processor 3k via the convergence flag information bus is sequentially performed in the connection order of the convergence flag information bus 181. Finally, when the convergence flag (= 1) of 1 is returned to the convergence determination unit 183 of the specific element processor 3m that first transmitted the convergence flag as 1, it is determined that all the element processors 3 in the group have converged. Judgment, convergence information (=
1) is sent to the host computer 1 via the convergence information bus 182. When the host computer 1 receives the convergence information (= 1) from all the groups, it determines that the calculations of all the element processors have converged, and ends the calculations.

According to this structure, the convergence judgment is made parallel for each group, and the convergence judgment time can be shortened.

Note that in this embodiment, the convergence determination unit 183 groups the rows of the element processors arranged in a grid and manages the convergence information of this group. However, it goes without saying that the same effect can be obtained by randomly grouping. Further, in the above embodiment, the internal information flag, the convergence flag information, and the convergence information have been described as logical values of 0 or 1, but any value may be used as long as it can be determined whether convergence or non-convergence. The convergence information bus 182 need only be provided in one element processor 3m in the group, and need not be provided in all element processors.

Further, the specific element processor 3m may be any of the element processors in the group.

<Embodiment 35> Next, the third embodiment of the present invention will be described.
Five embodiments will be described. FIG. 53 is a block diagram showing the configuration of an element processor forming a multiprocessor for reducing the load on the host computer when parallelizing the convergence determination. Also, FIG.
4 is an overall configuration diagram of a multiprocessor having the element processor of FIG. 53 as a component.

In FIG. 53, reference numeral 181 indicates that all the element processors 3k, 3p and 3q are divided into a plurality of groups, the convergence judgment units 183 in the respective element processors in the group are connected in a ring shape, and the convergence flags are adjacent to each other. A convergence flag information bus for transmission to the convergence determination unit 183 in
Reference numeral 182 denotes a convergence information bus in which at least one or more element processors 3p and 3q of each group are connected to each other, and a convergence determination unit 183 of the element processors 3p and 3q of which the adjacent groups are provided are connected in a ring shape, and 186 denotes all groups Is a termination information bus that is provided in at least one of all element processors 3p and connects the convergence determination unit 183 of this element processor 3p to the host computer to transmit convergence information of all groups.

When the grouping as shown in FIG. 54 is performed, the convergence determination unit 183 of the specific element processor 3p in the group provided with the convergence information bus 182 starts the convergence determination, and the processing unit 5 therein.
At the same time as receiving the internal information flag indicating that it has converged, if it converges, it sets the convergence flag to 1 and sends it to the convergence determination unit 183 of the adjacent element processor 3k via the convergence flag information bus. Here, it is assumed that the convergence information flag bus 181 connected in a ring shape between the convergence determination units 183 of the element processors 3k and 3p in the group has a function of transmitting information in one direction.

The convergence determining unit 183 of the adjacent element processor 3k described above receives the internal information flag (= 1) from the processing unit of the element processor 3k to which it belongs.
And the convergence determination unit 1 of the adjacent element processors 3p and 3q
When the logical product (AND) of the convergence flags (= 1) from 83 is obtained and the result is true (= 1), the convergence flag is set to 1 and the convergence determination unit 183 of the adjacent element processor 3k is passed through the convergence flag information bus. To send. Each of the convergence determination units 183 connected in a ring shape has an internal information flag (= 1) from the processing unit of the element processor 3k to which it belongs and a convergence flag (= 1) from the convergence determination unit 183 of the adjacent element processor 3k. If the logical product (AND) of 1) is taken to be 1, the convergence flag is set to 1, and the procedure for transmitting to the convergence determination unit 183 of the adjacent element processor 3k via the convergence flag information bus 181 is performed. Implement one after another in the order of connection. Finally, the convergence flag (=
When 1) is returned, it is determined that all the element processors 3p or 3q in the group have converged.

Further, if the convergence determining unit 183 of a specific element processor among the element processors 3p provided with the end information bus 186 determines that all the element processors 3p and 3k of the group to which the self processor belongs have converged, the convergence information The convergence information (= 1) is transmitted through the convergence information bus connected in a ring shape with 1. Here, it is assumed that the convergence information bus 182, which is connected in a ring shape between the convergence determination units 183 of the element processors 3p and 3q in the group, has a function of transmitting information in one direction.

The element processor 3p of a predetermined group sends it to the element processor 3q provided with the convergence information bus 182 of the adjacent group. Element processor 3 provided with the convergence information bus 182 of the aforementioned adjacent group
The convergence determination unit 183 of q determines the convergence information (= 1) of the group to which the self belongs and the convergence information (= 1) of the adjacent group.
If it is true (= 1) by taking the logical product (AND) of the above, the convergence information is set to 1, and the convergence information is sent to the convergence determination unit 183 of the element processor 3q of the adjacent group via the convergence information bus 182.

As described above, each of the convergence determining units 183 connected in a ring shape has convergence information (=
When the logical product (AND) of 1) and the convergence information (= 1) from the adjacent group is taken to be 1, the convergence information is set to 1 and the convergence information bus 182 of the adjacent group is provided to the element processor 3q. The procedure of sending to the convergence determination unit 183 via the convergence information bus 182 is sequentially executed in the order of connection of the convergence information bus 182.

Finally, when the convergence information (= 1) is returned to the convergence determination unit 183 of the specific element processor 3p that first transmitted the convergence flag as 1, all the element processors 3k, 3p, It is determined that 3q has converged, and the end information (= 1) is sent to the host computer 1 via the end information bus 186. When the host computer 1 receives the end information (= 1), all the element processors 3
It is judged that the calculations of k, 3p and 3q have converged, and the calculation is ended.

With this configuration, it is possible to reduce the load on the host computer when parallelizing the convergence determination, and it is possible to further speed up the calculation.

In this embodiment, the convergence determination unit 183 groups the rows of the element processors arranged in a grid and manages the convergence information of this group, but groups the columns. However, it goes without saying that the same effect can be obtained by randomly grouping. Further, in the above embodiment, the internal information flag, the convergence flag information, and the convergence information have been described as logical values of 0 or 1, respectively, but any value may be used as long as it can be determined whether convergence or non-convergence. Further, the convergence information bus 182 may be provided in one element processor 3p and 3q in the group,
It does not need to be provided in all element processors. Furthermore, the end information bus 186 need only be provided in one element processor 3p, and need not be provided in all element processors.

Further, the specific element processors 3p and 3q may be any of the element processors in the group, and the specific element processor 3p may be any of the element processors representing the group.

<Embodiment 36> Next, the third embodiment of the present invention will be described.
Six embodiments will be described. When a convergence calculation is executed on a multiprocessor, an instability point (nonconvergence point) may circulate, although it is rare. It is necessary to detect such a so-called "oscillation phenomenon".

The "oscillation phenomenon" can be detected by once confirming the convergence in all the element processors and then making the convergence judgment again. By making the convergence judgment a plurality of times, the convergence can be judged with considerable accuracy. You can

Specifically, the end flags are sequentially transferred in accordance with a predetermined route, and the convergence judgment as a whole is performed. FIG. 55 is a conceptual diagram showing an example of a route for transferring the end flag. In FIG. 55, reference numerals 190 and 191 denote grid points obtained as a result of discretizing the two-dimensional space. Further, an arrow line 192 connecting each lattice point indicates a route to which the end flag is transferred.

The processing for determining the convergence at each grid point will be described below. When convergence is confirmed for the first time after the arrival of the end flag from the adjacent grid point, the end flag is propagated to the next grid point. FIG. 56 shows a flowchart for each grid point to propagate the end flag to the adjacent grid point. However, the processing of the grid point 190 that is the starting point of the end flag is excluded.

As shown in FIG. 56, first, it is determined whether or not a message having an end flag has arrived from an adjacent grid point (step ST20). Then, when a message having an end flag arrives from an adjacent grid point, the self-grid point convergence determination processing is driven and waits until the self-grid point processing reaches convergence (step ST21). A message having an end flag is transferred to the next grid point along a predetermined route as shown (step ST22).

FIG. 57 shows a flowchart for transmitting the end flag at the grid point which is the starting point of the end flag transfer. As shown in the figure, at the grid point which is the starting point of the end flag, only the convergence of the processing at the self-grid point is judged (step ST25), and if it has converged, it follows the path as shown in FIG. And sends the message with the end flag to the next grid point (step ST26).

As described above, after passing through all the lattice points, the end flag is transferred to the host computer and the convergence is confirmed. In the multiprocessor of the thirty-fifth embodiment, once the convergence is confirmed, the above process is repeated again to ensure the convergence determination.

As described above, in this embodiment, the message having the convergence determination flag is input to the processing at each grid point, so that the convergence determination processing of the processing at the own grid point is started. Since the message with the convergence judgment flag is output when the processing of the own lattice point is converged, the convergence judgment of the entire system can be correctly performed even when the instability point exists.

In this embodiment, the case has been described in which the convergence determination process of the processing of the own lattice point at the lattice point which is the starting point of the end flag is always activated, but the convergence determination process is activated from the host computer. Of course, the same effect can be obtained.

In this type of information processing apparatus, the solution of the differential equation is distributed and stored in the storage means such as the memory allocated to each lattice point. Therefore, it is necessary to accumulate the distributed and stored calculation results, perform visualization processing, and display them on the monitor.

In this embodiment, a method of accumulating the solutions of the differential equations distributed at each lattice point in the host computer will be described.

In the thirty-sixth embodiment, there has been described the method of determining the convergence of whether or not the calculation is completed for the entire system when the convergence calculation is executed on the multiprocessor.
That is, the end flag is sequentially transferred according to a predetermined route, and after making a round through all the lattice points, a message indicating that the entire system has converged is sent to the host computer.
The host computer performs a process for confirming the end of calculation again by receiving the message.

FIG. 56 is a flow chart showing the relationship between the convergence judgment processing at each grid point and the transmission of the solution of the differential equation. The convergence determination procedure and the transmission of the solution of the differential equation will be described with reference to FIG. First, each grid point receives an end flag from an adjacent grid point (step ST20).
Convergence judgment of processing of own lattice point is performed (step ST2
1) After confirming the convergence, an end flag is sent out along a predetermined path (step ST22), and at the same time, the calculation result at the self lattice point, that is, the solution of the differential equation is sent out to the host computer.

Further, FIG. 58 shows a message packet PAC having the solution of the differential equation sent to the host computer.
Shows the format of. The fields of the message packet are the left data field (first operand) pa3,
A right data field (second operand) pa4, a destination PE number pa1 in which an element processor number to which a message packet is to be transferred is stored, and a destination node number pa2 in which an address of an instruction to be executed next is stored. Has been done.

[0384] The left data field, the right data field in the message packet according to this embodiment,
The destination element processor number and destination node number are given as follows. The left data field is the value (function value) at the grid point of the solution of the differential equation. The right data field is the identification number of the grid point. The destination element processor (PE) number is a number assigned to the element processor by the host computer. The destination node number is RESULT. RESULT is a predetermined value and indicates that the message packet stores the calculation result at each lattice point.

When the host computer receives the above message packet, the following operation is performed.

(1) The destination node number field is checked, and since the value is RESULT, it is confirmed that the message packet is the calculation result at each lattice point.

(2) Read out the number of the lattice point stored in the right data field and the solution of the differential equation stored in the left data.

(3) The address is determined from the grid point number by a predetermined method, and the solution value at the grid point is stored in the storage means such as the memory of the host computer.

As described above, in this embodiment, the convergence of the calculation of each grid point is confirmed, and at the same time, the calculation result (the solution of the differential equation) at the own grid point is transferred to the host computer. , The calculation of the whole system converges,
That is, there is an effect that the final result data is prepared on the host computer when it is confirmed that the solution of the differential equation under execution is completed.

In the thirty-sixth embodiment, it is premised that one lattice point process (program) is assigned to one element processor. However, in the thirty-seventh to forty-third embodiments, a plurality of lattice point processes (programs) are allocated. It is premised that the processing program for the grid points is allocated to the same element processor, and the data transfer between the grid points is performed via the data memory in the same element processor. Below, each embodiment will be described in detail.

<Thirty-seventh Embodiment> A thirty-seventh embodiment of the present invention will be described. As another method to detect the instability point (non-convergence point) cycle, transfer the end flag through multiple paths that pass through all grid points to confirm that all grid points have converged. A convergence determination method that can be considered.

Specifically, the convergence determination can be made in multiples by transmitting / receiving the end flags in the two directions of the vertical direction and the horizontal direction to the element processors arranged in a square lattice.

FIG. 59 is a conceptual diagram showing the transfer path of the end flag in this embodiment.

In the figure, 193, 194 and 195
Indicates a square lattice in a two-dimensional space, the solid line arrow indicates the first end flag transfer path 196, and the dotted line arrow indicates the second end flag transfer path 197. In this embodiment, by making the transfer paths of the first and second end flags orthogonal to each other, the circulation at the non-converging point can be detected.

FIG. 60 shows a flowchart for propagating the end flag to each adjacent grid point to the adjacent grid point. However, the processing of the grid points 193 and 195 that are the starting points of the end flags is excluded.

As shown in FIG. 60, first, it is determined whether or not a convergence determination message has arrived from adjacent grid points (step ST30). When a message with an end flag arrives from an adjacent lattice point, the process of determining the convergence of the own lattice point is driven and waits until the process of the own lattice point reaches convergence (step ST31). At the time of convergence, the end flag arrived. Belongs to the first transfer path, or the second
It is determined whether or not it belongs to the transfer route of the above, and the message having the end flag is transferred to the next grid point along the predetermined desired route as shown in FIG. 59 (step ST32).

FIG. 61 shows a flowchart for transmitting the end flag at the lattice point which is the starting point of the end flag transfer. As shown in the figure, first, at the grid point that is the starting point of the end flag, only the convergence of the processing at the own grid point is determined (step ST40), and if it has converged, the first or second convergence message is given. The flag indicating that it belongs to the route is stored (step ST41), and then the message having the end flag is sent to the next grid point along the route as shown in FIG. 59 (step ST42).

At this time, a value corresponding to the type of whether the flag belongs to the first route or the second route is stored in the value of the end flag. Based on this value, the route of the end flag that has arrived can be determined at other grid points.

As described above, since the path for transferring two or more convergence judgment flags is provided, the convergence judgment of the entire system can be correctly executed even when there is an instability point.

In this embodiment, the value of the flag is used to indicate which of the two routes the end flag is transferred to. However, a program that processes the end flag is used. It is obvious that the same effect can be obtained by separately preparing and activating the program for convergence determination for each transfer path of the end flags when each end flag arrives.

<Embodiment 38> Next, the third embodiment of the present invention will be described.
The eight embodiments will be described. A procedure for detecting an instability point in a convergence calculation using a multiprocessor when there is a possibility that the instability point exists will be described.

First, similarly to the thirty-fifth embodiment, the end flag is transferred through all the grid points along a predetermined path, and then transferred to the host computer. Next,
The host computer sends a message for stopping the processing of all the lattice points, and as a result, stops all the processing. After that, by confirming the convergence again, it is possible to detect the circulation of the unstable point and realize the reliable convergence determination.

FIG. 62 is a flow chart showing the processing contents related to the convergence judgment of each lattice point in this embodiment. A process related to the convergence determination of each grid point will be described with reference to FIG. In this embodiment, a memory or a register is used to store the result of the convergence judgment.

In step ST50, it is determined whether a message having an end flag has arrived from an adjacent grid point. When a message having an end flag arrives from an adjacent grid point, the convergence determination processing of the own grid point is driven and waits until the processing of the own grid point reaches convergence (step ST5).
1) At the time of convergence, a message having an end flag is transferred to the next grid point along a predetermined route as shown in FIG. 55, for example (step ST5).
3). At this time, the memory is cleared (step ST
52) And the convergence determination processing program is started (step ST54). The convergence judgment processing program judges whether or not the processing of the self lattice point is in the non-convergence state, and if it is determined to be the non-convergence state, writes a flag indicating that the self lattice point has become the non-convergence state. .

As shown in FIG. 63, the process for determining the convergence at the lattice point which is the starting point of the message having the end flag is basically the message having the end flag in the 36th embodiment. The process is the same as the process of the grid point which is the starting point of, but in addition to this process, the memory is cleared (step ST61), and the convergence determination processing program is started (step ST63). The convergence judgment processing program judges whether or not the processing of the self lattice point is in the non-convergence state, and if it is determined to be the non-convergence state, writes a flag indicating that the self lattice point has become the non-convergence state. .

Thereafter, the message having the end flag is transferred to the host computer. When the host computer receives the message having the end flag, it sends a message for stopping the processing to a predetermined grid point.

The grid point that has received the message for stopping the process stops the process and at the same time transfers the message for stopping the process along a predetermined route to the next adjacent grid point. The grid point that has received the message for stopping the process also performs the same stop process. After the processing of all grid points is stopped, the memory allocated to each grid point is read from the host computer, and if all the read results are zero, the target calculation has converged. Become. If any of the above-mentioned read-out results is different from zero, the above process is repeated.

FIG. 64 shows a flowchart for stopping processing at the grid point. A message for stopping the processing is transmitted from the host computer only to a predetermined grid point. A predetermined grid point determines whether or not a processing stop message has arrived (step ST70). When the processing stop message arrives, the processing is stopped (step ST71). After that, a message for stopping the processing is transferred along a predetermined route (step ST
72). In this embodiment, the case where the message for stopping the processing is transmitted from the host computer only to a predetermined grid point has been described, but this message can be sent to all or a plurality of grid points simultaneously or in time series. The same effect can be obtained even if the data is transmitted manually.

Further, although the case where the processing of the lattice points is stopped by the message is shown in this embodiment, the element processors constituting the multiprocessor system according to the present invention have a mechanism for receiving the interrupt signal. In this case, the same effect can be obtained even if the processing of the lattice points is stopped by interrupting the element processor from the host computer.

In this embodiment, a case has been described in which a memory for storing a flag indicating that a grid point has become a non-convergent state is assigned to each grid point, but one or more memories exist in the system. It is clear that the same effect can be obtained if they do. Further, if the element processors constituting the multiprocessor have a structure having a register, the same effect can be obtained even if the register is used.

<Thirty-ninth Embodiment> Next, the third embodiment of the present invention will be described.
9th Embodiment is described. In the thirty-sixth to thirty-eighth embodiments, a message having a flag indicating that the processing of its own lattice point has reached a converged state is transferred along a predetermined route, and the above message is transmitted to the host computer. It After that, the host computer
The case where the process for detecting the “oscillation phenomenon” described in the sixth embodiment is activated has been described.

However, in rare cases, it is assumed that the convergence state is not reached for a long time depending on the boundary conditions and the like.

A convergence determination method of the information processing apparatus which can cope with the case where the system state is continuously unstable as described above will be described below.

The processing time is measured using a timer on the host computer, a watch dog timer attached to the system, etc., and if the above convergence message is not transferred to the host computer for a certain period of time, processing of each lattice point is performed. The program performs the following processes (1) and (2).

(1) The criterion for the convergence judgment at each grid point is relaxed more than usual.

(2) The message to be transferred is flagged to indicate that it has been judged using the relaxed judgment criteria.

By performing the processes (1) and (2), it is possible to prevent the system from continuously falling into an unstable state.

Next, an embodiment for realizing the processes (1) and (2) will be described based on the 36th embodiment.

FIG. 65 and FIG. 66 are flowcharts of the convergence determination processing at each lattice point necessary to realize the above processing (1) and (2). It should be noted that FIGS.
This corresponds to each of FIGS. 56 and 57 described in the embodiment.

FIG. 65 is a flowchart showing the convergence determination processing at grid points other than the grid point which is the starting point of the flag. As shown in the figure, first, it is determined whether or not a message having an end flag arrives from an adjacent grid point (step ST80). When that message arrives,
It is determined whether or not a flag indicating that the convergence criterion is relaxed is added to the arrived message (step ST81).

If this message is not provided with a flag indicating that the convergence criterion is relaxed, the convergence criterion is determined according to the normal criterion (step ST81), and it is determined whether or not it has converged (step ST83). When converged, a convergence message is sent to the adjacent grid points (step ST8).
4).

After a convergence message is input from an adjacent grid point, if a flag indicating that the judgment criterion is relaxed and the convergence judgment is made is added to this message, the convergence judgment of the own grid point is set in advance. The second reference is used (steps ST85 and ST86), and a flag indicating that the convergence determination has been loosened is added and sent to the next grid point (step ST87).

FIG. 66 is a flow chart showing the convergence determination processing at the grid point which is the starting point of the flag. FIG. 66 shows
When a message instructing to change the convergence criterion is received from the host computer, the convergence criterion is determined using a second criterion that is set in advance, and a flag indicating that the criterion is relaxed is added to the adjacent grid. The procedure for sending a message to a point is shown. It is determined whether or not an instruction message for changing the convergence criterion has arrived from the host computer (step ST90). When the instruction message arrives, the convergence criterion is changed in step ST91. Then, it is determined whether or not the processing of the own lattice point has converged on the basis of the given criteria (step ST92). When the processing of the own lattice point converges with the given reference, it is determined whether or not the convergence determination reference has been changed (step ST
93). If the convergence criterion is not changed, the convergence message is sent to the adjacent grid point as it is (step S
(T95), if the convergence criterion is changed, a flag indicating that the criterion is relaxed is added to the convergence message (step ST94), and the convergence message is sent to the adjacent grid point (step ST95).

It is obvious that the functions for realizing the above (1) and (2) can be added also in the 37th and 38th embodiments as in the 39th embodiment.

<Fortyth Embodiment> Next, a fourth embodiment of the present invention will be described.
An embodiment will be described. The feature of this embodiment lies in a convergence determination method for detecting an unstable point in convergence calculation using a multiprocessor.

In this embodiment, a convergence judgment program (convergence judgment unit) for judging whether or not the calculation of each lattice point has converged, and a register (CREG) or memory for storing the convergence state are provided. CREG can be externally cleared to zero at an arbitrary timing, and 1 is set when it is determined by the convergence determination program that the calculation of the lattice point has not converged.

The convergence determination of the entire system is performed by the following procedure. A corresponding flowchart is shown in FIG.

(1) CREG corresponding to all grid points
The register is cleared to zero (step ST100).

(2) Wait for a sufficient time to complete the processing for one time for all grid points (step ST101).

(3) It is confirmed that the above registers of all grid points are read out and remain 0 (step ST10).
2).

(4) When 1 is read out even at one grid point, the processes of (1) to (3) are repeated. If the values of the above registers at all grid points are all 0, the process ends (step ST103).

In this embodiment, when it is judged by the convergence judgment program that the convergence has not occurred, the CRE
Although 1 is written to the G register, this process may be incorporated in the program from the beginning, or
After the calculation of the lattice points converges, the program may be rewritten to start the convergence determination program and operate the CREG register.

Further, although the case where a register is allocated for each grid point as a storage means for storing the convergence state of the calculation of the grid points has been described in this embodiment, the same effect can be obtained even if a memory is used as the storage means. It is clear that Further, in the present embodiment, the case of allocating a register or a memory element for each grid point has been described, but it is sufficient if there is one or more in the system. Also,
Needless to say, when the convergence determination method according to the present invention is used on a multiprocessor system, it is more effective to allocate one or more of the storage means to each element processor.

As described above, in this embodiment, the system has at least one storage means for storing the fact that the non-convergent state has occurred, and means for clearing all the storage means to zero and the storage of the storage means. Since a means for reading the contents and confirming that all of them are zero is provided, even if there is a non-convergence point, it is possible to judge the convergence of the system without error.

In this embodiment, the processing program for each grid point writes "1" in the register (CREG) when the grid point falls into a non-convergent state. If you add it, CRE will eventually
By reading the value of G, the number of lattice points that have fallen into the non-convergent state can be known. In this way, if each grid point processing program adds 1 to the content of CREG when the grid point falls into a non-convergent state, the convergence judgment standard based on the final CREG value is obtained. By changing or adjusting the roughness of the grid points, the processing time can be shortened.

Needless to say, the inventions of the thirty-first to thirty-ninth embodiments are effective for an ordinary multiprocessor having a plurality of processors.
By using the element processor of the first embodiment or the like in combination with the information processing apparatus capable of independently performing the operation, the element processor can operate independently during the convergence determination, and the accuracy of the solution can be improved.

<Forty-First Embodiment> Next, a fourth embodiment of the present invention will be described.
One embodiment will be described. FIG. 71 is a block diagram showing a network configuration including an input / output control unit and a data memory for performing data communication between adjacent element processors according to the forty-first embodiment of the present invention. In FIG. 71, 3t is an element processor that does not internally have an input / output control unit for communication with the data memory or the data memory, 200 is a data memory arranged on the network, 201 is an element processor 3t and a plurality of data memories. 200, determines the access route to 200, and the element processor 3t
And an input / output control unit for controlling data communication between the data memory 200 and 202, a data bus connecting the element processor 3t and the input / output control unit 201 for data communication,
Reference numeral 203 denotes an inter-element processor connection that connects the element processor 3t and the data memory 200.

The input / output control unit 201 is connected to four data memories 200 here, and each data memory 200 is connected to another input / output control unit connected to an adjacent element processor of the element processor 3t. It However, the data memory 2 connected to the input / output control unit 201
The number of 00s is not limited to four. The number of data memories 200 connected to each input / output control unit 201 is determined according to the state of the neckwork, and the state of the neckwork is determined according to each analysis mode.

The element processor 3t uses the data bus 202.
A memory access request is sent to the input / output control unit 201 via. In the memory access request, communication direction data that describes which data memory 200 to access in the four directions and the address number of the memory space of the designated data memory 200 are described. Input / output control unit 20
1 switches the communication direction according to this access request,
It enables access to the specified data memory 200 in four directions. Then, the data of the address number described in the memory access request passes through the inter-element processor connection 203 and the input / output control unit 201,
It is given to the element processor 3t through the data bus 202. The data given to this element processor 3t is
For example, the data has been written in advance by the adjacent element processor and is equivalent to the data given by direct communication with the adjacent element processor.

Further, when accessing a plurality of data regularly arranged in the memory, the element processor 3t sends the start address and addressing mode to the input / output control unit 201 so that the data can be accessed. Needless to say, continuous access can be realized.

As described above, by arranging the input / output control unit 201 between the data memories 200 to form a network, the input / output control unit 201 is provided in the element processor 3t.
Even when is not implemented, the adjacent element processor can access the data memory 200 in which the data is written at high speed.

In the network configuration shown in FIG. 71, the element processor 3t and the input / output control unit 201 are directly connected via the data bus 202. However, since they are directly connected, the system is configured so that reference / update requests do not collide. It is necessary to build the behavior of. If a reference / update request for the same memory address collides, the processing is interrupted,
This leads to an increase in access time.

The network configuration shown in FIG. 72 has a buffer mechanism for temporarily storing a memory access request issued from the element processor 3t to the input / output control unit 201. In FIG. 72, reference numeral 204 is the data path 20.
71 is a buffer mechanism for temporarily storing a memory access request from the element processor 3t, and the same reference numerals as those in FIG. 71 are portions corresponding to the same reference numerals in FIG.

In the multiprocessor system configured as shown in FIG. 72, one data memory 200 is shared by two element processors 3t adjacent to each other. Two adjacent element processors 3t may access the same memory at the same time. Buffer mechanism 2
Reference numeral 04 temporarily stores a reference / update request for the data memory. The element processor 3t has a buffer mechanism 2
When the reference / update request is stored in 04, the data memory 2
Processing can proceed regardless of data acquisition from 00. As described above, in the multiprocessor system including the buffer mechanism 204, even when a reference / update request for the same memory address collides, it is possible to perform faster memory access without interrupting the processing.

FIG. 73 shows a lattice type network topology optimal for thermo-fluid analysis formed by connecting a plurality of unit units shown in FIG. In the two-dimensional grid type networks described in the eighth to eleventh embodiments, the element processors 3t are arranged at the positions where the grids intersect. As shown in FIG. 73, when the input control unit 201 is outside the element processor 3t, the input / output control unit 201 is arranged at the position where the grids intersect. The input / output control unit 201 includes an element processor 3t
Correspond to each other on a one-to-one basis, and the input / output control unit 201 and the element processor 3t are connected via a data bus 202,
Further, the input / output control unit 201 has four data memories 20.
0 is connected.

As described above, by connecting the respective devices such as the element processor 3t and the data memory 200 centering on the input / output control unit 201, a two-dimensional lattice type network is constructed and the memory access between the adjacent element processors is performed at high speed. Can be executed.

Of course, it is possible to construct a network based on the one-dimensional pipeline topology by using the input / output control unit 201. FIG. 74 is a block diagram showing a part of a network of a multiprocessor system configured in a one-dimensional pipeline topology. In the case of a one-dimensional network, the number of data memories 200 connected to the input / output control unit 201 is two.

By thus constructing the network via the input / output control unit 201, as in the case of the two-dimensional lattice type network, the data memory 20 of the element processor 3t is also used in the one-dimensional pipeline type network.
It goes without saying that access to 0 can be speeded up.

The same arrangement can be applied to the case where the element processors are three-dimensionally arranged. As shown in FIG. 75, in the case of a three-dimensional structure, six data memories 200 are connected to one input / output control unit. For example, in FIG.
A plurality of lattice type network topologies shown in FIG. 3 can be stacked to form a three-dimensional structure. In FIG. 75, the input / output control units 201a and 201b belong to a lattice type network topology arranged on different planes. This 2
The one input / output control unit 201a, 201b shares one data memory 200. In this way, the input / output control unit 2
By connecting the respective devices such as the element processor 3t and the data memory 200 centering on 01a and 201b, a three-dimensional lattice type network can be constructed and memory access between adjacent element processors can be executed at high speed.

Further, although it is applicable to any network, for example, in the lattice type network topology as shown in FIG. 73, data between the distant element processors 3t other than the adjacent element processors 3t is present. Communication is also possible. For example, by providing an area for writing the data of a predetermined element processor in the data memory and copying the area by the input / output control unit 201, each element processor 3t is placed at a position slightly distant from the adjacent element processor 3t. It is also possible to obtain the data of the arranged element processors.

It is also possible to configure the element processor to output a reference / update request to a plurality of input / output control units. When this is applied to the two-dimensional lattice type topology shown in FIG. 73, the configuration shown in FIG. 76 is obtained. As shown in FIG. 76, the element processors 3tc and 3td can output reference / update requests to the input / output control units 201c arranged in all directions. For example, when the element processors 3tc communicate with each other, the reference / update request is output to two adjacent input / output control units 201c sharing one data memory 200. Then, one adjacent element processor 3td can be skipped and the element processors 3tc can communicate with each other. For example, it is possible to selectively use a coarse node connection that performs a calculation using only the element processor 3tc and a fine node connection that performs a calculation using the element processors 3tc and 3td.

Further, the element processor 3t is connected to the input / output control unit 201 arranged in the periphery by the data bus, and not only issues the reference / update request, but also separates it depending on the object of analysis, accuracy, and the like. I / O connection section 20 of the place
It goes without saying that it may be connected to 1 via a data bus.

<Forty-Second Embodiment> Next, a fourth embodiment of the present invention will be described.
Two embodiments will be described. In the thirtieth to thirty-fourth embodiments, each element processor 3k, 3m, 3p, 3
The convergence determination flag (1 or 0) output by q is logically multiplied one after another by a logic circuit implemented in the convergence determination unit 180 or the convergence determination unit 183, and finally the host computer 1 as convergence determination information. I was transferring. By the way, in a multiprocessor system,
When the number of connected element processors is as small as several tens, the logical structure of the convergence judgment bits cannot be obtained sufficiently fast even with the configurations shown in the thirtieth to thirty-fourth embodiments. It is possible. However, in the case of a large-scale multiprocessor system having hundreds of element processors, until the logical product of all the convergence determination units 180 and the convergence determination unit 183 ends and the convergence determination result is transferred to the host computer 1. The total time of will be enormous.

FIG. 77 is a conceptual diagram showing the outline of a convergence determining apparatus according to the 42nd embodiment of the present invention. In FIG. 77, 3 is an element processor, 205 is a convergence determination bit register for temporarily storing a convergence determination bit, 206
Is the element processor 3 and the convergence determination bit register 205
Convergence determination bit line for transmitting the convergence determination bit output from the element processor 3 by connecting and, 208 is a convergence information signal line for transmitting the convergence information to the host computer, and 209 is fixed to the ground potential V _SS . N-type MOS transistor having a source connected to the ground potential point 207, a gate connected to the convergence determination bit register 205, and a drain connected to the convergence information signal line 208,
Reference numeral 210 is a resistor having one end connected to the power supply potential point 211 and the other end connected to the converged information signal line 208. The convergence determination device is a wired O that is an analog circuit.
It is configured using R. Wired OR is N type M
OS transistor, convergence information signal line 208, and resistor 210
Composed of and.

At least one bit of the convergence judgment bit output from each element processor 3 is temporarily stored in the convergence judgment bit register 8 via the convergence judgment bit line 7. The convergence judgment bits stored in the convergence judgment bit register 8 are logically ANDed by a wired OR and reflected on the convergence judgment result of at least 1 bit output to the convergence information signal line 12.

Now, when the convergence determination bit output from each element processor 3 is "0", it is defined as converged, and when it is "1", it is defined as an unconverged state. When all the element processors 3 output “0” as the convergence determination bit, that is, the convergence state, all the N-channel MOS transistors 209 are in the non-conduction state, and the convergence information signal line 208 receives the power supply potential via the resistor 210. V _DD is output, and the host computer can recognize that the entire system has converged.

When at least one of the element processors 3 outputs "1" (that is, the non-convergence state) as the convergence determination bit, the corresponding N-type MOS transistor 209 is in the conductive state, and the resistance is By setting the resistance value of 210 to be sufficiently larger than the resistance value of the N-type MOS transistor 209 at the time of conduction, the convergence information signal line 2
A potential that can be digitally regarded as the ground potential V _SS is output to 08. Since the convergence information signal line 208 is at a potential that can be regarded as the ground potential V _SS , the host computer 1 can recognize that the entire system has not yet converged.

In this embodiment, the logical value of the convergence determination bit output from each element processor 3 is "1".
Is defined as converging, and "0" as non-converging, and the N-type MOS transistor is defined as a P-type MO.
It goes without saying that a circuit that performs the same operation can be configured by changing to an S transistor.

By configuring the convergence determination device as described above, it becomes possible to continuously obtain the logical value of the convergence determination bit stored in the total convergence determination register 205 in a short time of about several microseconds. The convergence determination time can be shortened while performing the convergence determination independently of the arithmetic processing.

<Embodiment 43> Next, a fourth embodiment of the present invention will be described.
The third embodiment will be described. In the parallel method of thermofluid numerical analysis by the area division method, the calculation area is divided into at least the same number of divided areas as the element processors 3, and each element processor 3 is responsible for the calculation of each area. As is generally done, when the communication method between the element processors 3 is a message passing type low-speed remote access, the lattice points assigned to the element processors 3 are substantially the same due to the difference in the processing amount of the element processors 3. This can be dealt with to some extent by making the calculation addition uniform, but when an unstable point exists in the divided area, more iterative calculations are required until a convergent solution is obtained, which causes the element processor 3 to The throughput increases. Therefore, the above problem is solved by configuring a multiprocessor system by an asynchronous communication system that completely eliminates the latency due to communication synchronization wait and changing the number of lattice points to be mounted for each element processor 3.

FIG. 78 shows the division form of the calculation area including the analysis instability point. In FIG. 78, 213 is the total calculation area used for analysis, 214 is each element processor 3
Are divided areas, 215 are normal grid points,
Reference numeral 216 is an analysis instability point in which there are unstable factors such as a physical quantity changing with time. Factors that make the analysis unstable are, for example, points with rapid velocity changes or temperature changes, points in vortices, points at which physical quantities fluctuate unsteadily, points near moving objects or boundaries, points in swirling flow, and angles. These are singular points, etc., heat generation points, inflow / outflow points of fluids, etc., and points in the vicinity thereof.

Next, the operation will be described. The element processor 3 in charge of the divided area 14 including the analysis unstable point 216
Then, the instability of the analysis instability point 216 is due to the divided region 214.
The number of iterations is increased until it reaches all the lattice points in and obtains a spatially convergent solution. Therefore, as shown in the figure, the number of grid points in the divided area including the analysis unstable point 216 is made smaller than the number of grid points in the divided area 214 not including the other analysis unstable points 216. Then, the increase in the processing amount due to the increase in the number of repetitions can be offset by reducing the number of grid points. Furthermore, by performing the asynchronous communication method, it is possible to cause the calculation of the divided area 214 including the analysis instability point 216 to precede the stable divided area 214. As described above, by using the asynchronous communication method and the unequal distribution of grid points together, the convergence operation can be speeded up even when the calculation area includes an unstable area.

<Embodiment 44> Next, a fourth embodiment of the present invention will be described.
Four embodiments will be described. Most of the arithmetic circuits used in the element processor 3 described in the first to fifth embodiments have a synchronization system based on a clock provided in the element processor 3. This is because with the current technical strength, the relationship of reaction time (element delay) of elements in the circuit> delay (wiring delay) associated with information transmission in the chip is established.

However, in recent years, ultra-high-speed element technology has been rapidly advanced, and it is possible to operate with an element delay of 10 ps for silicon semiconductor elements, 5 ps for compound semiconductor elements, and 1 ps level for Josephson elements. Further, with the progress of VLSI technology, the chip size has been expanded to 15 mm × 15 mm, and the number of mountable elements is about to reach 3 million in logic LSI. If such a picosecond LSI is realized, the time (element delay) until the processing result is output in response to the input to the element is reduced, whereas in the chip which has not been a problem until now, The time taken for information to pass through the wiring (wiring delay) cannot be ignored. If the chip is composed of elements having an element delay of 1 picosecond, the operation of the entire chip with a single clock can be guaranteed only up to a chip area of 0.3 mm × 0.3 mm. Therefore, it is possible to significantly improve the processing capability of the element processor by designing a circuit based on an in-processor asynchronous system that does not synchronize the operation in the chip with a clock. Furthermore, in the asynchronous system design, advantages such as (1) to (3) described later can be cited, and the robustness and high speed of the element processor 3 can be improved, and in turn, it is possible to speed up the thermofluid analysis. According to the causal relation of signal transition, normal operation is possible regardless of the size of element delay, and high speed can be achieved. Timing fluctuations are eliminated even with external disturbances such as voltage fluctuations and temperature environment changes of the information processing apparatus, and high reliability can be achieved. Timing adjustment is not required and design becomes easy. Electric power for clock generation becomes unnecessary, and an information processing device with low power consumption can be obtained.

The asynchronous circuit having such characteristics can be used as a circuit in the element processor 3. Therefore, the basic configuration of the asynchronous circuit will be described below.
An asynchronous system is a group of functional modules composed of asynchronous circuits that exchange signals with each other. When a processing request is issued from the functional module A to the functional module B, a request signal "request" indicating a processing request from the module A to the module B and a "response" indicating a processing end notification from the module B to the module A By passing the two response signals, the operation for one processing request between the functional modules A and B is completed. However, in the asynchronous system, since there is no synchronous clock, it is necessary to devise to notify the arrival timing of these request signal and response signal. First, regarding the control signal, if "valid" is defined as "1" and "invalid" is defined as "0", the transition itself of 0 → 1 or 1 → 0 represents the timing of request or response. The problem arises when the signals to be exchanged are data signals. Normally, the data signal is a one-line type and can be expressed only in binary, so the timing of request / response cannot be described. Therefore, for exchanging a data signal between a plurality of functional modules configured by asynchronous circuits, for example, 2-wire type data that expresses 1-bit information with two signal lines is used. The 2-wire data representation includes a 2-wire 2-phase method, a 2-wire transition method, a parity alternation method, etc. Among them, the 2-wire 2-phase method has high versatility and can be simplified in circuit configuration. The case of using the data signal representation of the line two-phase method will be described.

In the 2-line 2-phase data representation, the 1-bit data D is represented by a 2-line signal (d1, d0) as shown in Formula 40.

[0467]

[Formula 40]

For example, to transfer "1", the idle phase (0,0) is changed to (1,0), and after the processing is completed, the spacer state (0,0) is reset to prepare for the next data transfer. Performs a series of operations.

Next, consider the data transfer path based on this 2-wire 2-phase data representation. FIG. 79 is a block diagram showing an inter-register data transfer path model based on the two-wire two-phase data representation. In FIG. 79, 217 is a control signal bus for transferring control signals, 218 is a two-wire two-phase control module for resetting the two-wire type signals after request / response processing is completed, and 219 is for temporarily storing the signals. , 220 is a two-wire type logic circuit, and 221 is a two-line type data bus. However, the two-wire type logic circuit 220 in the drawing is composed of basic logic elements configured based on the two-wire type logic.

Upon receiving the processing end information from the upper layer, the two-wire two-phase control module 218 issues a request (0 → 1 transition). In response to this request, the 2-wire data signal is read from the transfer source register 219. The data read from the transfer source register 219 is given to the two-wire logic circuit 220 via the two-wire data bus 221, and processed by the two-wire logic circuit 220. Further, the data processed by the 2-wire type logic circuit 220 is written to the transfer destination register 219 through the 2-wire type data bus 221. After that, 2 lines 2 which received the response (0 → 1 transition) generated in the register 219
The phase control module 218 transfers the processing end information to the lower order. Following the processing end information from the upper layer, a request disappearance command (1 → 0) is transferred from the upper layer in order to reset the data, and all two lines from the transfer source register 219 to the transfer destination register 219 via the logic circuit 220 are transferred. The signal transits to the spacer state, and finally the response disappears (1 → 0 transition)
Let it finish.

The 2-wire type logic circuit 220 shown in FIG.
A circuit having any configuration may be used as long as it is a circuit configured by connecting basic logic elements such as a two-wire AND gate, an OR gate, and a NOT gate. For example, even if the wiring delay becomes larger than the element delay by implementing the entire processing unit 5 according to any of the first to fifth embodiments with the two-wire logic circuit 220, the element The arithmetic processing in the processor 3 can be realized at high speed.

Of course, it is also possible to apply asynchronous processing not using a clock only to a specific operation sequence, and it goes without saying that the same effect can be obtained in this case as well.

Further, it is also possible to use the above embodiments in combination.

[0474]

As described above, according to the information processing apparatus of the first aspect of the present invention, the information processing apparatus that allocates a plurality of grid points obtained by spatially dividing the field to the element processor to perform the calculation. In, a plurality of data buses for communicating data between adjacent element processors are provided,
The data transmitted by the data bus is used to operate the element processors asynchronously and independently to perform the calculation, so that the communication time between the element processors can be shortened and the processing speed of the information processing device can be increased. The effect is that it can be achieved.

According to the information processing apparatus of the first aspect of the present invention, since the data communication between the adjacent element processors is performed asynchronously and repeatedly for each element processor, the processing of the adjacent element processors is hindered. Processing can be continued completely asynchronously without any interruption, and communication can be performed without hindering the operation of the adjacent element processor, which has the effect of speeding up the operation.

Further, according to the information processing apparatus of the present invention, each of the element processors can directly refer to the data memory of the adjacent element processor, so that the processing units of the adjacent element processors can be easily connected. Data communication can be performed asynchronously and repeatedly for each processing unit, and there is an effect that speedup of the information processing device can be easily realized.

Furthermore, according to the information processing apparatus of the present invention, the processing of the data flow graph can be changed according to the inside point bit, the outside point bit and the boundary condition bit. Since the hardware circuit is provided, the calculation can be performed by the hardware circuit according to the same wiring logic regardless of the type of grid point, and the calculation program can be simplified and the scale of the information processing device can be reduced. There is.

According to the information processing apparatus of the second aspect of the present invention, in an information processing apparatus for assigning a plurality of grid points obtained by spatially dividing a field to element processors to perform calculation, adjacent element processors Since a plurality of data buses for communicating data between each other are provided and the data transmitted by the data buses are used to operate the element processors asynchronously and independently, the calculation is performed. There is an effect that the time can be shortened and the processing speed of the information processing apparatus can be increased.

According to the information processing apparatus of the second aspect of the present invention, since the data communication between the adjacent element processors is performed asynchronously and repeatedly for each element processor, the processing of the adjacent element processors is hindered. Processing can be continued completely asynchronously without any interruption, and communication can be performed without hindering the operation of the adjacent element processor, which has the effect of speeding up the operation.

Further, according to the information processing apparatus of the second aspect of the present invention, each of the element processors can directly refer to the data memory of the adjacent element processor, so that the processing units of the adjacent element processors can be easily connected. Data communication can be performed asynchronously and repeatedly for each processing unit, and there is an effect that speedup of the information processing device can be easily realized.

Furthermore, according to the information processing apparatus of the invention described in claim 2, the equations are calculated by performing the calculation by the element processors connected by the coarse node connection and the calculation by the element processors connected by the fine node connection. As the calculation progresses, it is possible to improve the convergence by the calculation using the element processors connected by the coarse node connection and maintain the accuracy of the calculation by the calculation using the element processors connected by the fine node connection. The effect is that high processing can be performed at high speed.

According to the calculation method of the information processing apparatus of the third aspect of the present invention, in the information processing apparatus that allocates a plurality of grid points obtained by spatially dividing a field to element processors to perform calculation, Equipped with multiple data buses to communicate data between the element processors
The data transmitted by the data bus is used to operate the element processors asynchronously and independently to perform the calculation, so that the communication time between the element processors can be shortened and the processing speed of the information processing device can be increased. The effect is that it can be achieved.

According to the calculation method of the information processing apparatus of the third aspect of the invention, since the data communication between the adjacent element processors is performed asynchronously and repeatedly for each element processor, the processing of the adjacent element processors is performed. It is possible to continue the processing completely asynchronously without hindering the processing, and it is possible to communicate without hindering the processing of the adjacent element processors, which has the effect of speeding up the processing.

Further, according to the calculation method in the information processing apparatus of the third aspect of the invention, since the solution of the differential equation is obtained by operating the element processors asynchronously and independently and using the difference method, the accuracy of the analysis can be improved. There is an effect that the processing speed of the information processing apparatus can be increased without dropping the value.

According to the calculation method of the information processing apparatus of the fourth aspect of the present invention, in the information processing apparatus that allocates a plurality of grid points obtained by spatially dividing a field to element processors to perform calculation, Equipped with multiple data buses to communicate data between the element processors
The data transmitted by the data bus is used to operate the element processors asynchronously and independently to perform the calculation, so that the communication time between the element processors can be shortened and the processing speed of the information processing device can be increased. The effect is that it can be achieved.

According to the calculation method in the information processing apparatus of the present invention, the data communication between the adjacent element processors is performed asynchronously and repeatedly for each element processor. It is possible to continue the processing completely asynchronously without hindering the processing, and it is possible to communicate without hindering the processing of the adjacent element processors, which has the effect of speeding up the processing.

Further, according to the calculation method in the information processing apparatus of the present invention, each element processor can directly refer to the data memory of the adjacent element processor, so that the processing of the adjacent element processor can be easily performed. Data communication between units can be performed asynchronously and repeatedly for each processing unit, and there is an effect that the speedup of the information processing device can be easily realized.

Furthermore, according to the calculation method in the information processing apparatus of the present invention, the same calculation program whose processing can be changed by the internal point bit, the external point bit, and the boundary condition bit in the element processors. Since the processing unit performs the calculation by using, it is possible to perform the calculation by using the same calculation program regardless of the type of lattice points, and it is possible to simplify the calculation program and reduce the scale of the information processing device. effective.

According to the calculation method of the information processing apparatus of the fifth aspect of the present invention, in the information processing apparatus that allocates a plurality of grid points obtained by spatially dividing a field to element processors to perform calculation, Equipped with multiple data buses to communicate data between the element processors
The data transmitted by the data bus is used to operate the element processors asynchronously and independently to perform the calculation, so that the communication time between the element processors can be shortened and the processing speed of the information processing device can be increased. The effect is that it can be achieved.

According to the calculation method in the information processing apparatus of the fifth aspect, since the data communication between the adjacent element processors is performed asynchronously and repeatedly for each element processor, the processing of the adjacent element processors is performed. It is possible to continue the processing completely asynchronously without hindering the processing, and it is possible to communicate without hindering the processing of the adjacent element processors, which has the effect of speeding up the processing.

Furthermore, according to the calculation method in the information processing apparatus of the fifth aspect, since each element processor can directly refer to the data memory of the adjacent element processor, the processing of the adjacent element processor can be easily performed. Data communication between units can be performed asynchronously and repeatedly for each processing unit, and there is an effect that the speedup of the information processing device can be easily realized.

Furthermore, according to the calculation method in the information processing apparatus of the fifth aspect of the present invention, the same wiring that can change the processing of the data flow graph according to the interior point bit, the exterior point bit and the boundary condition bit. Since the hardware circuit according to the logic is provided, calculation can be performed by the hardware circuit according to the same wiring logic regardless of the type of grid point, and the calculation program can be simplified and the scale of the information processing device can be reduced. The effect is that you can do it.

According to the calculation method in the information processing apparatus of the sixth aspect of the present invention, in the information processing apparatus that allocates a plurality of grid points obtained by spatially dividing the field to the element processor to perform the calculation, Equipped with multiple data buses to communicate data between the element processors
The data transmitted by the data bus is used to operate the element processors asynchronously and independently to perform the calculation, so that the communication time between the element processors can be shortened and the processing speed of the information processing device can be increased. The effect is that it can be achieved.

Further, according to the calculation method in the information processing apparatus of the present invention, the data communication between the adjacent element processors is performed asynchronously and repeatedly for each element processor. It is possible to continue the processing completely asynchronously without hindering the processing, and it is possible to communicate without hindering the processing of the adjacent element processors, which has the effect of speeding up the processing.

Further, according to the calculation method in the information processing apparatus of the present invention, each element processor can directly refer to the data memory of the adjacent element processor, so that the processing of the adjacent element processor can be easily performed. Data communication between units can be performed asynchronously and repeatedly for each processing unit, and there is an effect that the speedup of the information processing device can be easily realized.

Furthermore, according to the calculation method in the information processing apparatus of the present invention, the number of communications at all grid points is leveled, so that it is possible to improve efficiency when parallelized. effective.

According to the calculation method of the information processing apparatus of the invention described in claim 7, in the information processing apparatus for assigning a plurality of grid points obtained by spatially dividing a field to element processors to perform calculation, Equipped with multiple data buses to communicate data between the element processors
The data transmitted by the data bus is used to operate the element processors asynchronously and independently to perform the calculation, so that the communication time between the element processors can be shortened and the processing speed of the information processing device can be increased. The effect is that it can be achieved.

According to the calculation method of the information processing apparatus of the present invention, data communication between adjacent element processors is performed asynchronously and repeatedly for each element processor. It is possible to continue the processing completely asynchronously without hindering the processing, and it is possible to communicate without hindering the processing of the adjacent element processors, which has the effect of speeding up the processing.

Furthermore, according to the calculation method in the information processing apparatus of the present invention, each element processor can directly refer to the data memory of the adjacent element processor, so that the processing of the adjacent element processor can be easily performed. Data communication between units can be performed asynchronously and repeatedly for each processing unit, and there is an effect that the speedup of the information processing device can be easily realized.

Furthermore, according to the calculation method in the information processing apparatus of the present invention, the number of calculations at all grid points is leveled by performing dummy calculation even for grid points having a small calculation amount. Therefore, there is an effect that efficiency can be improved when parallelized.

According to the calculation method of the information processing apparatus of the eighth aspect, in the information processing apparatus that allocates a plurality of grid points obtained by spatially dividing the field to the element processors to perform the calculation, Equipped with multiple data buses to communicate data between the element processors
The data transmitted by the data bus is used to operate the element processors asynchronously and independently to perform the calculation, so that the communication time between the element processors can be shortened and the processing speed of the information processing device can be increased. The effect is that it can be achieved.

According to the calculation method in the information processing apparatus of the present invention, the data communication between the adjacent element processors is performed asynchronously and repeatedly for each element processor. It is possible to continue the processing completely asynchronously without hindering the processing, and it is possible to communicate without hindering the processing of the adjacent element processors, which has the effect of speeding up the processing.

Further, according to the calculation method in the information processing apparatus of the present invention, each element processor can directly refer to the data memory of the adjacent element processor, so that the processing of the adjacent element processor can be easily performed. Data communication between units can be performed asynchronously and repeatedly for each processing unit, and there is an effect that the speedup of the information processing device can be easily realized.

Furthermore, according to the calculation method in the information processing apparatus of the present invention, the data transmitted from each other in the two element processors are time-sequentially converted into two.
If the data for these grid points are updated, if the updated data is a displacement below the specified value compared with the data of the previous set in time series, the data of the other party will not be rewritten. There is an effect that unnecessary communication between the processors can be omitted and the processing speed of the information processing apparatus can be increased.

According to the calculation method of the information processing apparatus of the ninth aspect of the invention, in the information processing apparatus for assigning a plurality of grid points obtained by spatially dividing the field to the element processors to perform the calculation, Equipped with multiple data buses to communicate data between the element processors
The data transmitted by the data bus is used to operate the element processors asynchronously and independently to perform the calculation, so that the communication time between the element processors can be shortened and the processing speed of the information processing device can be increased. The effect is that it can be achieved.

According to the calculation method in the information processing apparatus of the present invention, the data communication between the adjacent element processors is performed asynchronously and repeatedly for each element processor. It is possible to continue the processing completely asynchronously without hindering the processing, and it is possible to communicate without hindering the processing of the adjacent element processors, which has the effect of speeding up the processing.

Further, according to the calculation method in the information processing apparatus of the present invention, each element processor can directly refer to the data memory of the adjacent element processor, so that the processing of the adjacent element processor can be easily performed. Data communication between units can be performed asynchronously and repeatedly for each processing unit, and there is an effect that the speedup of the information processing device can be easily realized.

Further, according to the calculation method in the information processing apparatus of the present invention, the calculation by the element processors connected by the coarse node connection and the calculation by the element processors connected by the fine node connection are performed. Since the calculation of the equation is advanced, it is possible to improve the convergence by the calculation using the element processors connected by the coarse node connection and maintain the accuracy of the calculation by the calculation using the element processors connected by the fine node connection. Therefore, there is an effect that highly accurate processing can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a hardware configuration of an element processor according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a hardware configuration of an element processor according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a hardware configuration of an element processor according to a fourth embodiment of the present invention.

FIG. 5 is a data graph showing a basic flow of arithmetic processing.

FIG. 6 is a block diagram showing a configuration of an information processing apparatus for performing three-dimensional calculation by connecting two-dimensional calculation boards in a three-dimensional manner according to a fifth embodiment of the present invention.

FIG. 7 is a flowchart showing a calculation algorithm by an asynchronous calculation method according to a sixth embodiment of the present invention.

FIG. 8 is a conceptual diagram for explaining a control volume based on the difference method.

FIG. 9 is a diagram showing a structure of data handled in a data memory.

FIG. 10 is a flowchart showing a calculation procedure of a calculation algorithm based on an asynchronous calculation method.

FIG. 11 is a flowchart showing a calculation procedure of a calculation algorithm by an asynchronous calculation method.

FIG. 12 is a block diagram showing a configuration of a two-dimensional substrate for performing pipeline processing in the time axis direction according to the seventh embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of an information processing device according to an eighth embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of an element processor constituting an information processing device according to an eighth embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of an information processing device according to a ninth embodiment of the present invention.

FIG. 16 is a block diagram showing a configuration of an element processor for realizing an information processing device according to a ninth embodiment of the present invention.

FIG. 17 is a block diagram showing a configuration of an information processing device according to a tenth embodiment of the present invention.

FIG. 18 is a block diagram showing a configuration of an element processor for realizing an information processing device according to a tenth embodiment of the present invention.

FIG. 19 is a block diagram showing a structure of a memory for realizing an information processing device according to a tenth embodiment of the present invention.

FIG. 20 is a block diagram showing the structure of an element processor according to an eleventh embodiment of the present invention.

FIG. 21 is a block diagram showing the structure of an element processor according to a twelfth embodiment of the present invention.

FIG. 22 is a system flowchart for explaining the configuration of a processor unit according to the thirteenth embodiment of the present invention.

FIG. 23 is a block diagram illustrating a configuration of an information processing device according to a fourteenth embodiment of the present invention.

FIG. 24 is a block diagram showing a configuration of an element processor for realizing an information processing device according to a fifteenth embodiment of the present invention.

FIG. 25 is a block diagram showing the structure of an information processing apparatus according to a sixteenth embodiment of the present invention.

FIG. 26 is a block diagram showing the structure of an information processing apparatus according to the seventeenth embodiment of the present invention.

FIG. 27 is a block diagram showing a configuration of an element processor for realizing the information processing device according to the sixteenth and seventeenth embodiments.

FIG. 28 is a conceptual diagram showing the structure of the information processing apparatus according to the eighteenth embodiment of the present invention.

FIG. 29 is a conceptual diagram showing the structure of the information processing apparatus according to the nineteenth embodiment of the present invention.

FIG. 30 is a block diagram showing the structure of an information processing device according to a twentieth embodiment of the present invention.

FIG. 31 is a plan view showing the state of grid points for explaining the information processing apparatus according to the twenty-first embodiment of the present invention.

FIG. 32 is a diagram showing allocation of program memories for explaining the information processing apparatus according to the 22nd embodiment of the present invention.

FIG. 33 is a diagram showing allocation of program memories for explaining an information processing device of a dynamic data flow system according to a 23rd embodiment of the present invention.

FIG. 34 is a conceptual diagram showing an example of a color acquisition function for obtaining a different data memory address for each color identifier in the twenty-third embodiment.

FIG. 35 is a conceptual diagram showing an example of color identifier allocation of lattice points for realizing a color acquisition function.

FIG. 36 is a diagram showing an example of a configuration of a data memory for realizing a color acquisition function.

FIG. 37 is a diagram showing the structure of a data memory for realizing the information processing apparatus according to the twenty-fourth embodiment of the present invention.

FIG. 38 is a flowchart showing the procedure of inter-grid communication according to the twenty-fourth embodiment.

FIG. 39 is a diagram showing a structure of a data memory for realizing an information processing device according to a twenty-fifth embodiment of the present invention.

FIG. 40 is a flowchart showing the inter-grid communication procedure according to the twenty-fifth embodiment.

FIG. 41 is a conceptual diagram of a calculation area showing a memory area in each direction to communicate for each grid point.

FIG. 42 is a diagram for explaining communication between element processors according to the twenty-fifth embodiment.

FIG. 43 is a diagram showing a structure of a data memory for realizing sharing of a dummy communication data area according to a twenty sixth embodiment of the present invention.

FIG. 44 is a flowchart of a processing flow for realizing sharing of a data area for dummy communication.

FIG. 45 is a conceptual diagram for explaining a communication format between element processors according to the 27th embodiment of the present invention.

FIG. 46 is a layout diagram of grid points for explaining the simplification of the program according to the twenty-eighth embodiment of the present invention.

FIG. 47 is a diagram showing the relationship of lattice points for explaining the operation of the information processing apparatus according to the twenty ninth embodiment of the present invention.

FIG. 48 is a block diagram showing the structure of the information processing apparatus according to the 31st embodiment of the present invention.

FIG. 49 is a block diagram showing the structure of the information processing apparatus according to the 32nd embodiment of the present invention.

FIG. 50 is a block diagram showing the structure of an element processor for realizing the information processing apparatus according to the 33rd embodiment of the present invention.

FIG. 51 is a block diagram showing the structure of the information processing apparatus according to the 33rd embodiment of the present invention.

FIG. 52 is a block diagram showing the structure of the information processing apparatus according to the 34th embodiment of the present invention.

FIG. 53 is a block diagram showing the structure of an element processor for realizing the information processing device according to the 35th embodiment of the present invention.

FIG. 54 is a block diagram showing the structure of the information processing apparatus according to the 35th embodiment of the present invention.

FIG. 55 is a conceptual diagram showing the transfer path of the end flag for explaining the operation of the information processing apparatus according to the 36th embodiment of the present invention.

FIG. 56 is a flowchart for explaining a procedure for propagating an end flag to an adjacent grid point in the information processing apparatus according to the 36th embodiment.

FIG. 57 is a flowchart for explaining a procedure for propagating an end flag to an adjacent grid point in the information processing apparatus according to the 36th embodiment.

FIG. 58 is a diagram showing the structure of a message packet used for outputting result data according to the thirty-sixth embodiment.

FIG. 59 is a conceptual diagram showing a transfer path of an end flag for explaining the operation of the information processing apparatus according to the 37th embodiment of the present invention.

FIG. 60 is a flowchart for explaining a procedure for transmitting an end flag to an adjacent grid point in an information processing device according to a thirty-seventh embodiment of the present invention.

FIG. 61 is a flowchart showing the procedure for transmitting the end flag of the element processor which is the starting point of the end flag transfer of the information processing apparatus according to the 37th embodiment of the present invention.

FIG. 62 is a flowchart for explaining a procedure for propagating an end flag to an adjacent grid point in an information processing apparatus according to the 38th embodiment of the present invention.

FIG. 63 is a flow chart showing the procedure for transmitting the end flag of the element processor which is the starting point of the end flag transfer of the information processing apparatus according to the thirty-eighth embodiment of the present invention.

FIG. 64 is a flowchart showing the procedure of processing arbitration at lattice points in an information processing apparatus according to the 38th embodiment of the present invention.

FIG. 65 is a flowchart for explaining a procedure of propagating an end flag to an adjacent grid point in the information processing apparatus according to the 39th embodiment.

FIG. 66 is a flowchart for explaining a procedure for transmitting an end flag to an adjacent grid point in the information processing apparatus according to the 39th embodiment.

FIG. 67 is a flow chart showing the procedure of convergence determination of the information processing device according to the fortieth embodiment of the present invention.

FIG. 68 is a block diagram showing a configuration of a system for solving a differential equation using a conventional multiprocessor.

FIG. 69 is a graph showing parallelization efficiency when a conventional partial differential equation solving method is used.

FIG. 70 is a flowchart showing a calculation procedure of a fluid numerical analysis by the SIMPLE method.

71 is a block diagram illustrating a unit of a network including an input / output control unit and a data memory according to the 41st embodiment of the present invention. FIG.

72 is a block diagram for explaining another unit of the network configured of the input / output control unit and the data memory according to the 41st embodiment of the present invention. FIG.

FIG. 73 is a block diagram for explaining a first network configuration including an input / output control unit and a data memory according to the 41st embodiment of the present invention.

FIG. 74 is a block diagram for explaining a second network including an input / output control unit and a data memory according to the 41st embodiment of the present invention.

FIG. 75 is a block diagram illustrating a third network configuration including an input / output control unit and a data memory according to the 41st embodiment of the present invention.

FIG. 76 is a block diagram illustrating a fourth network configuration including an input / output control unit and a data memory according to the 41st embodiment of the present invention.

FIG. 77 is a conceptual diagram showing an outline of the configuration of a convergence determination device according to a forty-second embodiment of the present invention.

FIG. 78 is a conceptual diagram showing a division form of a calculation region including an analysis instability point according to the 43rd embodiment of the present invention.

FIG. 79 is a block diagram showing an inter-register data transfer path model according to the 44th embodiment of the present invention.

[Explanation of symbols]

1 host computer, 2 information processing device, 3, 3a
3t element processor, 4 network, 5 processing unit, 6 memory unit, 7,203 element processor connection, 8,200 data memory, 9 processor data bus, 10 floating point computer, 11 program memory, 12 function module, 13 Data flow graph, 14 calculator, 15
Data line, 16 operation nodes, 17 arcs, 18 2
Dimensional calculation board, 20 Routines for solving Navier-Stokes equation of motion, 21 Routines for solving pressure correction formulas, 22 Routines for correcting velocity / pressure, 23 Iterative cycles for convergence of non-linearity, 24 hours progress Calculation cycle, 25 element processors assigned to each grid point, 26 control volume, 27
Lattice point (P), 28 Adjacent lattice point (E), 29 Adjacent lattice point (W), 30 Adjacent lattice point (N), 31 Adjacent lattice point (S), 32 Partition for one lattice point, 65
Two-dimensional calculation board for time n-1, 66 two-dimensional calculation board for time n, 67 two-dimensional calculation board for time n + 1, 71, 2
01 Input / output control unit, 76 memory, 73, 75, 9
0,202 data bus, 76a multi-port memory,
79 2-port memory, 80,204 buffer mechanism,
83 Matching Memory, 84 Pipeline, 85
Multiplier, 86,87 adder, 88,89 data line,
91 I / O unit, 92 output data bus, 93 output I / O unit, 94 output data bus, 95 data output controller, 96 serial data bus, 97 post processing unit, 98 image output data bus, 99 display, 101 Network, 104 row direction calculation information bus, 105 column direction calculation information bus, 106 internal calculation information bus, 107 output information processing unit, 108 output information bus, 109 output processing information bus, 120 coordinate conversion unit, 125 grid points on boundary , 126 internal grid points, 137 virtual grid points, 180 convergence determination unit, 181 convergence flag information bus, 182 convergence information bus, 183 convergence determination unit, 184 internal information flag bus, 185 internal calculation information bus, 186 end information bus, 205 Convergence judgment bit register, 206 Convergence judgment Tsu DOO line, 208 convergence information signal lines, 209N-channel MOS transistor 210 resistor.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hirono Tsubota 2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (72) 2-3-2 Marunouchi Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Co., Ltd. (72) Inventor Shinji Nakajima 2-3-3 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Co., Ltd. (72) Inventor Kosuke Terada 3-52, Yamada Nishi, Suita City, Osaka Senri Ichijo Ike B −803 (72) Inventor Makoto Iwata 3-16 Hiyoshidai Ichibancho, Takatsuki City, Osaka Prefecture (72) Inventor Katsuto Yamaguchi 22-14 Uenomachi, Nishinomiya City, Hyogo Prefecture (72) Inventor Junji Onishi Suita City, Osaka Prefecture Yamada Nishi 3-52 A202 (72) Inventor Akira Kondo 3-1-12 Hagiwara, Kawanishi-shi, Hyogo (56) Reference JP-A-5-324589 (JP, A) JP-A-5-233556 (JP, A) JP-A-2-195472 (J , A) JP 5-276181 (JP, A) JP 4-40525 (JP, A) JP 3-241452 (JP, A) JP 5-181895 (JP, A) JP 4-281582 (JP, A) JP 4-289954 (JP, A) JP 5-298398 (JP, A) JP 4-338873 (JP, A) JP 4-281549 (JP, A) JP-A-3-102561 (JP, A) JP-A-1-253059 (JP, A) JP-A-61-118859 (JP, A) JP-A-63-192153 (JP, A) JP-A-61 -256466 (JP, A) JP 63-95568 (JP, A) JP 58-146952 (JP, A) JP 61-120253 (JP, A) JP 60-173636 (JP, A) ) Tokushu 63-503099 (JP, A) Toshiyuki Tamura et al., A Data-Driven architecture for Distributed Parallel Processing, IEEE Inte national Confer ence on Computer D esign: VLSI in Com puters and Process ors, the United States, 1991, p. 218-224 Kennorou Shimano, Chuichi Arakawa, Numerical analysis of incompressible flow by parallel computation method using domain decomposition, Journal of Japan Society of Mechanical Engineers, Japan, 1993, Vol. 59, No. 567, p3340. −3346 Ken Kano et al., Nonlinear deformation analysis by finite element method on parallel computer Cenju, Journal of Information Processing, Japan, 1993, Vol. 4, p708-719 Hidehiro Takata et al., A 100-Mega-Access per Second Matching memory fora Data-Driven Microproc., 1990, UJORNAL OFS., IEEE JORNAL OFS SOL. 1, p95-99 Makoto Iwata et al., Dynamic Data Driven Processing System Qv-x Visual Evaluation Support Environment, IPSJ Research Report, Japan, 1994, VOL. 94 No. 106 (94-OS-67), p57-64 Toshiyuki Tamura et al., Software Development Environment of Data Driven Processor RAPID, Research Report of Information Processing Society of Japan, Japan, 1994, Vol94 No. 106 (94-OS-67), p169-174 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 15/80 G06F 15/16-15/177 G06F 17/13

Claims (9)

(57) [Claims] 1. A plurality of element processors, and a plurality of data buses connecting between the element processors adjacent to each other, wherein the element processors are discretized into a lattice shape for use in solving a field governing equation that can be described by a predetermined equation. An information processing device that divides the calculation space into a plurality of areas, allocates the element processors to each of the plurality of areas, and performs operations in parallel and iteratively, wherein one element processor is , In the process of repetitive calculation, regardless of the process of calculation in the other adjacent element processors, update the data of the grid point of the boundary portion between the areas adjacent to each other, the other element processor, Regardless of whether or not the data of the grid point of the boundary portion related to one element processor is updated by the one element processor,
While referring to the data of the grid points of the boundary portion according to the one element processor via the data bus,
The iterative operation is performed, the element processor has a processing unit for executing the operation, and a data memory for storing various data relating to the operation, and the one element processor is the lattice point of the boundary portion. Writing data to the data memory of its own, the other element processor refers to the data of the grid point of the boundary portion stored in the data memory of the one element processor, the processing unit, An inside point bit and an outside point bit indicating whether the position where the grid point exists for all of the grid points is inside the calculation area in the field, or inside or outside the object in the calculation area, and Boundary condition bits that give information on boundary conditions to the grid points located at the boundary of the calculation area are set to the element processor of the element processor. Information further comprising a hardware circuit according to the same wiring logic, which can be loaded into a data memory and change the processing of the data flow graph according to the inside point bit, the outside point bit and the boundary condition bit. Processing equipment. 2. A plurality of element processors and a plurality of data buses connecting between the element processors adjacent to each other, which are discretized into a lattice shape used when solving a field governing equation that can be described by a predetermined equation. An information processing device that divides the calculation space into a plurality of areas, allocates the element processors to each of the plurality of areas, and performs operations in parallel and iteratively, wherein one element processor is , In the process of repetitive calculation, regardless of the process of calculation in the other adjacent element processors, update the data of the grid point of the boundary portion between the areas adjacent to each other, the other element processor, Regardless of whether or not the data of the grid point of the boundary portion related to one element processor is updated by the one element processor,
While referring to the data of the grid points of the boundary portion according to the one element processor via the data bus,
The iterative operation is performed, the element processor has a processing unit for executing the operation, and a data memory for storing various data relating to the operation, and the one element processor is the lattice point of the boundary portion. Writing data in its own data memory, the other element processor refers to the data of the grid point of the boundary portion stored in the data memory of the one element processor, and the adjacent element processor An information processing apparatus, comprising: a fine node connection in which the element processors are connected to each other; and a coarse node connection in which the element processors are connected to each other by a coarse node connection connection by skipping one or more of the element processors. 3. A plurality of element processors and a plurality of data buses that connect the element processors adjacent to each other, and are discretized into a lattice shape used when solving a field governing equation that can be described by a predetermined equation. A calculation method using an information processing device that divides the calculation space into a plurality of areas, allocates the element processors to each of the plurality of areas, and performs operations in parallel and iteratively, a) A step in which one of the element processors updates the data of the grid point at the boundary portion between the areas adjacent to each other in the process of the iterative operation regardless of the step of the operation in the other adjacent element processors. And (b) the other element processor updates the data of the grid points of the boundary portion related to the one element processor by the one element processor. Irrespective of whether or not it has been performed, a step of performing repetitive calculation while referring to the data of the grid point of the boundary portion related to the one element processor via the data bus, The equation includes a differential equation, and the element processor is operated asynchronously and independently to obtain a solution of the differential equation by using a difference method. 4. A plurality of element processors and a plurality of data buses that connect the element processors adjacent to each other, and are discretized into a lattice shape for use in solving a field governing equation that can be described by a predetermined equation. A calculation method using an information processing device that divides the calculation space into a plurality of areas, allocates the element processors to each of the plurality of areas, and performs operations in parallel and iteratively, a) A step in which one of the element processors updates the data of the grid point at the boundary portion between the areas adjacent to each other in the process of the iterative operation regardless of the step of the operation in the other adjacent element processors. And (b) the other element processor updates the data of the grid points of the boundary portion related to the one element processor by the one element processor. Irrespective of whether or not it has been performed, a step of performing repetitive calculation while referring to the data of the grid points of the boundary portion of the one element processor via the data bus, the element processor Has a processing unit for executing an operation and a data memory for storing various data related to the operation, and in the step (a), the one element processor is
Writing the data of the grid point of the boundary portion in the data memory of its own, in the step (b), the other element processor,
With reference to the data of the grid points of the boundary portion stored in the data memory of the one element processor, the positions where the grid points exist for all of the grid points are calculation areas in the field. Boundary which gives the information of the boundary condition to the grid points located at the boundary of the calculation area, and the inside point bit and the outside point bit indicating whether the inside or outside of the calculation area or the inside or outside of the object in the calculation area. Condition bit,
The processing is performed by using the same calculation program which is given to the data memory of the element processor in advance and whose processing can be changed by the interior point bit, the exterior point bit and the boundary condition bit. A calculation method in an information processing device, wherein a unit performs a calculation. 5. A plurality of element processors and a plurality of data buses that connect the element processors adjacent to each other, and are discretized into a lattice shape used when solving a governing equation of a field that can be described by a predetermined equation. A calculation method using an information processing device that divides the calculation space into a plurality of areas, allocates the element processors to each of the plurality of areas, and performs operations in parallel and iteratively, a) A step in which one of the element processors updates the data of the grid point at the boundary portion between the areas adjacent to each other in the process of the iterative operation regardless of the step of the operation in the other adjacent element processors. And (b) the other element processor updates the data of the grid points of the boundary portion related to the one element processor by the one element processor. Irrespective of whether or not it has been performed, a step of performing repetitive calculation while referring to the data of the grid points of the boundary portion of the one element processor via the data bus, the element processor Has a processing unit for executing an operation and a data memory for storing various data related to the operation, and in the step (a), the one element processor is
Writing the data of the grid point of the boundary portion in the data memory of its own, in the step (b), the other element processor,
The processing unit refers to the data of the grid points of the boundary portion stored in the data memory of the one element processor, and the processing unit determines that the positions where the grid points exist for all the grid points. Inside point and outside point bit indicating whether the inside of the calculation area inside or the inside or outside of the object inside the calculation area, and the boundary condition information for the grid point located at the boundary of the calculation area. Boundary condition bits that give the above are loaded in the data memory of the element processor, and the processing of the data flow graph can be changed according to the inside point bits, the outside point bits and the boundary condition bits. A calculation method in an information processing apparatus, wherein the information processing apparatus further comprises a hardware-compliant logic circuit. 6. A plurality of element processors and a plurality of data buses that connect the element processors adjacent to each other, and are discretized into a lattice shape used when solving a field governing equation that can be described by a predetermined equation. A calculation method using an information processing device that divides the calculation space into a plurality of areas, allocates the element processors to each of the plurality of areas, and performs operations in parallel and iteratively, a) A step in which one of the element processors updates the data of the grid point at the boundary portion between the areas adjacent to each other in the process of the iterative operation regardless of the step of the operation in the other adjacent element processors. And (b) the other element processor updates the data of the grid points of the boundary portion related to the one element processor by the one element processor. Irrespective of whether or not it has been performed, a step of performing repetitive calculation while referring to the data of the grid points of the boundary portion of the one element processor via the data bus, the element processor Has a processing unit for executing an operation and a data memory for storing various data related to the operation, and in the step (a), the one element processor is
Writing the data of the grid point of the boundary portion in the data memory of its own, in the step (b), the other element processor,
With reference to the data of the grid point of the boundary portion stored in the data memory of the one element processor, the grid point to be calculated is on the boundary with the adjacent area, The method for computing in an information processing apparatus, wherein the number of communications at all the lattice points is leveled by performing dummy communications even for the lattice points having a small number of communications for solving the governing equation. 7. A plurality of element processors and a plurality of data buses that connect the element processors adjacent to each other, and are discretized into a lattice shape used when solving a field governing equation that can be described by a predetermined equation. A calculation method using an information processing device that divides the calculation space into a plurality of areas, allocates the element processors to each of the plurality of areas, and performs operations in parallel and iteratively, a) A step in which one of the element processors updates the data of the grid point at the boundary portion between the areas adjacent to each other in the process of the iterative operation regardless of the step of the operation in the other adjacent element processors. And (b) the other element processor updates the data of the grid points of the boundary portion related to the one element processor by the one element processor. Irrespective of whether or not it has been performed, a step of performing repetitive calculation while referring to the data of the grid points of the boundary portion of the one element processor via the data bus, the element processor Has a processing unit for executing an operation and a data memory for storing various data related to the operation, and in the step (a), the one element processor is
Writing the data of the grid point of the boundary portion in the data memory of its own, in the step (b), the other element processor,
With reference to the data of the grid point of the boundary portion stored in the data memory of the one element processor, the grid point to be calculated is on the boundary with the adjacent area, The method of computing in an information processing apparatus, wherein the number of operations at all the lattice points is leveled by performing a dummy operation on the lattice points having a small number of operations for solving the governing equation (1). 8. A plurality of element processors and a plurality of data buses that connect the element processors adjacent to each other, and are discretized into a lattice shape used when solving a field governing equation that can be described by a predetermined equation. A calculation method using an information processing device that divides the calculation space into a plurality of areas, allocates the element processors to each of the plurality of areas, and performs operations in parallel and iteratively, a) A step in which one of the element processors updates the data of the grid point at the boundary portion between the areas adjacent to each other in the process of the iterative operation regardless of the step of the operation in the other adjacent element processors. And (b) the other element processor updates the data of the grid points of the boundary portion related to the one element processor by the one element processor. Irrespective of whether or not it has been performed, a step of performing repetitive calculation while referring to the data of the grid points of the boundary portion of the one element processor via the data bus, the element processor Has a processing unit for executing an operation and a data memory for storing various data related to the operation, and in the step (a), the one element processor is
Writing the data of the grid point of the boundary portion in the data memory of its own, in the step (b), the other element processor,
With reference to the data of the grid points of the boundary portion stored in the data memory of the one element processor, when the adjacent grid points are allocated over different element processors, both the elements 2 time-series data to be sent to each other by the processors
If the data for these grid points are updated, the data of the other party will not be rewritten if the updated data is displaced by a predetermined value or less compared with the data of the previous set in time series. And a calculation method in the information processing device. 9. A plurality of element processors and a plurality of data buses that connect the element processors adjacent to each other, and are discretized into a lattice shape used when solving a field governing equation that can be described by a predetermined equation. A calculation method using an information processing device that divides the calculation space into a plurality of areas, allocates the element processors to each of the plurality of areas, and performs operations in parallel and iteratively, a) A step in which one of the element processors updates the data of the grid point at the boundary portion between the areas adjacent to each other in the process of the iterative operation regardless of the step of the operation in the other adjacent element processors. And (b) the other element processor updates the data of the grid points of the boundary portion related to the one element processor by the one element processor. Irrespective of whether or not it has been performed, a step of performing repetitive calculation while referring to the data of the grid points of the boundary portion of the one element processor via the data bus, the element processor Has a processing unit for executing an operation and a data memory for storing various data related to the operation, and in the step (a), the one element processor is
Writing the data of the grid point of the boundary portion in the data memory of its own, in the step (b), the other element processor,
Referring to the data of the grid point of the boundary portion stored in the data memory of the one element processor, a fine node connection connecting adjacent element processors, and one or more element processors A calculation method in an information processing device, comprising: using the information processing device having a coarse node connection in which the element processors are interlaced and connected by a coarse node connection connection.