JP3496283B2 - Hierarchical expansion processing method of mask pattern data of integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hierarchical expansion processing method for mask pattern data of an integrated circuit which is hierarchically compressed to reduce the data size.

In recent years, with the high integration of integrated circuits, the amount of mask pattern data in integrated circuits has significantly increased and the data size has become too large, making it difficult to handle such as storage and transfer.

For this reason, patterns such as these are grouped and hierarchically compressed into a tree structure to reduce the data size.

However, the mask pattern data of the hierarchically compressed integrated circuit is subjected to CAD for layout and graphics.
When it is used as an input to a program, it is necessary to perform hierarchical expansion processing mainly for coordinate conversion calculation and convert it into mask pattern data having no hierarchical structure.

[0005]

2. Description of the Related Art Hitherto, in a hierarchical expansion process of mask pattern data of a hierarchically compressed integrated circuit, as will be described later, the pattern in the group of the highest hierarchy is traced through all the hierarchies in order. Except that the absolute position of each pattern is obtained from the relative position of the group including the pattern.

FIG. 4 is a diagram for explaining the mask pattern data of the hierarchically compressed integrated circuit, the mask pattern data of the hierarchically expanded integrated circuit, the absolute position of the pattern and the relative position of the group.

FIG. 4A is a plan view showing an example of mask pattern data of an integrated circuit hierarchically compressed into two layers in an actual structure on the chip surface, and FIG. 4B is an actual structure on the chip surface in FIG. 4A. 6 is a plan view showing the mask pattern data of the integrated circuit obtained by hierarchically expanding the mask pattern data of the hierarchically compressed integrated circuit shown in FIG.

In FIG. 4, 1 is a frame of group A in the highest layer, 2 is a pattern in group A, 3 is a frame of group B in a lower layer included in group A, 4 is group B.
It is a pattern inside.

Here, the absolute position of the pattern means the position of the pattern with respect to the reference point of the group of the highest hierarchy, and the relative position of the group means the position of the group with respect to the reference point of the group of the higher hierarchy. .

Therefore, in the example shown in FIG. 4, a
[Coordinates (1, 2)] are absolute positions of pattern 2, b [coordinates (3, 1)] are relative positions of group B to group A, and c [coordinates (1, 1)] are in group B of pattern 4. Position b + c [coordinates (4, 2)] is the absolute position of pattern 4.

FIGS. 5 and 6 are diagrams for explaining in more detail the structure of the mask pattern data of the hierarchically compressed integrated circuit and the structure of the mask pattern data of the integrated circuit obtained by the hierarchical expansion processing.

FIG. 5 is a diagram showing an example of mask pattern data of a hierarchically compressed integrated circuit, FIG. 5A is a diagram showing the concept of a hierarchical structure, and FIG. 5B is a diagram showing the actual contents of the data on the chip surface. FIG. 5C is a plan view showing the structure of FIG. 5, and FIG. 5C is a view showing the contents of data in a memory map.

FIG. 6 is a diagram showing mask pattern data of an integrated circuit obtained by hierarchically expanding the mask pattern data of the hierarchically compressed integrated circuit shown in FIG.
FIG. 6A is a plan view showing the content of data as an actual structure on the chip surface, and FIG. 6B is a diagram showing the content of data as a memory map.

In FIG. 5A, the mask pattern data of the integrated circuit is compressed into two layers, one group A is in the upper layer, and the group whose relative position is b1 is in the lower layer of this group A. B and the group B whose relative position is b2.

In FIG. 5B, 6 is the frame of the group A in the upper hierarchy, 7 is the frame of group B whose relative position is b1, and 8 is the frame of group B whose relative position is b2.
9 shows the patterns existing in the group A as representatives, and 10 and 11 represent the patterns existing in the group B as representatives.

Further, FIG. 5C shows that the mask pattern data of the hierarchically compressed integrated circuit is "Group A" in this example.
The position of the pattern in the ... "," the position of the pattern in the group B ... "," the relative position b1 of the group B to the group A ", and the" relative position b2 of the group B to the group A ". It is shown that.

FIG. 6A shows the result of the hierarchical expansion processing.
The patterns 10 and 11 in the group B are shown to be the patterns in the group A, and FIG. 6B shows that in this case, the data of the positions of all the patterns is stored in the memory at positions (absolute) in the group A. Position) data is stored.

Here, a group B whose relative position is b1.
The absolute positions of the patterns 10 and 11 in the inside are calculated from the relative position b1, and the absolute positions of the patterns 10 and 11 in the group B whose relative position is b2 are calculated from the relative position b2.

As described above, in the hierarchical expansion processing of the mask pattern data of the hierarchically compressed integrated circuit, the absolute positions of the respective patterns are determined by tracing all the hierarchies in order and excluding the patterns in the group of the highest hierarchy. It is performed by obtaining the relative position of the group including the pattern.

FIG. 7 is a diagram showing another example of mask pattern data of a hierarchically compressed integrated circuit, FIG. 7A is a diagram showing the concept of a hierarchical structure, and FIG. 7B is an actual data on a chip surface. It is a top view shown by a structure.

In FIG. 7, 13 is the highest hierarchical group A.
, 14 is the frame of the group B in the lower hierarchy included in the group A, b is the relative position of the group B with respect to the group A, and the patterns in the groups A and B are not shown.

Reference numeral 15 indicates the frame of the lower-level group C included in the group A, c indicates the relative position of the group C with respect to the group A, and the patterns within the group C are not shown.

Reference numeral 16 denotes the frame of the lower-level group D included in the group A, d denotes the relative position of the group D with respect to the group A, and the patterns in the group D are not shown.

Reference numeral 17 denotes a frame of a lower-layer group E included in group B, 18 denotes a pattern existing in this group E, and e1 denotes a relative position of this group E with respect to group B.

Reference numeral 19 indicates the frame of the group F in the lower hierarchy included in the group B, and f1 indicates the relative position of this group F with respect to the group B. The patterns within this group F are omitted from the drawing. .

Reference numeral 20 denotes a frame of the lower-level group E included in the group C, 21 denotes a pattern in the group E, and e2 denotes a relative position of the group E with respect to the group B.

Reference numeral 22 denotes a frame of a lower-level group F included in the group C, and f2 denotes a relative position of the group F with respect to the group C. The patterns in the group F are omitted from the drawing. .

Reference numeral 23 indicates the frame of the group G of the lower hierarchy included in the group F included in the group B, g1 indicates the relative position of this group G with respect to the group F, and the pattern within this group G is shown in the figure. Is omitted.

Reference numeral 24 indicates the frame of the group H of the lower hierarchy included in the group F included in the group B, h1 indicates the relative position of this group H with respect to the group F, and the pattern within this group H is shown in the figure. Is omitted.

Reference numeral 25 indicates the frame of the group G in the lower hierarchy included in the group F included in the group C, g2 indicates the relative position of this group G with respect to the group F, and the pattern within this group G is shown in the figure. Is omitted.

Reference numeral 26 indicates the frame of the group H of the lower hierarchy included in the group F included in the group C, h2 indicates the relative position of this group H with respect to the group F, and the pattern within this group H is shown in the figure. Is omitted.

FIG. 8 shows the operation of a CPU (central processing unit) which is a processing device when the mask pattern data of the hierarchically compressed integrated circuit shown in FIG. 7 is hierarchically expanded by the conventional hierarchical expansion processing method. It is a figure which shows a situation.

That is, when the layer expansion processing is performed on the mask pattern data of the hierarchically compressed integrated circuit shown in FIG. 7 by the conventional layer expansion processing method, for example, first, the patterns in the groups B, C and D are selected. Absolute position calculation is performed sequentially.

Next, the absolute positions of the patterns in the groups E and F in the group B are calculated in order.

Next, the absolute positions of the patterns in groups E and F in group C are calculated in order.

Next, the absolute position calculation of the patterns in the groups G and H in the group F in the group B and the absolute position calculation of the patterns in the groups G and H in the group F in the group C are sequentially performed.

[0037]

As described above, in the conventional method of hierarchically developing mask pattern data of an integrated circuit, the absolute position of the pattern is calculated by tracing all the hierarchies in order. When it is complicated and the number of patterns is large, the processing time becomes long,
There is a problem that it is difficult to perform high-speed hierarchical expansion processing.

In view of the above point, the present invention can speed up the hierarchical expansion processing of mask pattern data of the hierarchically compressed integrated circuit, and shorten the processing time of the semiconductor CAD program such as layout and graphics. It is an object of the present invention to provide a method for hierarchically developing mask pattern data of an integrated circuit.

[0039]

According to a method of hierarchically developing mask pattern data of an integrated circuit according to the present invention, absolute position calculation of a plurality of patterns is performed when hierarchically expanding mask pattern data of a hierarchically compressed integrated circuit. C
Performed in parallel by hierarchy using PU, and the plurality
Of CPU, CPU to perform absolute position calculation of the pattern in the hierarchy of the group between the uppermost and the lowest, a lower layer of the group included in the group that contains the pattern itself performs absolute position computing relative position data, said plurality
Of the CPUs of (1) to (3), which transfers the patterns to the CPU that calculates the absolute position of the pattern in the group of the lower hierarchy.

[0040]

According to the present invention, performed in parallel for each hierarchy using the absolute position computing a plurality of CPU of the pattern in the case of hierarchical expansion process of the mask pattern data of the integrated circuits hierarchically compressed, and the Out of a plurality of CPUs , the pattern in the group of the hierarchy between the top and the bottom is separated.
The CPU that performs pair position calculation uses the relative position data of the lower layer group included in the group that includes the pattern for which the absolute position calculation is performed by itself as the absolute position of the pattern in the lower layer group of the plurality of CPUs. Since the data is transferred to the CPU that calculates the position, the hierarchical expansion processing is speeded up.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. 1 to 3 and FIG. 7 by taking as an example a case where hierarchical processing of integrated circuit mask pattern data shown in FIG. 7 is performed.

FIG. 1 shows an example of a computer system used in an embodiment of the present invention. In FIG. 1, 28 is a workstation (WS), 29 is a parallel machine in which a plurality of CPUs are parallelized, 30 to 33 are parallel machines 29
Is a CPU constituting the.

2 and 3 are views for explaining the contents of one embodiment of the present invention, FIG. 2 shows the flow of data, and FIG. 3 shows the operating conditions of the CPUs 30-33.

In this embodiment, the CPU 30 is in charge of the layer expansion processing of the groups B, C, and D in the hierarchy one level lower than the highest level, and the CPU 31 controls the group two levels below the highest level. It is in charge of hierarchical expansion processing of the portions of groups E and F in group B of B and C.

The CPU 32 is in charge of the hierarchical expansion processing of the groups E and F in the group C among the groups B and C in the hierarchy two steps lower from the highest rank, and the CPU 33
Is responsible for the layer expansion processing of the groups G and H in the group F of the lowest layer.

Therefore, in this embodiment, the workstation 28 supplies the data of group A to the CPU 30, the data of group B to the CPU 31, and the data of group C to the CPU 32. Data is supplied, and data of group F is supplied to the CPU 33.

For the CPU 30, the CPU 3
Transfer of data at relative position b of group B to 1; C
The data transfer of the relative position c of the group C to the PU 32 and the absolute position calculation of the patterns in the groups B, C, and D are sequentially performed.

For the CPU 31, the CPU 30
The reception of the data of the relative position b of the group B transferred from the CPU, the transfer of the data of the relative position b + f1 of the group F in the group B to the CPU 33, the absolute position calculation of the patterns in the groups E and F in the group B are sequentially performed. Let it be done.

For the CPU 32, the CPU 30
The reception of the data of the relative position c of the group C transferred from the CPU 33, the transfer of the data of the relative position c + f2 of the group F of the group C to the CPU 33, the absolute position calculation of the patterns of the groups E and F of the group C are sequentially performed. Let it be done.

For the CPU 33, the CPU 31
The data at the relative position b + f1 of the group F in the group B transferred from the group B, the group F in the group B is received.
Of absolute positions of patterns in groups G and H in group CP
The reception of the data at the relative position c + f2 of the group F in the group C transferred from the U32 and the absolute position calculation of the patterns in the groups G and H in the group F in the group C are sequentially performed.

In this case, except for the pattern in the group A, the groups B, C, D, E, F, G and H are excluded.
The absolute position data of each pattern can be obtained, and the mask pattern data of the integrated circuit obtained by hierarchically expanding the mask pattern data of the hierarchically compressed integrated circuit shown in FIG. 7 can be obtained.

As described above, in this embodiment, the hierarchical expansion processing of the mask pattern data of the hierarchically compressed integrated circuit shown in FIG. 7 is performed by the four CPUs 30 to 30 in the parallel machine 29.
33 in parallel by layers and groups B and C
I also try to do in parallel.

Therefore, according to the present embodiment, the hierarchical expansion processing of the mask pattern data of the hierarchically compressed integrated circuit shown in FIG. 7 is performed by the conventional hierarchical expansion processing method as shown in FIG. Can be done faster than.

[0054]

As described above, according to the present invention, a plurality of absolute position calculations of patterns are performed when the hierarchical expansion processing of the mask pattern data of the hierarchically compressed integrated circuit is performed.
Performed in parallel by hierarchy using CPU, and the double
Of the number of CPU, CPU to perform absolute position calculation of the pattern in the hierarchy of the group between the uppermost and the lowest, a lower layer of the group included in the group that contains the pattern itself performs absolute position computing the relative position data, the double
Among the several CPUs , the data is transferred to the CPU that calculates the absolute position of the pattern in the group of the lower hierarchy, so that the hierarchical expansion processing is speeded up and the processing time of the semiconductor CAD program such as layout and graphics is shortened. Can be planned.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a computer system used in an embodiment of the present invention.

FIG. 2 is a diagram for explaining the contents of one embodiment of the present invention.

FIG. 3 is a diagram for explaining the contents of one embodiment of the present invention.

FIG. 4 is a diagram for explaining mask pattern data and the like of a hierarchically compressed integrated circuit.

FIG. 5 is a diagram showing an example of mask pattern data of a hierarchically compressed integrated circuit.

FIG. 6 is a diagram showing mask pattern data of an integrated circuit obtained by hierarchically expanding the mask pattern data of the hierarchically compressed integrated circuit shown in FIG. 5;

FIG. 7 is a diagram showing another example of mask pattern data of a hierarchically compressed integrated circuit.

FIG. 8 is a diagram showing an operating state of a CPU, which is a processing device, when the mask pattern data of the hierarchically compressed integrated circuit shown in FIG. 7 is hierarchically expanded by a conventional hierarchical expansion processing method.

[Explanation of symbols] (Figs. 1 and 2) 28 workstations 29 parallel machines 30-33 CPU

Claims (2)

(57) [Claims] 1. A performed in parallel for each hierarchy using the absolute position computing a plurality of CPU of the pattern in the case of hierarchical expansion process of the mask pattern data hierarchy compressed integrated circuits, and, of the plurality of CPU Among them, the CPU that calculates the absolute position of the pattern in the group of the hierarchy between the highest level and the lowest level calculates the relative position data of the group of the lower level layer included in the group that includes the pattern for which the absolute position calculation is performed. A method of hierarchically expanding mask pattern data of an integrated circuit, comprising: transferring to a CPU that performs absolute position calculation of a pattern in the group of the lower hierarchy among the plurality of CPUs . 2. The CPU for transferring the relative position data of the lower layer group transfers the relative position data of the lower layer group before calculating the absolute position of the pattern in the group which it is in charge of. The method for hierarchically developing mask pattern data of an integrated circuit according to claim 1, wherein the method is performed.