JP3496978B2 - Driver circuit for semiconductor test equipment - Google Patents
Driver circuit for semiconductor test equipmentInfo
- Publication number
- JP3496978B2 JP3496978B2 JP11353994A JP11353994A JP3496978B2 JP 3496978 B2 JP3496978 B2 JP 3496978B2 JP 11353994 A JP11353994 A JP 11353994A JP 11353994 A JP11353994 A JP 11353994A JP 3496978 B2 JP3496978 B2 JP 3496978B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- circuit
- current
- terminal
- increasing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 230000000630 rising effect Effects 0.000 claims description 16
- 230000003247 decreasing effect Effects 0.000 claims description 15
- 238000001514 detection method Methods 0.000 claims description 12
- 230000007704 transition Effects 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 230000010485 coping Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Description
【発明の詳細な説明】
【0001】
【産業上の利用分野】本発明は半導体試験装置で高速化
に対応できるドライバー回路に関するものである。
【0002】
【従来の技術】半導体試験装置用ドライバー回路は高速
化出来ない回路上の制限があった。高速化するにはドラ
イバー回路の電流を増大する必要があったが従来のドラ
イバー回路の電流を増大すると、消費電力の増大によ
り、回路が破壊される可能性があった。従来の半導体試
験装置用ドライバー回路を図3に示す。VLSI等の半
導体試験装置用ドライバーの出力を高速化するには、電
流源I11・5、電流源I12・11、電流源I21・
12、電流源I22・6を大きくしなければならず、ド
ライバー回路のパワー制限により高速化に限界があっ
た。
【0003】
【発明が解決しょうとする課題】これは次の様な欠点が
あった。半導体試験装置用ドライバー回路を高速化する
には、ドライバー回路の電流を増大しなければならず、
回路上の制限によって高速化できなかった。回路配線の
変更、回路定数の変更だけでは高速化はできなかった。
半導体試験装置用ドライバー回路を高速化するために、
回路電力を上げる方式を取れば、回路の電流が大きくな
るため、回路の放熱が大変問題となり、回路の放熱が空
冷では追いつけず、冷却方法について工夫が必要であっ
た。半導体試験装置用ドライバー回路を高速化するため
に、回路の電流が大きくなると、半導体試験装置そのも
のを大電流方式にするため、装置全体が異常に大型化し
て、経済効果がそこなわれた。
【0004】
【課題を解決するための手段】本発明の課題を解決する
ための手段は、(ア)ダイオード・ブリッジ回路の出力
電圧VP7の遷移時間を検出する、C1,QX11から
なる検出回路1及びC2,QX21からなる検出回路2
を設け、(イ)立ち上がり時には、立ち上がり用の電流
源の電流を増やし、立ち下がり用の電流を減らす、RX
1,DX11,QX12,QX13からなる電流増減回
路3を設け、立ち下がり時には、立ち下がり用の電流源
の電流を増やし、立ち上がり用の電流を減らす、RX
2,DX21,QX22,QX23からなる電流増減回
路4を設け、以上のように構成する、半導体試験装置用
ドライバー回路である。
【0005】
【作用】次に本発明の作用を述べる、ダイオード・ブリ
ッジ回路の出力電圧VP7の遷移時間を検出する回路1
及び検出回路2において、出力電圧VP7の遷移時間を
検出する。電流増減回路3で、立ち上がり時には、立ち
上がり用の電流源の電流を増やし、立ち下がり用の電流
を減らし、電流増減回路4で、立ち下がり時には、立ち
下がり用の電流源の電流を増やし、立ち上がり用の電流
を減らす等の作用によって遷移時間を効率良く高速化す
る。
【0006】
【実施例】以下、本発明の実施例による電気回路を図1
に示す。
(1)コンデンサC1,トランジスタQX11からなる
検出回路1、及びコンデンサC2,トランジスタQX2
1からなる検出回路2において、ダイオード・ブリッジ
回路の出力電圧VP7の遷移時間を検出する。例えば、
立ち上がりのときC1とQX11で、立ち上がり部を検
出して、電流IC1の変化に換える。立ち下がりのと
き、C2とQX21で、立ち下がり部を検出して、電流
IC2の変化にかえる。
電流IC1の変化は次式で与えられる=(δVp/δ
t)× C1
電流IC2の変化は次式で与えられる=(δVp/δ
t)× C2
(2)抵抗RX1,ダイオードDX11,トランジスタ
QX12,トランジスタQX13からなる電流増減回路
3で、立ち上がり時には、立ち上がり用の電流源の電流
を増やし、立ち下がり用の電流を減らす。また、抵抗R
X2,ダイオードDX21,トランジスタQX22,ト
ランジスタQX23からなる電流増減回路4の回路で、
立ち下がり時には、立ち下がり用の電流源の電流を増や
し、立ち上がり用の電流を減らす。よって遷移時間を効
率的に運用し、大電流を流さないでも、目的とするドラ
イバー回路の高速化に対応できた。例えば、立ち上がり
部で電流を増やすとき電流Ip1は次式で与えられる。
〔VF(DX11)+VRX1−VBE(QX12)〕
/ R11=〔VF(DX11)−VBE(QX12)
+RX1(I11+(δVp/δt)X C1〕/ R
11
(3)ダイオード・ブリッジの出力電圧VP・7の電圧
変化、IC1・8の電流変化及び定常電流I1・9の変
化、電流増減IP1・10の変化を図2に示す。
【0007】
【発明の効果】本発明は、以上説明したように構成され
ているので、以下に記載されるような効果を奏する。
(1)半導体試験装置用ドライバー回路を高速化するに
は、回路の電流I11・5,I22・6等を大きくしな
ければならず、回路電力の制限で、高速化できなかった
従来技術と異なる。本発明では、定常電流I1・9は通
常点に置きダイオード・ブリッジ回路の出力電圧VP7
の遷移時間を検出することによって、出力電圧VP7の
立ち上がり、立ち下がりの遷移時間にタイミングよくド
ライバー電流を供給する電流増減回路の機能によって、
定常電流を常に大きく流すことなくドライバー回路の高
速化が可能となった。
(2)ドライバー回路の高速化のために、定常電流を常
に大きく流す必要のない回路構成となったため、回路の
放熱の問題もなく、小型で高性能で、経済効果の高い半
導体試験装置用ドライバー回路の提供が可能となった。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver circuit capable of coping with high speed in a semiconductor test apparatus. 2. Description of the Related Art A driver circuit for a semiconductor test apparatus has a limitation in terms of a circuit which cannot be operated at high speed. To increase the speed, it was necessary to increase the current of the driver circuit. However, if the current of the conventional driver circuit was increased, the circuit could be broken due to an increase in power consumption. FIG. 3 shows a conventional driver circuit for a semiconductor test apparatus. To speed up the output of a driver for a semiconductor test device such as a VLSI, the current sources I11.5, I1211, I21
12. The current source I22.6 must be increased, and there is a limit to speeding up due to the power limitation of the driver circuit. [0003] This has the following disadvantages. To speed up the driver circuit for semiconductor test equipment, the current of the driver circuit must be increased,
The speed could not be increased due to circuit limitations. It was not possible to increase the speed simply by changing the circuit wiring and changing the circuit constants.
In order to speed up the driver circuit for semiconductor test equipment,
If the method of increasing the circuit power is adopted, the current of the circuit becomes large, so that the heat radiation of the circuit becomes a serious problem, and the heat radiation of the circuit cannot be caught by air cooling, and a method of cooling is required. When the current of the circuit increases in order to increase the speed of the driver circuit for the semiconductor test apparatus, the semiconductor test apparatus itself becomes a large current type, so that the entire apparatus becomes abnormally large and the economic effect is impaired. Means for solving the problems are as follows. (A) A detection circuit 1 comprising C1 and QX11 for detecting a transition time of an output voltage VP7 of a diode bridge circuit. And a detection circuit 2 comprising C2 and QX21
(A) At the time of rising, the current of the rising current source is increased and the falling current is reduced.
1, a current increasing / decreasing circuit 3 composed of DX11, QX12, and QX13. At the time of falling, the current of the current source for falling is increased, and the current for rising is reduced.
2, a driver circuit for a semiconductor test apparatus, provided with a current increasing / decreasing circuit 4 composed of DX21, QX22, and QX23, and configured as described above. Next, a circuit 1 for detecting the transition time of the output voltage VP7 of the diode bridge circuit, which describes the operation of the present invention.
And the detection circuit 2 detects the transition time of the output voltage VP7. The current increasing / decreasing circuit 3 increases the current of the rising current source when rising, and reduces the falling current, and the current increasing / decreasing circuit 4 increases the current of the falling current source when falling, The transition time is efficiently speeded up by an action such as reducing the current of the device. FIG. 1 shows an electric circuit according to an embodiment of the present invention.
Shown in (1) Detection circuit 1 including capacitor C1 and transistor QX11, and capacitor C2 and transistor QX2
1 detects a transition time of the output voltage VP7 of the diode bridge circuit. For example,
At the time of rising, the rising portion is detected by C1 and QX11, and replaced with a change in the current IC1. At the time of falling, the falling part is detected by C2 and QX21, and the change in the current IC2 is changed. The change in the current IC1 is given by the following equation: = (δVp / δ)
t) × C1 The change of the current IC2 is given by the following equation = (δVp / δ)
t) × C2 (2) In the current increasing / decreasing circuit 3 including the resistor RX1, the diode DX11, the transistor QX12, and the transistor QX13, at the time of rising, the current of the rising current source is increased, and the falling current is decreased. The resistance R
X2, a diode DX21, a transistor QX22, and a transistor QX23.
At the time of the fall, the current of the fall current source is increased, and the rise current is decreased. Therefore, it was possible to efficiently operate the transition time and cope with an increase in the speed of the target driver circuit without flowing a large current. For example, when increasing the current at the rising portion, the current Ip1 is given by the following equation. [VF (DX11) + VRX1-VBE (QX12)]
/ R11 = [VF (DX11) -VBE (QX12)
+ RX1 (I11 + (δVp / δt) X C1] / R
11 (3) FIG. 2 shows a change in the output voltage VP.7 of the diode bridge, a change in the current of ICs 1 and 8, a change in the steady-state current I1.9, and a change in the current increase / decrease IP1.10. [0007] The present invention is configured as described above, and has the following effects. (1) In order to increase the speed of a driver circuit for a semiconductor test device, the currents I11, 5, I2, and 6 of the circuit must be increased, and this is different from the conventional technology that could not be increased due to the limitation of circuit power. . In the present invention, the steady-state current I1 · 9 is set at the normal point and the output voltage VP7 of the diode bridge circuit is set.
By detecting the transition time of the output voltage VP7, the function of a current increasing / decreasing circuit that supplies a driver current with good timing at the transition time of the rise and fall of the output voltage VP7
It has become possible to speed up the driver circuit without constantly flowing a large steady current. (2) A small, high-performance, and economically efficient driver for semiconductor test equipment that has no circuit heat dissipation problem because it has a circuit configuration that does not require a large steady-state current to flow in order to speed up the driver circuit. Circuits can now be provided.
【図面の簡単な説明】 【図1】本発明の、実施例による電気回路図 【図2】本発明の、実施例による電圧、電流変化の図 【図3】従来技術の、実施例による電気回路図 【符号の説明】 1 検出回路 2 検出回路 3 電流増減回路 4 電流増減回路 5 I11の電流源 6 I22の電流源 7 ダイオード・ブリッジの出力電圧VP 8 コンデンサーC1による検出電流IC1 9 定常電流I1 10 立ち上がり電流IP1 11 I12の電流源 12 I21の電流源[Brief description of the drawings] FIG. 1 is an electric circuit diagram according to an embodiment of the present invention. FIG. 2 is a diagram of voltage and current changes according to an embodiment of the present invention. FIG. 3 is a prior art electrical circuit diagram according to an embodiment; [Explanation of symbols] 1 Detection circuit 2 Detection circuit 3 Current increase / decrease circuit 4 Current increase / decrease circuit 5 I11 current source 6 I22 current source 7. Diode bridge output voltage VP 8 Detection current IC1 by capacitor C1 9 Steady-state current I1 10 Rising current IP1 11 I12 current source 12 I21 current source
Claims (1)
ファしたバッファ出力電圧VOUTを被試験半導体へ供
給する半導体試験装置用ドライバー回路であって、 該入力電圧信号(VP)を受けて遷移する立ち上がり側
の遷移時間を検出する第1の検出回路(1)と、 該入力電圧信号(VP)を受けて遷移する立ち下がり側
の遷移時間を検出する第2の検出回路(2)と、 該第1の検出回路(1)に基づいて、立ち上がり時には
立ち上がり用の電流源の電流を増やし、立ち下がり用の
電流を減らす第1の電流増減回路(3)と、 該第2の検出回路(2)に基づいて、立ち下がり時には
立ち下がり用の電流源の電流を増やし、立ち上がり用の
電流を減らす第2の電流増減回路(4)とを具備し、 該第1の検出回路(1)は第1のコンデンサ(C1)と
第3のトランジスタ(QX11)とを備え、 該第3のトランジスタの入力端は該入力電圧信号(V
P)に接続し、 該第3のトランジスタのエミッタ端は該第1のコンデン
サの一端に接続し、 該第1のコンデンサの他端は回路アースに接続して立ち
上がり側の遷移時間を検出して該第3のトランジスタの
出力端から該第1の電流増減回路へ供給するものであ
り、 該第2の検出回路(2)は第2のコンデンサ(C2)と
第4のトランジスタ(QX21)とを備え、 該第4のトランジスタの入力端は該入力電圧信号(V
P)に接続し、 該第4のトランジスタのエミッタ端は該第2のコンデン
サの一端に接続し、 該第2のコンデンサの他端は回路アースに接続して立ち
下がり側の遷移時間を検出して該第4のトランジスタの
出力端から該第2の電流増減回路へ供給するものであ
り、 該第1の電流増減回路(3)は第1の抵抗(RX1)、
第1のダイオード(DX11)、第5のトランジスタ
(QX13)を備え、 該第1の抵抗と第1のダイオードを直列接続して正の電
源端と該第3トランジスタの出力端に接続し、 該第5のトランジスタの入力端は該第3トランジスタの
出力端に接続し、該第5のトランジスタのエミッタ端は
抵抗を介して正の電源に接続し、該第5のトランジスタ
の出力端は該第1のトランジスタの入力端へ接続し、 該第2の電流増減回路(4)は第2の抵抗(RX2)、
第2のダイオード(DX21)、第6のトランジスタ
(QX23)を備え、 該第2の抵抗と第2のダイオードを直列接続して負の電
源端と該第4トランジスタの出力端に接続し、 該第6のトランジスタの入力端は該第4トランジスタの
出力端に接続し、該第6のトランジスタのエミッタ端は
抵抗を介して負の電源に接続し、該第6のトランジスタ
の出力端は該第2のトランジスタの入力端へ接続する、 ことを特徴とする半導体試験装置用ドライバー回路。(57) A driver circuit for a semiconductor test apparatus which receives an input voltage signal (VP) and supplies a buffered output voltage VOUT which is current-buffered to a semiconductor device under test, comprising: A first detection circuit (1) for detecting a transition time on a rising side which transits upon receiving the signal (VP), and a second detection circuit for detecting a transition time on a falling side which transits upon receiving the input voltage signal (VP) A first current increasing / decreasing circuit (3) for increasing the current of the rising current source at the time of rising and decreasing the falling current based on the first detecting circuit (1) based on the first detecting circuit (1). A second current increasing / decreasing circuit (4) for increasing the current of the falling current source at the time of falling and reducing the rising current based on the second detection circuit (2); 1 detection circuit (1 The first capacitor (C1) and comprises a third transistor and a (QX11), the input terminal of the third transistor is input voltage signal (V
P), the emitter end of the third transistor is connected to one end of the first capacitor, and the other end of the first capacitor is connected to circuit ground to detect the transition time on the rising side. The second detection circuit (2) supplies a second capacitor (C2) and a fourth transistor (QX21) from the output terminal of the third transistor to the first current increasing / decreasing circuit. The input terminal of the fourth transistor is connected to the input voltage signal (V
P), the emitter of the fourth transistor is connected to one end of the second capacitor, and the other end of the second capacitor is connected to the circuit ground to detect the transition time on the falling side. From the output terminal of the fourth transistor to the second current increasing / decreasing circuit, wherein the first current increasing / decreasing circuit (3) includes a first resistor (RX1),
A first diode (DX11) and a fifth transistor (QX13), wherein the first resistor and the first diode are connected in series and connected to a positive power supply terminal and an output terminal of the third transistor; The input terminal of the fifth transistor is connected to the output terminal of the third transistor, the emitter terminal of the fifth transistor is connected to a positive power supply via a resistor, and the output terminal of the fifth transistor is connected to the The second current increasing / decreasing circuit (4) is connected to a second resistor (RX2);
A second diode (DX21) and a sixth transistor (QX23), wherein the second resistor and the second diode are connected in series and connected to a negative power supply terminal and an output terminal of the fourth transistor; The input terminal of the sixth transistor is connected to the output terminal of the fourth transistor, the emitter terminal of the sixth transistor is connected to a negative power supply via a resistor, and the output terminal of the sixth transistor is connected to the negative terminal of the sixth transistor. A driver circuit for a semiconductor test apparatus, wherein the driver circuit is connected to an input terminal of a second transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11353994A JP3496978B2 (en) | 1994-04-28 | 1994-04-28 | Driver circuit for semiconductor test equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11353994A JP3496978B2 (en) | 1994-04-28 | 1994-04-28 | Driver circuit for semiconductor test equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07294607A JPH07294607A (en) | 1995-11-10 |
| JP3496978B2 true JP3496978B2 (en) | 2004-02-16 |
Family
ID=14614889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11353994A Expired - Fee Related JP3496978B2 (en) | 1994-04-28 | 1994-04-28 | Driver circuit for semiconductor test equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3496978B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111736054B (en) * | 2020-06-23 | 2022-09-16 | 中国南方电网有限责任公司超高压输电公司 | Test circuit for IGBT drive desaturation protection function and simulation test method thereof |
-
1994
- 1994-04-28 JP JP11353994A patent/JP3496978B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07294607A (en) | 1995-11-10 |
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