JP3497464B2 - Mounting board and mounting structure for mounting semiconductor device - Google Patents
Mounting board and mounting structure for mounting semiconductor deviceInfo
- Publication number
- JP3497464B2 JP3497464B2 JP2000357210A JP2000357210A JP3497464B2 JP 3497464 B2 JP3497464 B2 JP 3497464B2 JP 2000357210 A JP2000357210 A JP 2000357210A JP 2000357210 A JP2000357210 A JP 2000357210A JP 3497464 B2 JP3497464 B2 JP 3497464B2
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- semiconductor device
- wiring
- substrate
- mounting substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、半導体装置を実
装する実装基板および前記実装基板に半導体装置を実装
した実装構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting board on which a semiconductor device is mounted and a mounting structure in which the semiconductor device is mounted on the mounting board.
【０００２】[0002]
【従来の技術】従来、半導体装置を基板、いわゆる実装
基板に実装するには、半導体装置を実装基板（マザー基
板）に位置合わせをして重ねて固着し、その後前記半導
体装置と実装基板の間の間隙に樹脂を含浸させて補強・
固着を行っている。前記実装構造として、たとえば表面
実装型エリアアレイ端子半導体装置を、ＢＧＡ（Ball
Grid Array）基板に実装した実装構造を例にとって説
明する。図８（Ａ）中、１０は表面実装型エリアアレイ
端子半導体装置を、２０は実装基板を、９は補強樹脂層
をそれぞれ示す。表面実装型エリアアレイ端子半導体装
置１０は、半導体素子３がＢＧＡ基板１に接着材２を介
して接合され、半導体素子３上の電極とＢＧＡ基板上の
パターンが金属細線４で接続され、半導体素子３と金属
細線４全体を覆うように樹脂封止部５が設けられたもの
である。なお、ＢＧＡ基板の封止樹脂面とは反対側には
外部端子として金属端子（Ball）６が形成されている。
また、実装基板２０は配線部１２とレジスト部１４を有
する。2. Description of the Related Art Conventionally, in order to mount a semiconductor device on a substrate, a so-called mounting substrate, the semiconductor device is aligned and fixed on a mounting substrate (mother substrate) and then fixed between the semiconductor device and the mounting substrate. Reinforcing by impregnating the gap with resin
It is stuck. As the mounting structure, for example, a surface mount type area array terminal semiconductor device may be used as a BGA (Ball).
A mounting structure mounted on a (Grid Array) substrate will be described as an example. In FIG. 8A, 10 is a surface mounting type area array terminal semiconductor device, 20 is a mounting substrate, and 9 is a reinforcing resin layer. In the surface mount type area array terminal semiconductor device 10, the semiconductor element 3 is bonded to the BGA substrate 1 via the adhesive material 2, and the electrode on the semiconductor element 3 and the pattern on the BGA substrate are connected by the thin metal wire 4. The resin sealing portion 5 is provided so as to cover the whole 3 and the thin metal wire 4. A metal terminal (Ball) 6 is formed as an external terminal on the side of the BGA substrate opposite to the sealing resin surface.
Further, the mounting substrate 20 has a wiring portion 12 and a resist portion 14.
【０００３】前記エリアアレイ端子半導体装置１０の金
属端子６と実装基板２０の配線は、互いに所定の位置に
位置合わせされ、リフロー等により固着され、その後補
強樹脂が半導体装置１０と実装基板２０の間に含浸され
補強樹脂層９が形成され、補強される。この補強樹脂層
９は、周囲環境による熱応力および自己発熱による熱応
力によって、外部端子部に不具合が生ずることを防ぐた
めに形成される。しかしながら、前記構成の半導体装置
実装構造では、半導体端子部における熱応力は小さくす
ることができるが、補強樹脂層９の端部９ｂ（図８
（Ｂ）参照）に熱応力が集中し、補強樹脂層端部９ｂか
ら亀裂が発生しレジスト部を突き破り、さらには配線部
に亀裂が発生し、配線の電気抵抗の増加、電気的断線が
発生するという問題があった。（図８（Ｂ）は実装構造
を半導体装置側から見た平面図で、実装基板の配線１２
を透視した図となっており、５は樹脂封止部を９は補強
樹脂層を、２０は実装基板を示す）。図８（Ｃ）は、補
強樹脂層端部９ｂから、実装基板２０のレジスト部１４
に亀裂１９が生じ、配線部１２にまで達している状態を
示している。The metal terminals 6 of the area array terminal semiconductor device 10 and the wiring of the mounting substrate 20 are aligned with each other at predetermined positions and fixed by reflow or the like, and then a reinforcing resin is applied between the semiconductor device 10 and the mounting substrate 20. Is impregnated into the reinforcing resin layer 9 and is reinforced. The reinforcing resin layer 9 is formed in order to prevent a defect from occurring in the external terminal portion due to the thermal stress due to the surrounding environment and the thermal stress due to self-heating. However, in the semiconductor device mounting structure having the above structure, although the thermal stress in the semiconductor terminal portion can be reduced, the end portion 9b of the reinforcing resin layer 9 (see FIG.
Thermal stress concentrates on (B)), a crack is generated from the reinforcing resin layer end portion 9b and penetrates the resist portion, and further a crack is generated in the wiring portion, increasing the electric resistance of the wiring and causing an electrical disconnection. There was a problem of doing. (FIG. 8B is a plan view of the mounting structure as seen from the semiconductor device side.
Is a transparent view, and 5 is a resin sealing portion, 9 is a reinforcing resin layer, and 20 is a mounting substrate). FIG. 8C shows the resist portion 14 of the mounting substrate 20 from the reinforcing resin layer end portion 9b.
It shows a state in which a crack 19 is generated in the wire and reaches the wiring portion 12.
【０００４】[0004]
【発明が解決しようとする課題】本発明は前記問題点に
鑑みてなされたものであり、その目的は、半導体装置を
実装基板に実装した場合、補強樹脂層の端部に熱応力が
集中した場合でも、実装基板のレジスト部あるいはさら
に配線部に亀裂が生じないような実装基板を提供するこ
と、さらに、前記実装基板に半導体装置を実装した寿命
の長い実装構造を提供することにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is that when a semiconductor device is mounted on a mounting board, thermal stress is concentrated on the end portion of the reinforcing resin layer. Even in such a case, it is to provide a mounting board in which a resist portion or a wiring portion of the mounting board is not cracked, and further to provide a long-life mounting structure in which a semiconductor device is mounted on the mounting board.
【０００５】[0005]
【課題を解決するための手段】前記目的は、以下の実装
基板および実装構造を提供することにより解決される。
（１）少なくとも基板に固着せしめた半導体素子および
これらを封止する樹脂封止部を有する半導体装置を実装
する実装基板であって、レジスト部と該レジスト部によ
り覆われる配線部を有し、前記半導体装置を実装基板に
実装する際前記半導体装置と実装基板のレジスト部との
間に設けられる補強樹脂層の端部に相当する配線部の配
線の幅および／または厚さを他の配線部の配線の幅およ
び／または厚さより大きくすることを特徴とする半導体
装置を実装する実装基板。
（２）実装基板の表面の、前記幅および／または厚さを
大きくした配線部に相当する部分に、補強樹脂層端部の
位置を制御する凹部または堰部を形成することを特徴と
する前記（１）記載の半導体装置を実装する実装基板。
（３）少なくとも基板に固着せしめた半導体素子および
これらを封止する樹脂封止部を有する半導体装置を実装
する実装基板であって、レジスト部と該レジスト部によ
り覆われる配線部を有し、前記半導体装置を実装基板に
実装する際前記半導体装置と実装基板のレジスト部との
間に設けられる補強樹脂層の端部が接触する実装基板表
面の部分に、低弾性樹脂の層を形成することを特徴とす
る半導体装置を実装する実装基板。
（４）少なくとも基板に固着せしめた半導体素子および
これらを封止する樹脂封止部を有する半導体装置を実装
する実装基板であって、レジスト部と該レジスト部によ
り覆われる配線部を有し、前記半導体装置を実装基板に
実装する際前記半導体装置と実装基板のレジスト部との
間に設けられる補強樹脂層の端部に相当する部分におい
て、配線部を実装基板の表面から遠くに設けたことを特
徴とする半導体装置を実装する実装基板。
（５）少なくとも基板に固着せしめた半導体素子および
これらを封止する樹脂封止部を有する半導体装置を実装
する実装基板であって、レジスト部と該レジスト部によ
り覆われる配線部を有し、前記半導体装置を実装基板に
実装する際前記半導体装置と実装基板のレジスト部との
間に設けられる補強樹脂層の端部に相当する部分におい
て、配線部にビアを設けたことを特徴とする半導体装置
を実装する実装基板。
（６）少なくとも基板に固着せしめた半導体素子および
これらを封止する樹脂封止部を有する半導体装置を、レ
ジスト部と該レジスト部により覆われる配線部を有する
実装基板に実装した実装構造であり、前記半導体装置と
実装基板のレジスト部が補強樹脂層により補強固着され
た実装構造において、前記実装基板が前記（１）ないし
（５）のいずれか１に記載の実装基板であることを特徴
とする実装構造。The above-mentioned object can be solved by providing the following mounting board and mounting structure. (1) A mounting substrate for mounting a semiconductor device having at least a semiconductor element fixed to a substrate and a resin sealing portion for sealing the semiconductor element, the resist portion and the resist portion.
Ri covered by a wiring portion, the semiconductor device mounting wiring portion corresponding to the edge portion of the semiconductor device and the mounting substrate the resist portion and the reinforcing resin layer provided among <br/> of when mounted on the board A mounting board on which a semiconductor device is mounted, characterized in that the width and / or the thickness of the wiring is made larger than the width and / or the thickness of the wiring of another wiring portion. (2) A concave portion or a dam portion for controlling the position of the end portion of the reinforcing resin layer is formed in a portion of the surface of the mounting substrate corresponding to the wiring portion having the increased width and / or thickness. A mounting board on which the semiconductor device according to (1) is mounted. (3) A mounting substrate for mounting a semiconductor device having at least a semiconductor element fixed to a substrate and a resin sealing portion for sealing the semiconductor element, the resist portion and the resist portion.
The surface of the mounting board, which has a wiring portion covered with the semiconductor device and is in contact with an end of a reinforcing resin layer provided between the semiconductor device and the resist portion of the mounting board when the semiconductor device is mounted on the mounting board. A mounting board on which a semiconductor device is mounted, characterized in that a layer of low-elasticity resin is formed in the portion. (4) A mounting substrate for mounting a semiconductor device having at least a semiconductor element fixed to a substrate and a resin sealing portion for sealing the semiconductor element, the resist portion and the resist portion.
A wiring portion that is covered with the semiconductor device, and a portion corresponding to an end portion of a reinforcing resin layer provided between the semiconductor device and the resist portion of the mounting substrate when the semiconductor device is mounted on the mounting substrate. A mounting board for mounting a semiconductor device, wherein a wiring part is provided far from the surface of the mounting board. (5) A mounting substrate for mounting a semiconductor device having at least a semiconductor element fixed to a substrate and a resin sealing portion for sealing the semiconductor element, the resist portion and the resist portion.
A wiring portion that is covered with the semiconductor device, and a portion corresponding to an end portion of a reinforcing resin layer provided between the semiconductor device and the resist portion of the mounting substrate when the semiconductor device is mounted on the mounting substrate. A mounting board for mounting a semiconductor device, wherein a via is provided in a wiring portion. (6) A semiconductor device having a resin sealing portion for sealing the semiconductor element and these were allowed affixed to at least a substrate, Les
The mounting structure is mounted on a mounting substrate having a distant portion and a wiring portion covered by the resist portion , wherein the semiconductor device and the mounting substrate have a resist portion reinforced and fixed by a reinforcing resin layer. A mounting structure, wherein the mounting board is the mounting board according to any one of (1) to (5).
【０００６】[0006]
【発明の実施の形態】本発明においては、半導体装置実
装構造に用いる実装基板として、補強樹脂層の端部に熱
応力が集中し、前記端部近傍の実装基板のレジスト部あ
るいはさらに配線部にその熱応力がかかった場合でも、
亀裂または断線が生じないような構造を有する実装基板
あるいは、その熱応力が配線部にかかりにくいような構
造の実装基板を用いることを特徴とする。次に、このよ
うな実装基板を用いる実装構造の態様を説明する。以下
の態様においては、半導体装置の基板として、前記のＢ
ＧＡ基板を用いる例を示すが、本発明における半導体の
基板としては、ＢＧＡ基板のみならず、配線部分が直接
実装基板の配線に接触するような基板を用いることもで
きる。BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, as a mounting substrate used for a semiconductor device mounting structure, thermal stress is concentrated on the end portion of the reinforcing resin layer, and the resist portion of the mounting substrate near the end portion or further on the wiring portion. Even when that thermal stress is applied,
It is characterized in that a mounting board having a structure in which cracks or disconnections do not occur, or a mounting board having a structure in which thermal stress is less likely to be applied to the wiring portion is used. Next, a mode of a mounting structure using such a mounting substrate will be described. In the following embodiment, the above-mentioned B is used as the substrate of the semiconductor device.
Although an example using a GA substrate is shown, the semiconductor substrate in the present invention may be not only a BGA substrate but also a substrate whose wiring portion directly contacts the wiring of the mounting substrate.
【０００７】（第１の態様）実装基板の第１の態様は、
実装基板の、半導体装置を実装基板に実装する際前記半
導体装置と実装基板の間に設けられる補強樹脂層の端部
（以下において、「補強樹脂層端部」という）に相当す
る部分において、配線に配線太部を設けるものである。
図１は、この実装基板を用いる実装構造を半導体素子の
側から見て、実装基板の配線部が顕れるようにした透視
図である。図中５は樹脂封止部、２０は実装基板、９は
補強樹脂層、９ａは補強樹脂層端部、１２は実装基板の
配線部、１２ａは配線太部をそれぞれ示す。配線太部１
２ａは実装基板平面に対して平行な方向（以下におい
て、単に「平面方向」ということがある。）において、
その他の配線部より配線の幅が広く、かつ実装基板平面
に対して垂直方向の厚さ（以下において、単に「厚さ」
ということがある）はその他の配線部と同じ厚さに形成
されている。配線太部１２ａの平面方向における幅は、
配線部の他の部分に比較して１．５倍程度以上であるこ
とが好ましい。ただし、余り幅を大きくすると隣接する
配線太部の電気的影響を受けることになるので、上限は
この点および他の要素を考慮して適宜決めることができ
る。また、配線太部１２ａを形成する位置は、図に示す
ように補強樹脂層端部９ｂをまたぐように形成すること
が好ましく、配線部の長手方向には０．３〜１ｍｍ程度
に設けることが好ましい。また、配線太部の厚さを、後
述の第２の態様のように、より厚く形成することも可能
である。図に示す配線太部１２ａを有する実装基板を用
いると、周囲環境による熱応力および自己発熱による熱
応力は補強樹脂層端部９ｂに集中し、実装基板の配線１
１の配線太部１２ａに集中するが、１２ａは他の部分に
比較して幅広に形成しているので、熱応力に対する抵抗
が強く、配線に亀裂が発生することがなく、実装構造の
寿命を長くすることができる。(First Mode) The first mode of the mounting board is
When mounting the semiconductor device on the mounting substrate of the mounting substrate, wiring is provided in a portion corresponding to an end portion of the reinforcing resin layer provided between the semiconductor device and the mounting substrate (hereinafter referred to as “reinforcing resin layer end portion”). A thick wire portion is provided on the.
FIG. 1 is a perspective view of a mounting structure using this mounting substrate, as viewed from the semiconductor element side, so that the wiring portion of the mounting substrate is exposed. In the figure, 5 is a resin sealing portion, 20 is a mounting substrate, 9 is a reinforcing resin layer, 9a is an end portion of the reinforcing resin layer, 12 is a wiring portion of the mounting substrate, and 12a is a thick wiring portion. Thick wiring 1
2a is in a direction parallel to the plane of the mounting board (hereinafter, may be simply referred to as "plane direction"),
The width of the wiring is wider than other wiring parts, and the thickness in the direction perpendicular to the mounting board plane (hereinafter, simply "thickness"
Is formed in the same thickness as other wiring portions. The width of the thick wiring portion 12a in the plane direction is
It is preferably about 1.5 times or more as compared with other portions of the wiring portion. However, if the excessive width is made large, it will be electrically affected by the adjacent thick wiring portion, so the upper limit can be appropriately determined in consideration of this point and other factors. Further, as shown in the figure, the position where the thick wiring portion 12a is formed is preferably formed so as to straddle the reinforcing resin layer end portion 9b, and it is provided in the longitudinal direction of the wiring portion at about 0.3 to 1 mm. preferable. Further, it is possible to form the thickness of the thick wiring portion to be thicker as in a second aspect described later. When the mounting board having the thick wiring portion 12a shown in the figure is used, the thermal stress due to the ambient environment and the thermal stress due to self-heating are concentrated on the reinforcing resin layer end portion 9b, and the wiring 1 of the mounting board is
Although it concentrates on one wiring thick portion 12a, since 12a is formed wider than other portions, resistance to thermal stress is strong, wiring does not crack, and the life of the mounting structure is improved. Can be long.
【０００８】（第２の態様）実装基板の第２の態様は、
実装基板の、補強樹脂層端部に相当する部分において、
配線に配線厚部を設けるものである。図２は、前記の実
装基板を用いる実装構造の断面を表わす概念図である。
図中、３は半導体素子、５は樹脂封止部、９は補強樹脂
層、９ｂは補強樹脂層端部、２０は実装基板、２０ａは
実装基板２０のレジスト部、２０ｂは実装基板２０を構
成する基体、１２は配線部、１２ｂは配線厚部をそれぞ
れ示す。配線厚部１２ｂにおける配線の厚さがその他の
配線部の厚さより厚くなるように形成されている。配線
厚部１２ｂにおける厚さは、配線部の他の部分に比較し
て１．５倍程度以上厚く形成することが好ましい。ま
た、配線厚部１２ｂを形成する位置は、図に示すように
補強樹脂層端部９ｂをまたぐように形成することが好ま
しく、配線部の長手方向には０．３〜１．０ｍｍ程度に
設けることが好ましい。また、配線厚部の幅（太さ）
を、前記の第１の態様のように、より幅広に形成するこ
とも可能である。図２に示す配線厚部１２ｂを有する実
装基板を用いると、周囲環境による熱応力および自己発
熱による熱応力は補強樹脂層端部９ｂに集中し、実装基
板の配線１２の配線厚部１２ｂに集中するが、１２ｂは
他の部分に比較して厚く形成されているので、熱応力に
対する抵抗が強く、配線に亀裂が発生することがなく、
実装構造の寿命を長くすることができる。(Second Mode) A second mode of the mounting board is
In the part of the mounting board corresponding to the end of the reinforcing resin layer,
A thick wiring portion is provided on the wiring. FIG. 2 is a conceptual diagram showing a cross section of a mounting structure using the mounting board.
In the figure, 3 is a semiconductor element, 5 is a resin sealing portion, 9 is a reinforcing resin layer, 9b is an end portion of the reinforcing resin layer, 20 is a mounting substrate, 20a is a resist portion of the mounting substrate 20, and 20b is a mounting substrate 20. A base body, a wiring portion 12 and a wiring thick portion 12b, respectively. The thickness of the wiring in the thick wiring portion 12b is formed to be thicker than the thickness of the other wiring portions. The thickness of the wiring thick portion 12b is preferably formed to be about 1.5 times thicker than other portions of the wiring portion. Further, it is preferable that the wiring thick portion 12b is formed so as to straddle the reinforcing resin layer end portion 9b as shown in the figure, and is provided in the longitudinal direction of the wiring portion at about 0.3 to 1.0 mm. It is preferable. The width (thickness) of the thick wiring part
Can also be formed wider as in the first aspect. When the mounting board having the wiring thick portion 12b shown in FIG. 2 is used, the thermal stress due to the ambient environment and the thermal stress due to self-heating are concentrated at the end portion 9b of the reinforcing resin layer and concentrated at the wiring thick portion 12b of the wiring 12 of the mounting substrate. However, since 12b is formed thicker than other parts, it has a high resistance to thermal stress and does not cause cracks in the wiring.
The life of the mounting structure can be extended.
【０００９】（第３の態様）実装基板の第３の態様は、
第１の態様あるいは第２の態様において、さらに、実装
基板の表面の、前記幅および／または厚さを大きくした
配線部に相当する部分に、補強樹脂層端部の位置を制御
する凹部を形成したものである。図３はこの態様を示す
概念図で、配線部の一部を厚部１２ｂに形成している。
実装基板２０の表面には、この厚部１２ｂに相当する部
分に凹部１５が形成されている。補強樹脂を含浸する
際、この凹部１５により、補強樹脂の流れが制限され、
補強樹脂層端部９ｂの位置が容易に制御可能となる。し
たがって、この態様の場合は、半導体装置を実装基板に
実装する場合特別な注意を払うことなく、補強樹脂層の
端部９ｂが、配線部の太部または厚部の位置に形成され
ることが確実となり、熱応力を、確実に配線太部あるい
は厚部に集中させ、実装構造の寿命を長くすることがで
きる。また、凹部の幅は０．３〜１．０ｍｍ程度が適切
である。(Third Aspect) A third aspect of the mounting board is
In the first aspect or the second aspect, further, a concave portion for controlling the position of the end portion of the reinforcing resin layer is formed in a portion of the surface of the mounting substrate corresponding to the wiring portion having the increased width and / or thickness. It was done. FIG. 3 is a conceptual diagram showing this aspect, in which a part of the wiring portion is formed in the thick portion 12b.
A recess 15 is formed on the surface of the mounting substrate 20 at a portion corresponding to the thick portion 12b. When the reinforcing resin is impregnated, the recess 15 restricts the flow of the reinforcing resin,
The position of the reinforcing resin layer end portion 9b can be easily controlled. Therefore, in the case of this aspect, the end portion 9b of the reinforcing resin layer may be formed at the position of the thick portion or the thick portion of the wiring portion without paying special attention when mounting the semiconductor device on the mounting substrate. As a result, the thermal stress can be reliably concentrated on the thick or thick portion of the wiring, and the life of the mounting structure can be extended. Further, it is appropriate that the width of the recess is about 0.3 to 1.0 mm.
【００１０】（第４の態様）実装基板の第４の態様は、
第１の態様あるいは第２の態様において、さらに、実装
基板の表面の、前記幅および／または厚さを大きくした
配線部に相当する部分に、補強樹脂層端部の位置を制御
する堰部を形成したものである。図４（Ａ）および図４
（Ｂ）はこの態様を示す概念図で、図４（Ａ）は実装基
板の配線部を透視した図を、図４（Ｂ）はその断面図を
示す。この例では、配線部の補強樹脂層端部９ｂに相当
する部分を厚太部１２ｄに形成している。実装基板２０
の表面には、この厚太部１２ｄに相当する部分に堰部１
６が形成されている。補強樹脂を含浸する際、この堰部
１６により、補強樹脂の流れが止められる。したがっ
て、この態様の場合も第３の態様と同様に、補強樹脂層
の端部が、配線部の太部または厚部の位置に形成される
ことが確実となり、熱応力を、確実に配線太部あるいは
厚部に集中させ、実装構造の寿命を長くすることができ
る。堰部は、実装基板のレジストと密着性の良好な樹脂
を用いることが好ましく、レジストがエポキシ系の樹脂
の場合には、たとえばエポキシ系の樹脂を用いることが
好ましい。また、堰部の幅は０．３〜１．０ｍｍ程度が
適切である。(Fourth Aspect) A fourth aspect of the mounting board is
In the first aspect or the second aspect, a weir portion for controlling the position of the end portion of the reinforcing resin layer is further provided on a portion of the surface of the mounting substrate corresponding to the wiring portion having the increased width and / or thickness. It was formed. 4A and FIG.
4B is a conceptual diagram showing this aspect, FIG. 4A is a perspective view of the wiring portion of the mounting substrate, and FIG. 4B is a sectional view thereof. In this example, a portion corresponding to the reinforcing resin layer end portion 9b of the wiring portion is formed as the thick portion 12d. Mounting board 20
The weir portion 1 is provided on the surface corresponding to the thick portion 12d.
6 is formed. When impregnating the reinforcing resin, the dam portion 16 stops the flow of the reinforcing resin. Therefore, also in the case of this aspect, as in the case of the third aspect, it is ensured that the end portion of the reinforcing resin layer is formed at the position of the thick portion or the thick portion of the wiring portion, and the thermal stress can be reliably reduced in the thick wiring portion. It is possible to extend the life of the mounting structure by concentrating on the thick portion or the thick portion. For the dam portion, it is preferable to use a resin having good adhesiveness with the resist of the mounting board. When the resist is an epoxy resin, for example, an epoxy resin is preferably used. Further, it is appropriate that the width of the weir is about 0.3 to 1.0 mm.
【００１１】（第５の態様）第５の態様は、前記半導体
装置を実装基板に実装する際前記半導体装置と実装基板
の間に設けられる補強樹脂層の端部が接触する実装基板
表面の部分に、低弾性樹脂の層を形成するものである。
図５はこの態様を示す概念図であり、図５中１７は低弾
性樹脂の層を示す。図５に示すように補強樹脂層の端部
９ｂが実装基板２０の低弾性樹脂の層１７の上に形成さ
れると、熱応力は補強樹脂層の端部９ｂに集中するが、
端部９ｂの下に形成された低弾性樹脂の層１７により応
力が分散され、その結果、実装構造は、熱応力に対して
強く、寿命を長くすることができる。前記低弾性樹脂と
しては、応力分散効果がある樹脂は特に制限なく用いる
ことができるが、低弾性樹脂の弾性率（ヤング率）が１
００Ｋｇ／ｍｍ2以下の樹脂が好ましく、たとえばシリ
コーン系樹脂や低弾性付与添加剤を混合したエポキシ樹
脂などが用いられる。また、低弾性の樹脂の層の厚さ
は、１０〜１００μｍ程度であることが好ましく、低弾
性樹脂層の幅は０．３〜０．５ｍｍ程度が適している。(Fifth Aspect) A fifth aspect is a portion of the surface of a mounting substrate which is in contact with an end portion of a reinforcing resin layer provided between the semiconductor device and the mounting substrate when the semiconductor device is mounted on the mounting substrate. Further, a low-elasticity resin layer is formed.
FIG. 5 is a conceptual diagram showing this aspect, and 17 in FIG. 5 shows a layer of low-elasticity resin. When the end portion 9b of the reinforcing resin layer is formed on the low-elasticity resin layer 17 of the mounting board 20 as shown in FIG. 5, thermal stress concentrates on the end portion 9b of the reinforcing resin layer,
The stress is dispersed by the low-elasticity resin layer 17 formed under the end portion 9b, and as a result, the mounting structure is resistant to thermal stress and can have a long life. As the low-elasticity resin, a resin having a stress dispersion effect can be used without particular limitation, but the elastic modulus (Young's modulus) of the low-elasticity resin is 1
A resin of 00 Kg / mm 2 or less is preferable, and for example, a silicone resin or an epoxy resin mixed with a low elasticity imparting agent is used. The thickness of the low-elasticity resin layer is preferably about 10 to 100 μm, and the width of the low-elasticity resin layer is suitably about 0.3 to 0.5 mm.
【００１２】（第６の態様）配線基板の第６の態様は、
実装基板の、補強樹脂層端部９ｂに相当する部分におい
て、配線部を実装基板の表面から遠くに設けたものであ
る。図６はこの態様を示すもので、実装基板の、補強樹
脂層端部９ｂに相当する部分において、実装基板の表面
近くに配線が通らず表面から離れた位置に配線１２ｔが
通り、前記部分から離れた位置にビア１２ｕを形成し、
このビア１２ｕを介して配線１２ｓと１２ｔを連結す
る。すなわち、実装基板の補強樹脂層が設けられる面か
らみて、配線１２ｔが配線１２ｓよりも遠くの位置に形
成されており、配線１２ｔ上には、レジスト２０ａより
も強固な、実装基板２０を構成する基体２０ｂが存在し
ている。したがって、熱応力は補強樹脂層９の端部９ｂ
に集中するが、補強樹脂層９の端部９ｂに相当する部分
の配線１２ｔは実装基板２０の表面から離れて形成され
ており、配線１２ｔ上にはレジスト（２０ａ）よりも強
固な基体２０ｂが存在することになるので、配線１２ｔ
に対して集中する応力は低減される。以上のような構成
を有する実装基板を用いた実装構造では、断線等の不具
合は発生せず、寿命を長くすることができる。また、図
６ではビア部分が実装基板を貫通しない構造であるが、
この変形例として、ビア部分を実装基板を貫通させ、図
６の１２ｔの部分を実装基板の補強樹脂層に接する面と
は反対側の面に配線する構造を採用してもよく、同様の
効果を得ることができる。(Sixth Mode) A sixth mode of the wiring board is
In the portion of the mounting board corresponding to the reinforcing resin layer end portion 9b, the wiring portion is provided far from the surface of the mounting board. FIG. 6 shows this aspect. In the portion of the mounting board corresponding to the end portion 9b of the reinforcing resin layer, the wiring 12t passes through a position away from the surface without passing through the wiring near the surface of the mounting board. Via 12u is formed at a distant position,
The wirings 12s and 12t are connected via the via 12u. That is, the wiring 12t is formed at a position farther than the wiring 12s as viewed from the surface of the mounting board on which the reinforcing resin layer is provided, and the mounting board 20 that is stronger than the resist 20a is formed on the wiring 12t. The base body 20b is present. Therefore, the thermal stress is applied to the end portion 9b of the reinforcing resin layer 9.
However, the wiring 12t in a portion corresponding to the end 9b of the reinforcing resin layer 9 is formed apart from the surface of the mounting substrate 20, and a base body 20b stronger than the resist (20a) is formed on the wiring 12t. Since it will exist, the wiring 12t
The stress concentrated on is reduced. In the mounting structure using the mounting board having the above-described configuration, problems such as disconnection do not occur and the life can be extended. Further, in FIG. 6, the via portion does not penetrate the mounting substrate,
As a modified example, a structure may be adopted in which the via portion penetrates the mounting substrate and the portion 12t in FIG. 6 is wired on the surface of the mounting substrate opposite to the surface in contact with the reinforcing resin layer. Can be obtained.
【００１３】（第７の態様）第７の態様は、実装基板
の、補強樹脂層端部９ｂに相当する部分において、ビア
の部分を形成するものである。この構造にすると、補強
樹脂層端部９ｂに相当する箇所に設けた、配線１２ｘと
１２ｙを結ぶビア１２ｚの、９ｂに近い部分に亀裂が生
じた場合でも、それが配線１２ｙに到達するまでに相当
の時間的余裕があり、この部分にビアを設けていない場
合に比較して、実装構造の寿命を長くすることができ
る。また、第６の態様と同様、ビア部分を実装基板を貫
通させる構造、すなわち、図７の１２ｚの部分を基板を
貫通させ、１２ｙの部分を実装基板の補強樹脂層に接す
る面とは反対側の面に配線する構造としてもよい。(Seventh Mode) In a seventh mode, a via portion is formed in a portion of the mounting substrate corresponding to the reinforcing resin layer end portion 9b. With this structure, even if a crack near the portion 9b of the via 12z that connects the wirings 12x and 12y provided at a portion corresponding to the reinforcing resin layer end portion 9b is cracked by the time it reaches the wiring 12y. There is a considerable time margin, and the life of the mounting structure can be extended as compared with the case where no via is provided in this portion. Further, similar to the sixth aspect, the structure is such that the via portion penetrates the mounting substrate, that is, the portion 12z of FIG. 7 penetrates the substrate and the portion 12y of the mounting substrate is opposite to the surface in contact with the reinforcing resin layer. The structure may be such that wiring is provided on the surface of
【００１４】[0014]
【発明の効果】本発明は、半導体装置と実装基板の間に
設けた補強樹脂層の端部に集中する熱応力に高い抵抗性
を有する、あるいは熱応力を分散することができる前記
のごとき構造の実装基板であるので、これに半導体装置
を実装した場合、その寿命を長くすることができる。According to the present invention, the structure as described above has a high resistance to the thermal stress concentrated at the end of the reinforcing resin layer provided between the semiconductor device and the mounting substrate, or can disperse the thermal stress. Since it is the mounting substrate of No. 3, when the semiconductor device is mounted on it, the life of the semiconductor device can be extended.
【図１】 配線太部を設けた実装基板を用いる実装構造
の平面図を示す図である。FIG. 1 is a diagram showing a plan view of a mounting structure using a mounting substrate provided with thick wiring portions.
【図２】 配線厚部を設けた実装基板を用いる実装構造
の一部断面図を示す。FIG. 2 is a partial cross-sectional view of a mounting structure using a mounting substrate provided with a thick wiring portion.
【図３】 配線太部または配線厚部に相当する箇所に凹
部を設けた実装基板を用いる実装構造の一部断面図を示
す。FIG. 3 is a partial cross-sectional view of a mounting structure using a mounting substrate having a concave portion at a portion corresponding to a thick wiring portion or a thick wiring portion.
【図４】 配線太部または配線厚部に相当する箇所に堰
部を設けた実装基板を用いる実装構造を示し、図４
（Ａ）はその平面図を、図４（Ｂ）はその一部断面図を
示す。FIG. 4 shows a mounting structure using a mounting substrate having a dam portion at a portion corresponding to a thick wiring portion or a thick wiring portion.
4A is a plan view thereof, and FIG. 4B is a partial sectional view thereof.
【図５】 補強樹脂層端部に相当する部分に低弾性樹脂
層を設けた実装基板を用いる実装構造の一部断面図を示
す。FIG. 5 is a partial cross-sectional view of a mounting structure using a mounting substrate in which a low-elasticity resin layer is provided in a portion corresponding to an end portion of a reinforcing resin layer.
【図６】 補強樹脂層端部に相当する部分の配線が補強
樹脂層端部から遠くにある実装基板を用いる実装構造の
一部断面図を示す。FIG. 6 is a partial cross-sectional view of a mounting structure using a mounting substrate in which a wiring corresponding to an end portion of the reinforcing resin layer is far from the end portion of the reinforcing resin layer.
【図７】 補強樹脂層端部に相当する部分に配線ビアを
設けた実装基板を用いる実装構造の一部断面図を示す。FIG. 7 is a partial cross-sectional view of a mounting structure using a mounting substrate in which a wiring via is provided in a portion corresponding to an end portion of a reinforcing resin layer.
【図８】 従来構造の実装基板および実装構造を示す図
であり、図８（Ａ）はその断面図を、図８（Ｂ）はその
平面図を、図８（Ｃ）は一部断面図を示す。8A and 8B are views showing a mounting substrate and a mounting structure of a conventional structure, FIG. 8A is a sectional view thereof, FIG. 8B is a plan view thereof, and FIG. 8C is a partial sectional view thereof. Indicates.
１ 基板 ３ 半導体素子 ５ 樹脂封止部 ９ 補強樹脂層 ９ｂ 補強樹脂層端部 １０ 半導体装置 １２ 配線 １２ａ 配線太部 １２ｂ 配線厚部 １２ｕ、１２ｚ 配線ビア １５ 凹部 １６ 堰部 １７ 低弾性樹脂層 １９ 亀裂 ２０ 実装基板 ２０ａ 実装基板のレジスト部 ２０ｂ 実装基板２０を構成する基体 1 substrate 3 Semiconductor element 5 Resin sealing part 9 Reinforcement resin layer 9b Reinforcing resin layer end 10 Semiconductor device 12 wiring 12a thick wiring 12b thick wiring part 12u, 12z wiring via 15 recess 16 weir 17 Low elasticity resin layer 19 cracks 20 mounting board 20a Mounted substrate resist part 20b Base that constitutes the mounting substrate 20
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平11−135674（ＪＰ，Ａ) 特開2001−35886（ＪＰ，Ａ) 特開2001−208663（ＪＰ，Ａ) 特開2000−12733（ＪＰ，Ａ) 特開 平３−173436（ＪＰ，Ａ) 国際公開98／043289（ＷＯ，Ａ１) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 23/12 ─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-11-135674 (JP, A) JP-A-2001-35886 (JP, A) JP-A-2001-208663 (JP, A) JP-A-2000-12733 (JP , A) JP-A-3-173436 (JP, A) International Publication 98/043289 (WO, A1) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/60 H01L 23/12
Claims (6)
子およびこれらを封止する樹脂封止部を有する半導体装
置を実装する実装基板であって、レジスト部と該レジス
ト部により覆われる配線部を有し、前記半導体装置を実
装基板に実装する際前記半導体装置と実装基板のレジス
ト部との間に設けられる補強樹脂層の端部に相当する配
線部の配線の幅および／または厚さを他の配線部の配線
の幅および／または厚さより大きくすることを特徴とす
る半導体装置を実装する実装基板。1. A semiconductor device was allowed affixed to at least a substrate and these a mounting substrate for mounting a semiconductor device having a resin sealing portion for sealing, the resist part and the Regis
A wiring portion covered by a mounting portion, and when mounting the semiconductor device on a mounting substrate, the resist of the semiconductor device and the mounting substrate is
Semiconductors characterized by greater than the width and / or thickness of the other wiring portions of the wiring width and / or thickness of the wiring of the wiring portion corresponding to the end portion of the reinforcing resin layer provided between the isolation portions A mounting board on which the device is mounted.
は厚さを大きくした配線部に相当する部分に、補強樹脂
層端部の位置を制御する凹部または堰部を形成すること
を特徴とする請求項１に記載の半導体装置を実装する実
装基板。2. A concave portion or a dam portion for controlling the position of the end portion of the reinforcing resin layer is formed in a portion of the surface of the mounting substrate corresponding to the wiring portion having the increased width and / or thickness. A mounting board on which the semiconductor device according to claim 1 is mounted.
子およびこれらを封止する樹脂封止部を有する半導体装
置を実装する実装基板であって、レジスト部と該レジス
ト部により覆われる配線部を有し、前記半導体装置を実
装基板に実装する際前記半導体装置と実装基板のレジス
ト部との間に設けられる補強樹脂層の端部が接触する実
装基板表面の部分に、低弾性樹脂の層を形成することを
特徴とする半導体装置を実装する実装基板。3. A semiconductor device was allowed affixed to at least a substrate and these a mounting substrate for mounting a semiconductor device having a resin sealing portion for sealing, the resist part and the Regis
A wiring portion covered by a mounting portion, and when mounting the semiconductor device on a mounting substrate, the resist of the semiconductor device and the mounting substrate is
Mounting board for mounting the portion of the mounting substrate surface ends of the reinforcing resin layer provided between the isolation portion is in contact, a semiconductor device characterized by forming a layer of low-elasticity resin.
子およびこれらを封止する樹脂封止部を有する半導体装
置を実装する実装基板であって、レジスト部と該レジス
ト部により覆われる配線部を有し、前記半導体装置を実
装基板に実装する際前記半導体装置と実装基板のレジス
ト部との間に設けられる補強樹脂層の端部に相当する部
分において、配線部を実装基板の表面から遠くに設けた
ことを特徴とする半導体装置を実装する実装基板。4. A semiconductor device was allowed affixed to at least a substrate and these a mounting substrate for mounting a semiconductor device having a resin sealing portion for sealing, the resist part and the Regis
A wiring portion covered by a mounting portion, and when mounting the semiconductor device on a mounting substrate, the resist of the semiconductor device and the mounting substrate is
In the portion corresponding to the end portion of the reinforcing resin layer provided between the isolation portion, a mounting substrate for mounting a semiconductor device, characterized in that provided in the distance wiring portion from the surface of the mounting substrate.
子およびこれらを封止する樹脂封止部を有する半導体装
置を実装する実装基板であって、レジスト部と該レジス
ト部により覆われる配線部を有し、前記半導体装置を実
装基板に実装する際前記半導体装置と実装基板のレジス
ト部との間に設けられる補強樹脂層の端部に相当する部
分において、配線部にビアを設けたことを特徴とする半
導体装置を実装する実装基板。5. A semiconductor device was allowed affixed to at least a substrate and these a mounting substrate for mounting a semiconductor device having a resin sealing portion for sealing, the resist part and the Regis
A wiring portion covered by a mounting portion, and when mounting the semiconductor device on a mounting substrate, the resist of the semiconductor device and the mounting substrate is
In a portion corresponding to an end portion of the reinforcing resin layer provided between the isolation portion, a mounting substrate for mounting a semiconductor device which is characterized by providing a via wiring portion.
子およびこれらを封止する樹脂封止部を有する半導体装
置を、レジスト部と該レジスト部により覆われる配線部
を有する実装基板に実装した実装構造であり、前記半導
体装置と実装基板のレジスト部が補強樹脂層により補強
固着された実装構造において、前記実装基板が請求項１
ないし請求項５のいずれか１項に記載の実装基板である
ことを特徴とする実装構造。6. A semiconductor device having at least a semiconductor element fixed to a substrate and a resin encapsulating portion for encapsulating the semiconductor element , a resist portion, and a wiring portion covered by the resist portion.
A mounting structure mounted on a mounting substrate having: a mounting structure in which the semiconductor device and a resist portion of the mounting substrate are reinforced and fixed by a reinforcing resin layer.
A mounting structure comprising the mounting board according to claim 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000357210A JP3497464B2 (en) | 2000-11-24 | 2000-11-24 | Mounting board and mounting structure for mounting semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000357210A JP3497464B2 (en) | 2000-11-24 | 2000-11-24 | Mounting board and mounting structure for mounting semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2002164385A JP2002164385A (en) | 2002-06-07 |
| JP3497464B2 true JP3497464B2 (en) | 2004-02-16 |
Family
ID=18829312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000357210A Expired - Fee Related JP3497464B2 (en) | 2000-11-24 | 2000-11-24 | Mounting board and mounting structure for mounting semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3497464B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11527469B2 (en) | 2020-03-17 | 2022-12-13 | Kioxia Corporation | Semiconductor device |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4056360B2 (en) | 2002-11-08 | 2008-03-05 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| JP4355313B2 (en) * | 2005-12-14 | 2009-10-28 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor device |
| JP2007250674A (en) * | 2006-03-14 | 2007-09-27 | Sanyo Electric Co Ltd | Substrate and semiconductor device using the same |
| JP5015065B2 (en) * | 2008-05-28 | 2012-08-29 | 新光電気工業株式会社 | Wiring board |
| JP2013183002A (en) * | 2012-03-01 | 2013-09-12 | Ibiden Co Ltd | Electronic component |
| JP2016122802A (en) * | 2014-12-25 | 2016-07-07 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP6806520B2 (en) | 2016-10-17 | 2021-01-06 | ラピスセミコンダクタ株式会社 | How to design semiconductor devices and wiring boards |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001208663A (en) | 2000-01-26 | 2001-08-03 | Sunline Co Ltd | Abrasion test method and abrasion tester for fishing line, fishing net line, etc. |
-
2000
- 2000-11-24 JP JP2000357210A patent/JP3497464B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001208663A (en) | 2000-01-26 | 2001-08-03 | Sunline Co Ltd | Abrasion test method and abrasion tester for fishing line, fishing net line, etc. |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11527469B2 (en) | 2020-03-17 | 2022-12-13 | Kioxia Corporation | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2002164385A (en) | 2002-06-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7520177B2 (en) | Semiconductor Device | |
| US4943843A (en) | Semiconductor device | |
| JP2022177252A (en) | semiconductor equipment | |
| JPH11354680A (en) | Printed wiring board and semiconductor package using the same | |
| JP3033227B2 (en) | Semiconductor device | |
| CN102428558A (en) | Semiconductor device | |
| JP7569912B2 (en) | Semiconductor Device | |
| JP3497464B2 (en) | Mounting board and mounting structure for mounting semiconductor device | |
| JP3683434B2 (en) | Semiconductor device | |
| US6529115B2 (en) | Surface mounted resistor | |
| KR890001155A (en) | Semiconductor Device and Embedded Method of Semiconductor Device | |
| CN107958875B (en) | Semiconductor device and wiring substrate design method | |
| CN211788920U (en) | semiconductor device | |
| JP2756791B2 (en) | Resin-sealed semiconductor device | |
| US9293399B2 (en) | Semiconductor device and electronic unit provided with the same | |
| JP2021190556A (en) | Mounting structure of semiconductor device | |
| JP3216636B2 (en) | Semiconductor device | |
| JP7018965B2 (en) | Electronic module | |
| WO2023189480A1 (en) | Semiconductor element and semiconductor device | |
| JPS60242643A (en) | Wiring for electronic part | |
| KR0142756B1 (en) | Chip Holding Lead-on Chip Type Semiconductor Package | |
| WO2023140046A1 (en) | Semiconductor device | |
| JP2932824B2 (en) | Magnetoresistive sensor | |
| JPH0888298A (en) | Resin-sealed electronic circuit device | |
| JP2554059Y2 (en) | Semiconductor device mounting structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081128 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081128 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091128 Year of fee payment: 6 |
|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091128 Year of fee payment: 6 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101128 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101128 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111128 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121128 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121128 Year of fee payment: 9 |
|
| S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121128 Year of fee payment: 9 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121128 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131128 Year of fee payment: 10 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |