JP3497720B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for distributing a clock signal in a semiconductor integrated circuit, and more particularly to a clock distribution circuit capable of reducing the number of stages such as a relay buffer and mitigating skew, and a circuit therefor. The present invention relates to a circuit for supplying a stable power supply to the.

[0002]

2. Description of the Related Art Conventional clock distribution circuits include, for example,
P. Ramanathan et al. Conference Co held in November 1989
A CLOCK DISTRIBUTION S at mputer-Aidea Design
There is a distribution circuit as shown in Fig. 3 of the content (minutes 398 to 401) presented under the title CHEME FOR NON-SYMMETRIC VLSI CIRCUITS. In this example, a clock signal is input for each logical function unit, and the difference in delay time from the input point of the clock signal to the distribution destination is minimized so that synchronization is achieved. Also, Japanese Patent Laid-Open No. 5-233092
In the example described in the publication, the skew is relaxed by making the wiring length and the wiring width of the wiring through which the clock signal propagates uniform and arranging the wiring in the letter H of the alphabet. Moreover, the deterioration of the input clock signal is alleviated by connecting a multi-stage relay buffer.

The power supply terminal of a conventional chip through which a large current flows is, for example, M68060 User's Manual Including the MC6806 issued by MOTOROLA in 1994.
0, MC68LC060, and MC68EC060 There is a supply circuit as described in Figure 13.2.1 on P13-2. In this example, a plurality of terminals are provided for the same power source, the plurality of terminals are divided into some groups, and power is supplied to different circuits in each group.
As a result, the noise generated from a part of the circuit (eg, output driver) in the LSI (semiconductor integrated circuit) is
Transmission to other circuits (for example, internal logic) in SI is reduced.

[0004]

In a circuit that distributes a clock signal for each logical function unit, since the distance from the input point of the clock signal to the distribution destination becomes long, in order to propagate the high frequency clock signal, Relay buffers connected in multiple stages are necessary to avoid amplitude deterioration. Japanese Patent Laid-Open No. 5-
In Japanese Patent No. 233092, a relay buffer connected in multiple stages is described because the distance over which a high-frequency clock signal propagates becomes long.

When the relay buffers are connected in multiple stages as described above, the deterioration of the signal amplitude can be alleviated, but the skew becomes large due to the manufacturing variations of the elements forming the relay buffers and the delay variations due to power source noise and the like.

An object of the present invention is to provide a semiconductor integrated circuit capable of distributing a clock signal by reducing the number of stages of the relay buffer to reduce the skew caused by the relay buffer.

Further, when there are many circuits that require a stable power supply, a large number of power supply terminals are provided and power is supplied from a separate power supply terminal for each circuit to stabilize the power supply to each circuit. This is possible, but many power terminals are required.

With respect to this point, the present invention provides a semiconductor integrated circuit capable of distributing a clock signal by suppressing the number of power supply terminals by stabilizing the power supply to be supplied in the circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

[1] The clock distribution circuit of the present invention is
In a semiconductor integrated circuit (100) in which a plurality of circuit blocks (101) each having a predetermined circuit (113) are input and a clock signal (CLK1) is input from the outside, A first circuit (102) that receives a clock signal (CLK2) and a third clock signal (CLK that has a lower frequency than the first clock signal from the first circuit to a plurality of circuit blocks.
The wiring (107, 108) for distributing 3) and the first PLL circuit (103) mounted for each of a plurality of circuit blocks are provided. The first PLL circuit generates a first clock signal from the third clock signal and outputs it to each circuit. The first circuit may be a second PLL circuit (102).

Further, a circuit (104) for suppressing deterioration of the third clock signal output from the first circuit and transmitted to the wiring, for example, a clock buffer or a relay buffer is provided, and the first circuit is provided via this circuit. The third clock signal is distributed from the circuit to the plurality of circuit blocks. The first PLL circuit to which the third clock signal is distributed via the wiring generates the first clock signal and distributes the first clock signal to a large number of circuits in the plurality of circuit blocks.

According to the above clock distribution means, the first circuit (second PLL circuit) in the semiconductor integrated circuit is mounted on each circuit block (101) via the wiring.
The clock signal input to the PLL circuit (103) of
End distribution destination (113) in each circuit block (101)
Since the frequency can be set to a frequency lower than that of the clock signal input to the circuit block, it is possible to reduce the number of stages of the relay buffer connected to the path through which the clock signal propagates up to the first PLL circuit (103) of each circuit block.

[2] The first and second PLL circuits each include a power supply stabilization circuit, the power supplies supplied to the power supply stabilization circuit are commonly connected, and the commonly connected power supplies are the power supply stabilization circuit. Power is supplied from the outside via the power supply terminal provided separately from the circuit that does not have. The power supply stabilization circuit supplies power to the voltage controlled oscillator in the first and second PLL circuits. In this way, the power supply terminal of the voltage controlled oscillator that requires a stable power supply is shared, and one set is provided in addition to the power supply terminal that supplies power to other circuits, so that a stable power supply is supplied to the voltage controlled oscillator. You can Since the current flowing through the voltage controlled oscillator in the PLL circuit is small and the current does not suddenly increase or decrease, the number of power supply terminals can be small.
Further, since the power supply stabilization circuit mounted in the PLL circuit can stabilize the power supply inside, the power supply supplied to the voltage controlled oscillator can be further stabilized.

[3] It is preferable that the wiring that distributes the third clock signal from the circuit that suppresses the deterioration of the third clock signal to the plurality of circuit blocks has the same wiring width and wiring length. Further, a wiring for feeding back a signal from the circuit for suppressing deterioration of the third clock signal to the first circuit which is the second PLL circuit is provided, and this wiring and the circuit for suppressing deterioration of the third clock signal. Therefore, the wiring width and the wiring length of the wirings for distributing the third clock signal to the plurality of circuit blocks may be equal to each other. According to this, the phase of the clock signal input from the outside to the second PLL circuit can be matched with the phase of the clock signal input to the terminal distribution destination in all the circuit blocks in the semiconductor integrated circuit. Further, the clock net in the semiconductor integrated circuit can be designed for each circuit block.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a schematic diagram of the present invention. In FIG. 1, 100 is an LSI, 101 is a circuit block mounted on the LSI 100 and having a predetermined logic function, 10
2 is a PLL circuit as a first circuit mounted to receive a second clock signal CLK2 input from the outside,
103 is a PLL circuit mounted on each circuit block 101,
Reference numerals 104 to 106 are relay buffers (circuits for suppressing deterioration of clock signals), 107 is a wiring connecting the PLL circuit 102 and the relay buffer 104, and 108 is the relay buffer 104 and the PLL circuit 103 mounted in each circuit block 101.
Wirings for connecting the circuit blocks 109 to the circuit blocks 101
Inside, wiring connecting the PLL circuit 103 and the relay buffer 105, 110 is each wiring connecting the relay buffer 105 and the relay buffer 106 in each circuit block 101, 111 is the relay buffer 104 to the PLL circuit 10.
2 is a wiring for transmitting a feedback signal to 2; 112 is a wiring for transmitting a feedback signal from the relay buffer 106 to the PLL circuit 103; and 113 is a circuit block 101.
A terminal clock distribution destination (for example, a flip-flop circuit or the like) mounted inside is denoted by 114, each wiring connecting the relay buffer 106 and each terminal distribution destination 113, and 115 is a wiring for propagating a clock signal input from the outside. .

In this circuit, the second clock signal CLK2 having a frequency lower than that of the first clock signal CLK1 input into each circuit block 101 is externally input to the PLL circuit 102 via the wiring 115. The third clock signal CLK3 output from the PLL circuit 102 is supplied to the wiring 107.
Through the relay buffer 104. The clock signal output from the PLL circuit 102 has a frequency obtained by multiplying the frequency of the clock signal input from the outside by a predetermined integer, or the same frequency as the clock signal input from the outside. The third clock signal CLK3 has a lower frequency than the first clock signal CLK1.

Relay buffer (clock buffer) 104
The clock signal that has passed through the wiring 111 or the wiring 108 reaches the PLL circuit 102 or the PLL circuit 103 at the same time. The wirings 108 are provided in one-to-one correspondence with the individual PLL circuits 103 starting from the relay buffer 104. PLL circuit 1 receiving the clock signal
03 outputs a clock signal to the relay buffer (clock buffer) 105. Note that the clock signal output from the PLL circuit 103 passes through the wiring 108 and the PLL circuit 1
The frequency is a frequency obtained by multiplying the frequency of the clock signal input to 03 by a predetermined integer. The clock signal input to the relay buffer 105 propagates to each relay buffer 106, and the distribution destination 113 at the end in the circuit block 101 or the PLL circuit 1
Propagate to 03. Note that the relay buffer can be configured by, for example, an inverter circuit assigned to each wiring 108. Further, the wiring 108 and the wiring 111 from the relay buffer 104 to the PLL circuit 103 and the wiring 111 from the relay buffer 104 to the PLL circuit 102 are designed to have the same wiring width and wiring length so that the propagation times are equal to each other. The wirings 110 from the relay buffer 105 to the relay buffer 106 are designed to have the same wiring width and wiring length so that the transmission times are the same in each circuit block 101. The wiring 114 from the relay buffer 106 to the distribution destination 113 at the end and the relay buffer 10
The wiring 112 from 6 to the PLL circuit 103 is designed to have the same wiring width and wiring length so that the transmission times are equal in each circuit block 101.

The operation of the circuit for clock distribution shown in FIG. 1 will be described. The PLL circuit 102 which receives the clock signal CLK2 having a frequency lower than that of the clock signal CLK1 used in each circuit block 101 from the outside,
The clock signal CLK3 generated by multiplying the frequency of the clock signal CLK2 input from the outside by a predetermined integer is generated to generate the wiring 1
It outputs to 07. The clock signal CLK3 is propagated to the relay buffer 104, passes through the wiring 108 or the wiring 111, and reaches the PLL circuit 103 or the PLL circuit 102 at the same time. Due to the action of the PLL circuit 102, the phase of the feedback signal received by the PLL circuit 102 via the wiring 111 matches the phase of the clock signal CLK2 input to the PLL circuit 102 from the outside through the wiring 115. Further, since the wirings 108 and 111 have the same propagation time, the phase of the clock signal CLK3 input to the PLL circuit 103 mounted on each circuit block 101 is also the phase of the clock signal input to the PLL circuit 102 from the outside. It matches the phase of CLK2. The PLL circuit 103 generates a clock signal CLK1 by multiplying the frequency of the input clock signal CLK3 by a predetermined integer and outputs the clock signal CLK1 to the wiring 109. The clock signal CLK1 is transmitted to the relay buffer 105.
Is transmitted to the relay buffer 106 through the wiring 112 or 114 and reaches the PLL circuit 103 or the distribution destination 113 at the end at the same time. The operation of the PLL circuit 103 causes the PLL circuit 103 to pass through the wiring 112.
The phase of the feedback signal received by the clock signal CLK3 is input to the PLL circuit 103 through the wiring 108.
Match the phase of. Further, since the wiring 114 and the wiring 112 have the same propagation time, the phase of the clock signal CLK1 received by the distribution destination 113 at the end passes through the wiring 108 and is PL.
The phase matches the clock signal CLK3 input to the L circuit 103. That is, the phase of the clock signal CLK1 received by the distribution destination 113 at the end passes through the wiring 108 and the PLL.
This matches the phase of the clock signal CLK3 input to the circuit 103, and further matches the phase of the clock signal CLK2 input to the PLL circuit 102 from the outside.

As described above, the PLL circuit 102 outputs the clock signal CLK3 obtained by multiplying the frequency of the clock signal CLK2 input from the outside by a predetermined integer to the LSI1.
00, and the frequency of the supplied clock signal CLK3 is multiplied by a predetermined integer multiple by the PLL circuit 103, and the multiplied clock signal CLK1 is used for synchronous operation inside each circuit block 101. That is, the clock signal CLK3 propagating in the LSI 100 over a long distance may have a lower frequency than the clock signal CLK1 used in each circuit block 101. Therefore, the number of stages of the relay buffer can be reduced in the propagation path from the PLL circuit 102 to the PLL circuit 103,
It is possible to mitigate the increase in skew that occurs when the number of stages of the relay buffer is increased as in JP-A-5-233092. In addition, a clock signal CL input from the outside
K2 is a clock signal CL propagating in the LSI 100
A frequency lower than K3 is sufficient. Further, the clock signal whose phase matches that of the clock signal input to the PLL circuit 102 from the outside is distributed to the distribution destinations 113 at the respective ends in each circuit block 101. The wirings from the relay buffer 104 to the PLL circuit 102 via the wiring 111 and to the PLL circuit 103 via the wiring 108 are of equal length and width, and each circuit block 101
From the relay buffer 106 in the
Since each wiring of the path to the L circuit 103 and the path to the terminal distribution destination 113 via the wiring 114 has the same length and equal width, the terminal distribution destination 113 in all the circuit blocks 101 has an external A clock signal whose phase matches the clock signal input to the PLL circuit 102 from is transmitted. In this case, it is not necessary to match all the wirings for transmitting the clock signals in all the circuit blocks 101 to the same delay time as in the known example of P. Ramanathan et al.

FIG. 2 shows an example of the arrangement of power wiring and power terminals. In FIG. 2, reference numeral 200 denotes PLL circuits 102 and 1.
Power supply terminal for supplying power to the voltage controlled oscillator in 03,
201 is a power supply terminal for supplying power to other circuits, 2
Reference numeral 02 is a wiring connecting the power supply terminal 200 and the voltage controlled oscillator in the PLL circuits 102 and 103, and 203 is the power supply terminal 20.
It is a wiring that connects 1 and other circuits. The power supply terminal 200 and the power supply wiring 202, and the power supply terminal 201 and the power supply wiring 203 in the figure respectively represent a pair of a high-potential-side power supply and a low-potential-side power supply.

Since the voltage controlled oscillator mounted on the PLL circuits 102 and 103 needs to supply a stable power source, the power source wiring and the power source terminal are the PLL circuits 102 and 1.
Power supply wiring 202 and power supply terminal 20 for supplying power to
0 and power supply wiring 203 for supplying power to other circuits
And a power supply terminal 201. It should be noted that the power supply terminals 201 for supplying power to most of the circuits are necessary because many currents flow, but the PLL circuits 102 and 10 are required.
Power supply terminal 2 that supplies power only to the voltage-controlled oscillator in 3
Since 00 usually has a smaller current than the others, only one set may be used.

A common power source is supplied to the power source terminals 200 and 201 from the outside. The power supplied to the power supply terminal 201 is supplied to many circuits in the LSI 100 through the wiring 203. A large amount of current flows through the power supply due to switching operations of a large number of circuits, and the current fluctuates, which causes noise in the power supply. Further, the power supplied to the power supply terminal 200 is supplied to the voltage controlled oscillator in the PLL circuits 102 and 103 through the wiring 202. Since the current flowing through the voltage controlled oscillator is small and the current does not suddenly increase or decrease, no large noise is generated in this power supply and it is stable. It should be noted that the power supply terminal 201 and the wiring 203 are further divided into two systems, that is, a group that supplies power to an output driver that generates larger noise and a group that supplies power to an internal logic that requires stable power to some extent. Things are possible.

Next, the power supply stabilizing circuit mounted on the PLL circuits 102 and 103 will be described. FIG. 3 shows an example of the power supply stabilizing circuit. In FIG. 3, 300 is p
A channel type MOS transistor, 310 is a voltage controlled oscillator, 320 is a reference voltage generating circuit, 330 is a differential amplifier circuit which functions as a voltage comparison circuit, 370 is a high potential side of a power supply supplied from the outside, 360 is supplied from the outside Is a low potential side of the power supply, 371 is a high potential side of the power supply applied to the voltage controlled oscillator 310, and 373 is a node serving as a reference voltage. Further, 311 is a capacitive element for removing a component that fluctuates in a short cycle in the voltage fluctuation of the power supply applied to the voltage controlled oscillator 310, 321 to 323 are resistance elements constituting the reference voltage generation circuit 320, and 324 is a reference voltage. It is a capacitive element that constitutes the generating circuit 320. Of these, the resistance elements 321 and 322 form a voltage dividing circuit, and the resistance element 323 and the capacitance element 324 form a low-pass filter. 374 is a p-channel MOS transistor 300
Of the gate electrode of. High potential side of the power source 37
0 and the low potential side 360 are supplied via the power supply wiring 202 of FIG.

The operation of the power supply stabilizing circuit will be described. Three
The node voltage of 72 is a voltage obtained by dividing the power supply voltage applied between the nodes of 370 and 360 by the voltage dividing circuit by the resistance elements 321 and 322, and the power supply voltage applied between the nodes of 370 and 360 changes. Then 37
The voltage between the 2 and 360 nodes also varies.

The node voltage of 373 is a voltage obtained by smoothing the node voltage of 372 with a low-pass filter formed by the resistance element 323 and the capacitive element 324. Even if the power supply voltage applied between the nodes 370 and 360 changes. 373 and 3
The voltage between the 60 nodes does not change suddenly,
It slowly changes with the product of the resistance value of 23 and the capacitance value of the capacitive element 324 as a time constant.

When the voltage at the node 371 is lower than the voltage at the node 373, the relationship between the voltage at the node 371 and the voltage at the node 373 is 37 due to the action of the differential amplifier circuit 130.
The voltage of the node of No. 4 decreases, the current flowing through the p-channel MOS transistor 300 increases, and the voltage of the node of 371 increases. Conversely, if the voltage at the node 371 is higher than the voltage at the node 373,
The voltage of the node of 374 rises and the p-channel type MO
The current flowing through the S-transistor 300 decreases, and the voltage of the node 371 drops. Therefore, when the voltage of the node 371 and the voltage of the node 373 become substantially equal, they are balanced and stable. At this time, 3
There is no particular limitation on the relationship between the voltage of the node 74 and the voltage of the node 371, and the voltage of the node 374 can be designed to be approximately the same as or lower than the voltage of the node 371.

In order for the node voltage of 371 to substantially follow the node voltage of 373, it is sufficient that the current flowing through MOS transistor 300 is always saturated. Therefore, the difference between the power supply voltage supplied to the node 370 from the outside and the voltage at the node 371 applied to the voltage controlled oscillator 310 may be the drain-source voltage required to flow the saturation current in the MOS transistor 300. . MOS
By increasing the gate width of the transistor 300, this voltage can be set to about 10% of the power supply voltage.

In the power supply stabilizing circuit of FIG. 3, when the current flowing through the MOS transistor 300 changes suddenly, the voltage applied to the MOS transistor 300 changes. Therefore, it is better to keep this current as constant as possible. The voltage is obtained. The capacitive element 311 is an element provided for that purpose, and in the current flowing through the voltage controlled oscillator 310, the high frequency component that changes in a short cycle is the capacitive element 31 1.
1 is charged and discharged to compensate for the MOS transistor 30.
It acts to keep the current flowing to 0 constant.

By using the power supply stabilizing circuit described in FIG. 3, even if the power supply voltage applied between the nodes 370 and 360 changes suddenly, the voltage applied to the voltage controlled oscillator 310 does not change suddenly. can do.

FIG. 4 shows another example of the power supply stabilizing circuit. The circuit of FIG. 4 is a circuit in which the p-channel type MOS transistor 300 of FIG. 3 is replaced with an n-channel type MOS transistor and the polarities thereof are exchanged. In FIG. 4, 400 is an n-channel MOS transistor, 42
Reference numeral 3 is a resistance element, and 430 is a differential amplifier circuit functioning as a voltage comparison circuit. The voltage of the nodes 372 and 373 on both ends of the resistance element 323 of FIG. 3 is close to the power supply voltage on the high potential side applied to the node of 370, while the resistance element 42 of FIG.
The voltages of the nodes 362 and 363 on both ends of 3 are close to the power supply voltage on the low potential side applied to the node of 360. Therefore, in order to obtain a stable resistance value, the resistance element 423 uses the resistance between the source and drain of an n-channel type MOS transistor having a long gate length and a narrow gate width, and connects its gate electrode to the node of 370. It is composed of Further, in the differential amplifier circuit 330 of FIG. 3, the voltage applied to the nodes of the inputs 371 and 373 is close to the power supply voltage on the high potential side applied to the node of 370, whereas the voltage of the differential amplifier circuit 430 of FIG. The voltage applied to the input nodes 361 and 363 becomes close to the low-potential-side power supply voltage applied to the node 360. The operation of the circuit of FIG. 4 is the same as the circuit of FIG. 3 except that the polarities are different.

As described above, in the semiconductor integrated circuit, the PL
Since the current flowing through the voltage controlled oscillator in the L circuits 102 and 103 is small and the current does not increase or decrease suddenly, the number of power supply terminals 200 can be small. In addition, the PLL circuit 1
When the power supply stabilization circuit is mounted on 02 and 103, the power supply can be stabilized internally, so that the power supply applied to the voltage controlled oscillator can be further stabilized. Further, when the PLL circuits 102 and 103 are composed of a digital control circuit as in most of the circuits other than the voltage-controlled oscillator as disclosed in, for example, Japanese Unexamined Patent Publication No. 09-074352, the digital control circuit does not require a particularly stable power source. Since no large noise is generated, power can be supplied from either the power supply terminal 200 or the power supply terminal 201.

Each circuit block 101 shown in the example of FIG.
In the case where the wirings 109 and 110 are wirings of equal length and width, even if the delay time is set for each circuit block 101, the phase of the clock signal CLK3 input to each PLL circuit 103 via the wiring 108 At the end of distribution destination 1
The phases of the clock signal CLK1 input to 13 match. Therefore, it is not necessary to match all the wirings for propagating the clock signals in all the circuit blocks 101 with the same delay time, and each circuit block 101
Even if the delay time suitable for the size of
The phase of the clock signal CLK3 input to each PLL circuit 103 via 08 is the same as the phase of the clock signal CLK1 input to the terminal distribution destination 113 in the circuit block 101. In this case as well, the phase of the clock signal CLK2 input to the PLL circuit 102 from the outside through the wiring 115 matches the phase of the clock signal CLK3 input to the PLL 103 through the wiring 108, so that the distribution destination at the end is distributed. The phase of the clock signal CLK1 input to 113 is also
It matches the phase of the clock signal CLK2 input to the PLL circuit 102 from the outside through the wiring 115.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

In the case of the example of FIG. 1, the PLL circuits 102 and P
Due to the action of the LL circuit 103, the clock signal CLK3 input to each PLL circuit 103 via the wiring 108 and the clock signal input to the distribution destination 113 at the end are input to the phase of the external clock signal CLK2 input to the PLL circuit 102. Since the phases of CLK1 match, the adjacent LSI
It is also possible to match the phases of the distribution destinations at the ends in the circuit block inside. If it is not necessary to match the phases of the adjacent LSIs as described above, the PLL circuit 1
02 can be replaced with a relay buffer such as an inverter. That is, the first circuit may be composed of a simple clock driver such as an inverter. In addition, the third clock signal may have the same frequency as the second clock signal.

Further, in the example of FIG. 1, the phases are matched by the PLL circuits 102 and 103 and the frequency is set to a predetermined integral multiple, but the frequency is not particularly limited to the PLL circuit.
Any circuit may be used as long as it can match the phases of the input signal and the output signal and can multiply the frequency by a predetermined integer.

In the example of FIG. 2, either the high-potential-side power source or the low-potential-side power source can share the voltage-controlled oscillator with the other circuits. Also,
Although the power supply terminal for supplying power to the voltage controlled oscillators in the PLL circuits 102 and 103 and the power supply terminal for supplying power to the other circuits are separated, each PLL circuit 102
When a power supply stabilizing circuit is mounted in the power supply circuits 103 and 103, it is possible that the power supply terminals need not be separated.

The present invention can be applied to various semiconductor integrated circuits such as memories, microcomputers and microprocessors which are operated in synchronization with a clock signal.

[0039]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the clock distribution circuit of the present invention, the first PLL circuit mounted in each circuit block is routed from the first circuit (second PLL circuit) in the semiconductor integrated circuit to the wiring. The input clock signal can be set to a frequency lower than that of the clock signal input to the distribution destination at the end in each circuit block, so that the first circuit (second P
It is possible to reduce the number of stages of the relay buffer or the clock buffer connected to the path through which the clock signal propagates from the LL circuit) to each of the first PLL circuits. In this way, since the number of stages of the relay buffer can be reduced, it is possible to alleviate the skew caused by the relay buffer and distribute the clock signal.

First circuit from outside (second PLL circuit)
It is possible to match the phase of the clock signal input to the terminal with the phase of the clock signal input to the terminal distribution destination in all the circuit blocks in the semiconductor integrated circuit. Therefore, the clock net in the semiconductor integrated circuit can be designed for each circuit block.

Further, by providing a common power supply terminal for a circuit requiring a stable power supply and providing one set other than the power supply terminal for supplying power to other circuits, a stable power supply is supplied to the voltage controlled oscillator of the PLL circuit. You can do it. By mounting the power supply stabilization circuit in the PLL circuit, the power supply can be further stabilized in the circuit, and the number of power supply terminals can be suppressed to distribute the clock signal.

[Brief description of drawings]

FIG. 1 is a layout diagram showing an example of a clock distribution circuit in a semiconductor integrated circuit of the present invention.

FIG. 2 is an explanatory diagram showing a detailed example of an arrangement configuration of power supply wirings and power supply terminals in FIG.

FIG. 3 is a circuit diagram showing an example of a power supply stabilization circuit mounted on a PLL circuit.

FIG. 4 is a circuit diagram showing another example of a power supply stabilization circuit mounted on a PLL circuit.

[Explanation of symbols]

1 LSI chip 101 Circuit block having predetermined logical function 102, 103 PLL circuit 104-106 relay buffer 107-112, 114, 115 wiring 113 end distribution destination 200,201 Power supply terminal 202, 203 wiring

Continuation of front page (56) Reference JP-A-3-161815 (JP, A) JP-A-2-246422 (JP, A) JP-A-11-15541 (JP, A) JP-A-2-350 (JP , A) Actual Kaihei 5-92820 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 1/08

Claims (5)

(57) [Claims] 1. A semiconductor integrated circuit comprising a plurality of circuit blocks each having a predetermined circuit to which a first clock signal is input, the second clock having a frequency lower than that of the first clock signal from the outside. A first circuit for receiving a signal, a wiring for distributing a third clock signal having a frequency lower than the first clock signal from the first circuit to the plurality of circuit blocks, and each of the plurality of circuit blocks A first PLL circuit that is mounted and that generates the first clock signal from the third clock signal, wherein the first clock is supplied from the first PLL circuit to a large number of circuits in the plurality of circuit blocks. all SANYO for distributing signals, said first and second PLL circuits voltage built respectively
Equipped with a power supply stabilization circuit that supplies operating power to the controlled oscillator
The power supply wiring to each of the power supply stabilization circuits above should be connected in common.
In addition, the power supply wiring connected in common above stabilizes the power supply.
Via a power supply terminal provided separately from the circuit that does not have a circuit,
Characterized by being supplied with power from the outside
Semiconductor integrated circuit. 2. A circuit for suppressing deterioration of the third clock signal is provided in the middle of the wiring, and the third clock signal is provided from the first circuit to the plurality of circuit blocks via the circuit for suppressing. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is distributed. 3. The semiconductor integrated circuit according to claim 1, wherein the first circuit is a second PLL circuit. 4. The power stabilizing circuit is supplied from the outside.
Voltage generation circuit that generates a reference voltage using a power supply
And a power supply and a voltage controlled oscillator supplied from the outside
The transistor inserted in series between the
Voltage comparison comparing the voltage applied to the oscillator and the reference voltage
It has a circuit and the
By controlling the conductance of the transistor
Keep the voltage applied to the voltage controlled oscillator constant.
Circuit, wherein the transistor is supplied from the outside.
Between the high potential side of the power supply and the voltage controlled oscillator
Inserted p-channel MOS transistor, or
Low-side power supply and voltage control of the power supply supplied from the outside
N-channel type MOS inserted between the oscillator Trang
4. The semiconductor collection according to claim 3, wherein the semiconductor collection is a transistor.
Product circuit. 5. The reference voltage generating circuit is supplied from the outside.
Voltage divider circuit that divides the power source
A low-pass filter that smoothes the output voltage of the voltage divider
5. The half according to claim 4, characterized in that
Conductor integrated circuit.