JP3498393B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlayer alignment method in a lithography process, and more particularly to a method of manufacturing a semiconductor device capable of preventing characteristic deterioration of the semiconductor device due to misalignment.

[0002]

2. Description of the Related Art A conventional inter-layer alignment method in a lithographic process is, for example, as described in JP-A-2-39534, desired processing is carried out using an active region defining layer and LOCOS oxidation is carried out to carry out element isolation regions. Then, the gate electrode region defining layer is aligned with the active region defining layer by using the interlayer alignment pattern for position information having the LOCOS oxide film step created at that time, and the desired processing is performed to form the gate electrode. After forming the passivation film, a method of forming a wiring layer by processing the passivation film by aligning the connection hole region defining layer with the active region defining layer using the position information interlayer aligning pattern having a LOCOS step is used. . On this occasion,
In each interlayer alignment, the same positional information interlayer alignment pattern was used as a reference in both the x and y directions. Also,
In the method of manufacturing a semiconductor device described in JP-A-6-61486, the passivation film is processed in conformity with the gate electrode region defining layer using the position information interlayer alignment pattern having the gate electrode step difference in the connection hole region defining layer. The method of forming an electrode layer was used. In this case as well, in each interlayer alignment, the same positional information interlayer alignment pattern is used as a reference in both the x and y directions.

[0003]

In the conventional method of manufacturing a semiconductor device having the above-mentioned lithography process, in the side of the pattern shape of the active region defining layer, the side of the pattern having the longer total length and the pattern shape of the gate electrode region defining layer are formed. Although the sides are orthogonal to the side with the longest length, there is always a layer misalignment, so if the connection hole area defining layer is aligned using the position information of the active area defining layer, the connection hole area defining layer and the gate will be aligned. The misalignment with the electrode region defining layer becomes large, and the possibility that the connection hole will come off the gate electrode becomes large. In order to prevent this, the gate electrode region defining layer is formed in a large pattern in the portion where the connection hole region defining layer is present, in consideration of the misalignment between the connection hole region defining layer and the gate electrode region defining layer. As a result, there is a problem that miniaturization is hindered to that extent. Furthermore, if the connection hole region defining layer is aligned using the position information of the gate electrode region defining layer, the misalignment between the connection hole region defining layer and the active region defining layer becomes large, and the connection hole is formed from the source / drain region of the active region. There is a greater chance of it coming off. As a result, the leakage current of the source / drain junction becomes very large. Usually, in order to prevent this, an impurity having the same conductivity type as that used for forming the source / drain regions is introduced after processing the connection hole. When such impurities are introduced, the source / drain junctions of the elements whose source / drain junctions are close to each other are brought close to each other, so that the element isolation characteristics are deteriorated and the LOCO
Since the metallurgical junction position of the source / drain region is formed in the conductive type layer having a relatively high concentration different from the source / drain region immediately below the S oxide film, there is a problem that the junction breakdown voltage is lowered. Furthermore, there is a problem that the semiconductor device manufacturing process becomes complicated because the number of extra impurity introducing processes increases.

An object of the present invention is to provide a method of manufacturing a semiconductor device which solves the above-mentioned conventional problems, prevents characteristic deterioration of the semiconductor device due to misalignment, and eliminates barriers to miniaturization / addition of steps. It is in.

[0005]

Means for solving the above problems will be described with reference to FIGS. 1 and 2.

The above-mentioned purpose is for the first, second and third exposures.
First, second and third patterns respectively formed on the mask
Of semiconductor devices, including the step of sequentially transferring the devices onto the substrate.
In the manufacturing method, the second pattern is the position of the first pattern.
Positioning process using placement information and the first putter
Position information of either the second pattern or the second pattern
The step of aligning the third pattern in the x direction
And a pattern different from the pattern used for alignment in the x direction.
Alternatively, by using the position information of the second pattern, the third pattern
Achieved by performing the y-direction alignment of the
It

Here, the first, second, and third patterns have a shape surrounded by straight sides along the x direction and the y direction, respectively, and the first pattern has a second shape in the x direction.
Pattern extends along the y-direction, and the first, second,
When performing alignment between the third patterns, the second pattern is aligned using the positional information of the first pattern, and the straight side along the x direction of the third pattern is the first pattern. Of the third pattern, and the straight side of the third pattern along the y direction is aligned using the position information of the second pattern.

The rotation of the third pattern is adjusted as follows.
Position of either the first pattern or the second pattern
The process of matching using information, or the first pattern
And the position information of the second pattern is processed and combined.
Match using the location information obtained.

Further, each pattern has an x direction and
Active with a shape surrounded by straight sides along the y direction
The area pattern is in the x direction and the electrode area pattern is in the y direction.
When extending and aligning between each pattern,
The area pattern uses the position information of the active area pattern
Alignment, the alignment of the connection hole area pattern
The position information of the connection hole area pattern in the x direction and the electrode area pattern
Performed using the position information of the turn, and the connection hole area pattern
Is aligned with the y-direction position of the connection hole area pattern.
Information and the position information of the pattern of the active area
It

Alignment of connection hole area pattern
Indicates the position information of the connection hole area pattern in the x direction and the active area.
The connection is performed at the same time by using the position information of the pattern of the area.
Position information of hole area pattern in y direction and pattern of electrode area
Using the location information of the
I don't mind.

The exposure apparatus having the alignment function as described above is used in a semiconductor manufacturing method.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION First pattern 1 and second pattern
When the interlayer alignment is performed between the second pattern 3 and the third pattern 3, when the second pattern 2 is aligned using the positional information of the first pattern 1, there is always a deviation in the x direction, the y direction, and the rotation. . At that time, the average value of each misalignment of the second pattern 2 with respect to the first pattern 1 is Δx.
_1-2 , Δy _1-2 and Δθ _1-2 . In this case, the third path
When the x direction and the rotation of the turn 3 are aligned by using the position information of the second pattern 2 and the y direction of the third pattern 3 is aligned by using the position information of the first pattern 1, the alignment is performed. The average value of the deviations is Δx _2-3 and Δθ _2-3 with respect to the x direction and rotation of the second pattern 2,
It is assumed that Δy _1-3 is in the y direction of pattern 1. Therefore, the misalignment in the x direction and the rotation of the third pattern 3 is Δx _2-3 and Δθ _2-3 with respect to the second pattern 2,
The deviation of the third pattern 3 in the y direction is Δy _1-3 with respect to the first pattern . When implemented by the above conventional method,
The deviation of the pattern 3 in the x direction and the rotation is Δx _1-2 + Δx _2-3 and Δθ _1-2 + Δθ _2-3 with respect to the second pattern 2, and the deviation of the third pattern 3 in the y direction is the third. 1 putter
, Δy _1-2 + Δy _2-3 . Thus, the third
Reduce the misalignment of the second x-direction and rotation with respect to the pattern 2 pattern 3, also when it is desired to reduce the deviation in the x direction with respect to the first pattern 1 of the third pattern 3, is effective invention I know there is.

In particular, as shown in FIG. 1, the x direction of the third pattern is relative to the second pattern , and the third pattern is
When it is necessary to reduce the misalignment in the y direction of the pattern with respect to the first pattern , as described above, the first direction in which the long side of the entire length of the side of the pattern is the x direction. Pattern 1, the second pattern 2 and the third pattern 3 in which the long side direction of the entire side of the pattern is the y direction, the second pattern is the position information of the first pattern . To align the x direction of the third pattern 3 using the positional information of the second pattern 2, and the y direction of the third pattern 3 to the positional information of the first pattern 1. You can see that it is good to do it together. The third path
The combined rotation of the turn 3 the first pattern 1 or the second path
By using any one of the position information of the turn 2 to adjust, it is possible to adjust to the one where the misalignment is a problem. Alternatively, the rotation can be aligned by using the positional information synthesized by processing the positional information of the first pattern and the second pattern .

[0014] For example, the active region pattern 4 total length of the sides of the pattern is long-side direction is the x direction, the electrode area the entire length of the sides of the pattern is long side direction y direction pattern 5 and the connecting hole region patterns 6 and 7 When performing interlayer alignment between the electrode regions, the electrode region pattern 5 is aligned using the position information of the active region pattern 4, the x direction of the connection hole region pattern 6 is aligned using the position information of the electrode region pattern 5,
Further, the y direction of the connection hole area pattern 6 is set to the active area pattern.
Use the position information of Point 4 to match. Here, the x direction of the connection hole region pattern 7 is aligned using the position information of the active region pattern 5, and the y direction of the connection hole region pattern 7 is aligned using the position information of the electrode region pattern 4. May be used. As a result, the connection hole 6
The probability that 7 and 7 will be off the eye from the portion surrounded by the active region and the electrode region is very small. As a result, the alignment margin can be increased, so that miniaturization can be promoted, a semiconductor device manufacturing method with less characteristic deterioration and no additional processes can be realized. It should be noted that the x direction used in the description of the present invention may be the y direction or the y direction may be the x direction depending on the crystal orientation reference of the semiconductor substrate used and the axis reference of the exposure apparatus used in the lithography method. .

By using the exposure apparatus having the alignment function as described above in the semiconductor manufacturing method, it is possible to perform arbitrary alignment, and it is possible to produce a semiconductor device with a large alignment margin. Further, it is obvious that not only the method of manufacturing a semiconductor device using the exposure apparatus having this function but also the semiconductor device manufactured by using the method is within the scope of the present invention.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a dynamic random access memory device which is an embodiment of the present invention will be described with reference to FIGS. 2 is a plan view of only the memory cell, and FIG. 3 (a) is a cross-sectional view taken along the line AB of FIG.
FIG. 3B is a CD sectional view of FIG. Here, a manufacturing method for forming a memory cell will be described.

LOCO is formed on the main surface of the p-type Si substrate 8 by using ordinary selective oxidation so as to form the pattern of the range defining layer 4.
The S oxide film 9 was formed. At this time, the alignment pattern having the step of the LOCOS oxide film 9 is formed. Then, L
The buried p-type layer 10 was formed so that the p-type impurity concentration immediately below the OCOS oxide film 9 was high. After that, a gate oxide film 11 and a polycrystalline Si film 12 for a gate electrode are formed, and the pattern of the range defining layer 5 is changed to the LOCOS oxide film 9 described above.
The polycrystalline Si film 12 for a gate electrode is processed by using the positional information of the alignment pattern having the step of the above, and using the lithography method in which the alignment pattern position of the range defining layer 4 is aligned with the target position determined relative to the alignment pattern position. did. At this time, a matching pattern having a step of the polycrystalline Si film 12 for gate electrode is formed. Then, the n-type impurity introduction layer 13 is formed using the LOCOS oxide film 9 and the gate electrode polycrystalline Si film 12 as a mask to form the source / drain, and then the Si oxide film 14 is formed so as to surround the gate electrode polycrystalline Si film 12. Then, a Si oxide film 15 was formed. When forming a hole in the prescribed range 6 for forming the charge storage electrode 16 in the Si oxide film 15, alignment in the x direction is performed by using the polycrystalline Si film 1 for the gate electrode.
The positional information from the alignment pattern having two steps was used, and the alignment in the y direction was performed using the positional information from the alignment pattern having the LOCOS oxide film 9 step. The alignment in the rotational direction when forming the holes was performed by using information from the alignment pattern having the step of the polycrystalline Si film 12 for gate electrode. Here, in order to compare with the conventional method, the alignment of the hole drilling in the specified range 6 is performed in the x direction and the y direction.
An alignment pattern was also produced using the alignment pattern having the steps of the polycrystalline Si film 12 for the gate electrode in both directions. After that, a polycrystalline Si film 16 for the charge storage electrode 16 is deposited /
After processing, and further depositing the charge storage capacity insulating film 17, a charge holding polycrystalline Si film 18 was deposited and processed together with the charge storage capacity insulating film 17. Then, when the boron-added lin-calus film 19 is deposited and a hole is formed in the specified range 7 for forming the electrode wiring 20, the alignment in the x direction is performed from the alignment pattern having the step of the polycrystalline Si film 12 for the gate electrode. Position information is used, and the y-direction alignment is LOCO
The position information from the alignment pattern having the S oxide film 9 step was used. For the alignment in the rotational direction at the time of forming the hole, the positional information from the alignment pattern having the step of the polycrystalline Si film 12 for gate electrode was used. Next, the electrode wiring 20 was deposited / processed to fabricate a memory cell. Subsequent manufacturing steps were performed as usual.

In the lithography method used here, the reduction projection exposure apparatus was used for pattern formation, but the X-ray same-magnification exposure apparatus, X-ray reduction exposure apparatus, step scan type exposure apparatus, etc. are not particularly limited. The pattern alignment method uses reflected light from the alignment pattern provided in each chip formed on a substrate forming a semiconductor device, recognizes the position of the pattern, and uses this position data as a basis. A method of determining the chip arrangement of the alignment layer was used. In practice, a specific chip on the substrate is selected, and a global method that uses position data of a designated layer in this chip is used, but the present invention is not limited to this. A die-by-die system in which positioning is performed for each chip, or a combination of these systems is also applicable. Further, in the above embodiment, the x direction and the y direction are described as different targets, but the present invention is not limited to this.
When the target in the x direction and the target in the y direction are combined and formed, the part for obtaining the position information in the x direction or the part for obtaining the position information in the y direction may be divided and used. The position data was processed by an electronic computer.

According to the present invention, as compared with the conventional method shown in FIG. 4, as shown in FIG. 5, the amount of holes in the specified range 6 deviating from the active region in the specified range 4 can be reduced. Since the polycrystalline Si film 16 for the charge storage electrode 16 contains n-type impurities, the n-type impurities are affected by the heat treatment after the charge storage electrode 16 is formed, and the n-type impurities are introduced into the n-type impurity introduction layer 13.
Has spread beyond. Therefore, when the amount of the eye deviation increases, the electric field strength at the junction position becomes higher as the distance from the buried p-type layer 10 approaches. Further, since the n-type impurity introduction layer of the adjacent cell is also close to the cell, the element isolation capability is lowered. However, in the present invention, since the amount of deviation can be made small, the electric field strength can be made small, and the concentration of the buried p-type layer 10 can be made low while keeping the element isolation capability equivalent to that of the conventional one, so that the electric field strength can be further increased. I was able to make it smaller. As a result, as shown in FIG. 6, the information retention characteristic could be improved. By utilizing the effects as described above, various alignment margins can be secured and it has been possible to contribute to the miniaturization of the device by about 2%. It goes without saying that the degree of contribution to miniaturization is somewhat changed by changing the arrangement of cells.

[0020]

According to the present invention, not only the characteristic deterioration of the semiconductor device due to misalignment can be prevented but also the alignment margin can be increased, so that the miniaturization can be promoted without increasing the number of steps and the characteristics can be improved. Is effective.

[Brief description of drawings]

FIG. 1 is a plan view of a mating pattern for explaining a method of the present invention.

FIG. 2 is a plan view of a semiconductor device for explaining the method of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor device for explaining an embodiment of the present invention.

FIG. 4 is a plan view of a semiconductor device for explaining interlayer alignment according to a conventional method.

FIG. 5 is a plan view of a semiconductor device for explaining interlayer alignment in an example of the present invention.

FIG. 6 is a diagram for explaining characteristics of a semiconductor device manufactured by using the present invention.

[Explanation of symbols]

1,4 ... first pattern , 2,5 ... second pattern ,
3, 6, 7 ... Third pattern , 4 ... Active area pattern
Down, the pattern of 5 ... electrode region, 6, 7 ... pa connecting hole area
turn.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Osamu Okura 1-280, Higashi Koikekubo, Kokubunji, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd. (56) References JP-A-2-27711 (JP, A) JP-A-6 -29183 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/027 G03F 9/00

Claims (4)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising the steps of sequentially transferring first, second and third patterns respectively formed on first, second and third exposure masks onto a substrate, wherein: The second pattern is aligned using the position information of the first pattern, and the third pattern is formed by using the position information of any one of the first pattern and the second pattern. Position adjustment in the x direction and position adjustment in the y direction of the third pattern by using position information of the first or second pattern different from the pattern used for the x direction alignment. A method of manufacturing a semiconductor device, comprising: 2. A method of manufacturing a semiconductor device, comprising the steps of sequentially transferring first, second and third patterns respectively formed on first, second and third exposure masks onto a substrate, wherein: The first, second, and third patterns have a shape surrounded by straight sides along the x direction and the y direction, respectively. The first pattern extends in the x direction and the second pattern extends in the y direction. If the first pattern, the second pattern, and the third pattern are aligned, the second pattern is aligned using the positional information of the first pattern, and the x of the third pattern is aligned.
There is a step of aligning the straight side along the direction using the position information of the first pattern, and aligning the straight side along the y direction of the third pattern using the position information of the second pattern. A method of manufacturing a semiconductor device, comprising: 3. The rotation alignment of the third pattern is performed by using the positional information of any one of the first pattern and the second pattern, or the first pattern and 3. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of processing the positional information of the second pattern and matching the positional information using the synthesized positional information. 4. A method of manufacturing a semiconductor device, comprising the step of sequentially transferring, onto a substrate, an active region pattern, an electrode region pattern, and a connection hole region pattern, which are separately formed for each exposure mask. the active region pattern extends in the x direction, the electrode region pattern extends in the y direction, and the active region pattern extends in the x direction.
When performing alignment between the patterns, the electrode region pattern is aligned using the positional information of the active region pattern, and the alignment of the connection hole region pattern is performed in the x direction of the connection hole region pattern. The position information and the position information of the pattern of the electrode region are used to perform the alignment of the connection hole region pattern by y of the connection hole region pattern.
A method of manufacturing a semiconductor device, comprising the step of using position information of a direction and position information of a pattern of the active region.