JP3499766B2 - PLL lock determination circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
Locked Loop) lock determination circuit, especially PLL
Related to low power consumption.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing the configuration of a conventional PLL lock determination circuit. As shown in this figure, the PLL
The lock determination circuit of the pull-down transistor Tr.1 is configured by comparing the output Up and the output Down signal of the phase / frequency detector Det which is one of the components of the PLL. A
It is realized by outputting a signal for controlling and changing the analog potential of Node1. At this time, N
The potential of ode1 was gently changed by setting the time constant determined by the resistors R51 and R52 and the capacitance C51.

More specifically, the PLL has a function of comparing a reference clock with a comparison (feedback) clock and synchronizing the comparison (feedback) clock with the reference clock. However, when the power is turned on or the reference clock is changed. There is a time lag until the locked state is reached. At this time, a signal for monitoring the locked state and the unlocked state is required, and normally, the lock determination signal is controlled by the output of the phase / frequency detector.

The phase / frequency detector outputs the difference in frequency and phase between the reference clock and the comparison (feedback) clock U
p, output Down is detected. When there is a frequency difference and a phase difference, either the signal Up or Down is intermittently at the high level according to the difference, and the transistor Tr. A repeatedly turns on and off repeatedly. At this time, the transistor Tr. When A is on, the potential of the Node1 decreases with RC time constant: R51 × C51, and the transistor Tr. When A is off, the potential of Node1 rises with RC time constant: R52 × C51.

Up and Down as the locked state approaches
As the signal sporadically outputs a high level, the transistor Tr. The off state of A becomes longer. Transistor T
r. When the off state of A continues for a time of R52 × C51 or more, the potential of Node1 starts to gradually rise, and when it reaches Vdd / 2, the Lock terminal outputs a high level. Even after it is determined that the Lock terminal is at the high level and is in the locked state, the potential of Node1 gradually rises toward Vdd, and is in the intermediate potential state for a while.

[0006]

However, in the above-described method according to FIG. 5, when Node1 is at the intermediate potential before and after the lock determination, there is a time zone in which a through current flows through the gate driven by this potential, There was a problem of consuming electric power.

The present invention has been made under such a background. By raising the node potential immediately after the lock determination, the potential of Node1 is stabilized, the period during which the through current flows is shortened, and the power consumption is reduced. It is an object of the present invention to provide a PLL lock determination circuit that realizes the above.

[0008]

According to a first aspect of the present invention, there is provided a phase / frequency detector for comparing a reference signal and a comparison signal to generate a detection pulse according to a phase / frequency difference between the reference signal and the comparison signal, and the detection. lock the locked state of the PLL by pulse
Lock-size consisting of a lock determination circuit for determining the click judgment gate, a loop filter for outputting a smoothed to the oscillator control signal to said detection pulse, a voltage controlled oscillator for outputting a clock of a predetermined frequency by the oscillator control signal
In a PLL with a constant function , the lock determination circuit performs a lock determination, and immediately after the input signal of the lock determination circuit is determined to be in a locked state, the input level of the input signal of the lock determination gate at the intermediate potential is forced. pulled up to, a lock determination circuit of a PLL to reduce the through current of the lock determination gate, pull-up input level of the lock determination gate, <br/> input signal of the lock determination circuit locked state The delay circuit which starts the operation when it is determined that the pull-up transistor is turned on for a predetermined time is performed.
An LL lock determination circuit is provided.

According to a second aspect of the present invention, a phase / frequency detector that compares a reference signal with a comparison signal and generates a detection pulse according to a phase / frequency difference between the reference signal and the lock state of the PLL by the detection pulse. From a lock control circuit that outputs the oscillator control signal by smoothing the detection pulse, and the voltage control oscillator that outputs a clock of a predetermined frequency according to the oscillator control signal. In the PLL with the lock determination function , the lock determination gate is at the intermediate potential immediately after the lock determination circuit determines the lock and the input signal of the lock determination circuit is determined to be in the lock state. forcibly pulling up the input level of the signal, the lock determination circuit der the PLL to reduce the through current of the lock <br/> click judgment gate Therefore, the input level of the lock judgment gate is
The first delay circuit and the latch circuit, which start the operation when the input signal of the lock judgment circuit is judged to be in the locked state, are pulled up for a predetermined time, and the second circuit which starts the operation by the lock release judgment. Provided is a PLL lock determination circuit which is pulled down for a predetermined time by a delay circuit and a latch circuit.

[0010]

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a PLL lock determination circuit according to the present invention will be described below. 1 is a circuit diagram showing a configuration of a first embodiment of a PLL lock determination circuit according to the present invention, and FIG. 2 is a PLL according to the first embodiment of FIG.
3 is a timing chart showing the operation of the lock determination circuit of FIG.

In FIG. 1, P according to the prior art shown in FIG.
The same parts as those of the LL lock determination circuit are designated by the same reference numerals. 1 is substantially different from the conventional PLL lock determination circuit shown in FIG. 5 in that the pull-up transistor Tr. B (strong strength) and the pull-up transistor Tr. That is, the gates 7 and 9 for controlling the opening and closing of B and the delay circuit (Delay) 8 are additionally arranged.

First, immediately after the power is turned on, the PLL outputs the output U of the phase / frequency detector Det so as to follow the reference clock signal.
The level high is output from p. At this time, Node2 is at a high level and Node1 is at a low level. As the phase and frequency gradually follow the reference clock signal over time, the Up signal high level output becomes fragmentary, and the high level width of Node2 is gradually shortened, and the high level of Node2 is gradually reduced. Width and time constant R1 x C1
The potential of Node1 begins to rise at a speed determined by.

When the potential of Node1 becomes Vdd / 2,
The potential of the Node3 becomes high level via the inverters 5 and 6, and the lock signal is output. The potential of Node3 and the potential of Node3 are applied to the gate 7 of the gate 9 of FIG.
And a signal delayed by the delay in the delay circuit (Delay) 8 are input, and after the Node 3 is inverted to the high level, the transistor T is delayed for the delay period by the Delay 8.
r. The gate input of B becomes low level, and the potential of Node1 is raised to Vdd all at once. When the delay period elapses, the transistor Tr. The input potential of B is returned to the high level, and Node1 is free in preparation for the unlock determination.

In these configurations, the pull-up transistor Tr. By providing a pull-down transistor as in the case of B, it is possible to reduce the shoot-through current also when making a lock-unlock decision. Further, by optimizing the time constant of Node 1 in FIG. 1 on the pull-up side and the pull-down side of the inverter 4, it is possible to reduce the through current more effectively.

In the timing chart of each node in the above-described operation according to FIG. 2, Node1 has the potential shown by the solid line, and is pulled up when the Lock signal of Node3 is output. Incidentally, according to the conventional technology,
The potential changes shown by the dotted line.

Next, FIG. 3 shows the configuration of the second embodiment of the lock determination circuit of the PLL according to the present invention. In addition, FIG.
7 is a timing chart showing the operation of the PLL lock determination circuit according to the second embodiment. The operation of the second embodiment will be described by referring to these figures and following the state immediately after the power is turned on.

First, in FIG. 3, immediately after the power is turned on, the Up signal from the phase / frequency detector Det causes
Node2 is in the state of outputting the high level most of the time. At this time, since the Lock terminal (Node3) is at low level, Node8 is also at low level. Also, since Node9 is at a high level, the composite gates 31 and 32 are
Physically connects Node2 and Node4. Therefore, Node2 is in a state of being connected to the resistor R31.

When the phase and frequency of the reference clock and the comparison clock gradually match with the passage of time, N
When the potential of ode1 rises slowly and exceeds Vdd / 2, Node9 goes low and gates 34 and 35
Output Nod of the latch configured by
After e3 goes high and Node6 is delayed by the delay 38 due to the influence of Delay38, the input of Node7 outputs a low level for a delay period and then returns to a high level again.

At this low level time, the composite gate 31,
The force that pushes Node1 to a high level via 32 works (strength is stronger on the Node6 side), and after a certain time, this force becomes free as Node6 goes high. Since the output of the gate 39 is high level without change, the gate 32 remains open.

When the lock is released from the locked state, an Up or Down signal is output from the phase / frequency detector, and the potential of Node1 gradually starts to decrease. When the potential of Node1 becomes Vdd / 2, Node9
Is high level, Node5 is low level, Node6
Remains high.

Further, at this time, due to the action of the Delay 37, the output of the gate 39 is delayed by a low level,
Therefore, the gate 32 becomes Disable for a certain time,
At once, the potential of Node1 drops to the Gnd level (No.
Strong strength on the de10 side). The gate 32 becomes effective immediately and returns to the initial state.

In the timing chart shown in FIG.
The potential of Node1 is as shown by the solid line, and the potentials of the other Nodes have the waveforms shown in the figure. In this figure, it is shown when locked and when unlocked. In this way, Nod also applies to the second embodiment.
The transition time due to the intermediate potential of e1 can be shortened.

As described above, the first and second embodiments of the present invention
Although the operation of the above has been described in detail with reference to the drawings, the present invention is not limited to this embodiment, and a design change and the like within the scope not departing from the gist of the present invention are included in the present invention.

[0025]

As described above, the PLL according to the present invention
According to the lock determination circuit of, the pull-up transistor,
Alternatively, by mounting a latch, the intermediate potential node is pulled up to Vdd after the lock is determined, and Gnd is released after the lock is released.
As a result, the through-current of the inverter connected to the node is reduced, thereby reducing the power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing details of a first embodiment of a PLL lock determination circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of the lock determination circuit of the PLL according to the first embodiment of FIG.

FIG. 3 is a circuit diagram showing details of a second embodiment of a PLL lock determination circuit according to the present invention.

FIG. 4 is a timing chart showing the operation of the lock determination circuit of the PLL according to the second embodiment of FIG.

FIG. 5 is a circuit diagram showing a configuration of a PLL lock determination circuit according to a conventional technique.

[Explanation of symbols]

1, 2, 4, 5, 6, 33, 36, 40 ... Inverter 3, 7, 9, 34, 35, 39 ... NAND gate 8, 37, 38 ... Delay device (Delay) 31 ... AND gate 32 ... NOR gate 51 ... OR gate C1, C31, C51 ... Capacitor Det ... Phase / frequency detector R1, R31, R51 ... Resistance Tr. A, Tr. B ... Transistor

Continued front page       (56) Reference JP-A-9-214333 (JP, A)                 JP-A-9-120324 (JP, A)                 Japanese Unexamined Patent Publication No. 9-171698 (JP, A)                 JP 58-196730 (JP, A)                 JP-A-10-107610 (JP, A)                 JP-A-6-232639 (JP, A)                 JP-A-5-291888 (JP, A)                 JP 64-11420 (JP, A)                 JP 62-186617 (JP, A)

Claims (2)

(57) [Claims] 1. A locking phase-frequency detector for generating a detection pulse corresponding to the phase-frequency difference by comparing the reference signal and the comparison signal, the lock state of the PLL by said detection pulse-format
P with lock determination function, which includes a lock determination circuit that determines with a constant gate, a loop filter that smoothes the detection pulse and outputs an oscillator control signal, and a voltage-controlled oscillator that outputs a clock of a predetermined frequency according to the oscillator control signal
In LL, the lock determination circuit makes a lock determination and the lock
Forcibly pulling up the input level of the input signal of the lock determination gate in intermediate potential immediately after the input signal is determined to be in the locked state of the determination circuit, a PLL to reduce the through current of the lock determination gate In the lock determination circuit, the input level of the lock determination gate is pulled up by a delay circuit which starts operation when it is determined that the input signal of the lock determination circuit is in a locked state, and the pull-up transistor is pulled for a predetermined time. The lock determination circuit of the PLL is characterized in that it is performed only by turning it on. 2. A lock and the phase-frequency detector for generating a detection pulse corresponding to the phase-frequency difference by comparing the reference signal and the comparison signal, the lock state of the PLL by said detection pulse-format
P with lock determination function, which includes a lock determination circuit that determines with a constant gate, a loop filter that smoothes the detection pulse and outputs an oscillator control signal, and a voltage-controlled oscillator that outputs a clock of a predetermined frequency according to the oscillator control signal
In LL, the lock determination circuit makes a lock determination and the lock
Forcibly pulling up the input level of the input signal of the lock determination gate in intermediate potential immediately after the input signal is determined to be in the locked state of the determination circuit, a PLL to reduce the through current of the lock determination gate A lock determination circuit, wherein the input level of the lock determination gate is the lock determination
A second delay circuit that is pulled up for a predetermined time by a first delay circuit and a latch circuit that start operation when it is determined that the input signal of the circuit is in a lock state, and a second delay circuit that starts operation by lock release determination. P that is pulled down for a predetermined time by a latch circuit
LL lock determination circuit.