JP3499812B2 - DC stabilized power supply - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to stabilization of output voltage in a DC stabilized power supply device. In particular, it relates to stabilization of the output voltage by improving the phase margin of the DC stabilized power supply device.

[0002]

BACKGROUND ART DC stabilized power supply apparatus stabilizes outputs the input voltage V _in from the input terminal to a predetermined output voltage V _out. FIG. 6 is a block diagram of the stabilized DC power supply device.
Input voltage V _in from the input terminal is converted into the output voltage V _out by the output transistor 14. The output voltage detection circuit 13 detects the output voltage V _out . Error amplification circuit 18
Is a reference voltage V _ref from the reference voltage source 17, the partial pressure of the output voltage V _out to be output from the output detection circuit 13, respectively enter, the difference between the partial pressure of the reference voltage V _ref and the output voltage V _out Amplify and output. In the base drive circuit 12, the signal output from the error amplification circuit 18 is amplified and supplied to the base of the output transistor 14,
Controls the collector-emitter voltage of the.

FIG. 4 shows a typical circuit configuration of a conventional DC stabilized power supply device. The same parts as those in FIG. 6 are designated by the same reference numerals. The conventional DC stabilized power supply device 1 includes a reference voltage source / error amplification circuit 11, a base drive circuit 12, an output voltage detection circuit 13, an output transistor 14, and an output capacitor C0.

First, the output voltage detection circuit 13 will be described. The output voltage detection circuit 13 includes a resistor R7 and a resistor R8 connected in series, and is provided between the output terminal and the ground. The connection point c between the resistors R7 and R8 is connected to the base of the transistor Q4 provided in the reference voltage source / error amplification circuit 11.

[0005] Thus, the voltage at the node c is the partial pressure V _adj becomes the output voltage V _out, a current corresponding to the partial pressure V _adj flows to the base of the transistor Q4.

Next, the reference voltage source / error amplifier circuit 11 will be described. One end of the resistor R4 and one end of the resistor R5 are both connected to the input terminal. The other end of the resistor R4 is PNP
The resistor R5 is connected to the emitter of the transistor Q5, and the other end of the resistor R5 is connected to the emitter of the PNP transistor Q6. The base of the transistor Q5 is the transistor Q
6 and the collector of the transistor Q5.

As a result, the resistor R4, the resistor R5, the transistor Q5, and the transistor Q6 form a current mirror circuit. Since the characteristics of the transistor Q5 and the transistor Q6 are the same, the emitter current I ₅ of the transistor Q5 and the emitter current I _{6 of the} transistor Q6 are equal.

The collector of the transistor Q5 is connected to the collector of the NPN type transistor Q4. The base of the transistor Q4 is connected to the connection point c in the output voltage detection circuit 13 as described above, and
The emitter of No. 4 is connected to one end of the resistor R1 and one end of the resistor R2. The other end of the resistor R1 is connected to the collector of the NPN transistor Q1, and the other end of the resistor R2 is connected to the collector of the NPN transistor Q2. The base of the transistor Q1 is connected to the base of the transistor Q2 and also to the connection point between the collector of the transistor Q1 and the resistor R1. Transistor Q
The emitter of 1 is grounded, and the emitter of the transistor Q2 is grounded via the resistor R3.

As a result, the resistor R1, the resistor R2, the transistor Q1, the transistor Q2, and the resistor R3 form a bandgap circuit. The emitter area of the transistor Q2 is N times the emitter area of the transistor Q1.

The base of the NPN transistor Q3 is connected to the connection point between the transistor Q2 and the resistor R2. The collector of the transistor Q3 is connected to the collector of the transistor Q6 and the base of an NPN type transistor Q7 provided in the base drive circuit 12 described later, and the emitter of the transistor Q3 is grounded. A phase compensation capacitance Cp1 is connected as a delay compensation circuit between the base and collector of the transistor Q3. As a result, the gain can be reduced before the phase delay advances, so that the stability of the feedback control system is improved and the output oscillation is less likely to occur.

Next, the voltage output from the reference voltage source / error amplification circuit 11 to the base drive circuit 12 will be described. The voltage output by the reference voltage source / error amplification circuit 11 is
It is the voltage V _b at the connection point b between the transistor Q3 and the transistor Q6. V _adj = V _BE4 + V _a (1) V _a = V _BE3 + I ₂ × R ₂ = V _BE3 + (V _BE1 −V _BE2 ) × R ₂ / R ₃ (2) However, V _BE1 , V _BE2 , V _BE3 and V _BE4 are base-emitter voltages of the transistors Q1, Q2, Q3 and Q4, respectively, and R ₂ and R ₃ are resistance values of the resistors R2 and R3, respectively.

Base-emitter voltages V _BE1 and V _BE2 of the transistors Q1 and Q2 are expressed by equations (3) and (4), respectively. V _BE1 = k × T / q × ln (I ₁ / I _S1 ) ... (3) V _BE2 = k × T / q × ln (I ₂ / I _S2 ) ... (4) where k is Boltzmann's constant, T Is an absolute temperature, q is an electron charge amount, and I _S1 and I _S2 are collector saturation currents.

From the expressions (2) to (4), the voltage Va at the connection point _a is expressed by the expression (5). V _a = V _BE3 + k × T / q × R ₂ / R ₃ × ln (I ₁ × N / I ₂ ) ... (5) Therefore, from the equations (1) and (5), the voltage at the connection point c is obtained. V _adj is expressed by equation (6). V _adj = V _BE4 + V _a = V _BE4 + V _BE3 + k × T / q × R ₂ / R ₃ × ln (I ₁ × N / I ₂ ) ... (6) Base-emitter voltage V of the transistors Q3 and Q4
_BE3 and V _BE4 have a negative temperature coefficient, and the temperature coefficient is canceled by appropriately setting R ₂ , R ₃ , and N of the bandgap voltage terms having the positive temperature coefficient of the third term of the equation (6). Therefore, the voltage V _adj at the connection point c can be _kept constant even when the temperature changes.

Output from the output voltage detection circuit 13
Voltage V_outPartial pressure V_adjIs a constant voltage corresponding to the reference voltage
When it is smaller than the value of the transistor Q4 according to the equation (6).
Mitter potential, that is, voltage V at connection point a_aBecomes smaller,
The output signal to the base drive circuit 12 becomes large. one
On the other hand, the output voltage V output from the output voltage detection circuit 13
_outPartial pressure V_adjIs greater than a constant voltage corresponding to the reference voltage
Similarly, from the equation (6), the voltage V at the connection point a_a
Becomes larger and the output signal to the base drive circuit 12 becomes
Get smaller.

Next, the base drive circuit 12 will be described. The NPN type transistor Q7 and the NPN type transistor Q8 are Darlington connected. The collector of the transistor 8 is connected to the base of the PNP type output transistor 14. The emitter of the transistor 8 is grounded via the resistor R6.

As a result, the output voltage V_outIs greater than the specified value
If it is smaller, the base drive circuit 12 also serves as a reference voltage source.
The error amplification signal input from the error circuit 11 becomes large.
And the current supplied to the base of the output transistor 14 is
It becomes large, and the collector-emission of the output transistor 14
Voltage V_CE14Becomes smaller. Therefore, the output voltage V_{ou t}
Grows.

On the other hand, when the output voltage V _out is higher than the predetermined value, the error amplification signal input from the base drive circuit 12 from the reference voltage source / error circuit 11 becomes small, so that the current supplied to the base of the output transistor 14 is reduced. Becomes smaller and the collector-emitter voltage V _CE14 of the output transistor 14 becomes larger. Therefore, the output voltage V _out becomes small.

With the above configuration, the output voltage V _out
Is feedback-controlled so that is stabilized at a predetermined value.

Further, on the output terminal side of the output voltage detection circuit 13, an output capacitor C0 is provided between the output terminal and the ground. This can serve to smooth the AC component such as high frequency noise of the output voltage V _out , reduce the high frequency impedance, and stabilize the output voltage V _out . A load resistor R _L is connected to the output terminal.

[0020]

In recent years, the surface mounting and downsizing of devices, as represented by portable equipment, have been rapidly progressing. Also in the DC stabilized power supply device, the output capacitors of the chip products that are surface-mounted are being actively used for both surface mounting and downsizing of the device, and ceramic capacitors particularly useful for downsizing are being widely used.

Ceramic capacitors have a smaller equivalent series resistance (ESR) than aluminum electrolytic capacitors (<10
0 [mΩ]), when used for the output capacitor of the stabilized DC power supply, the phase margin of the feedback control system decreases,
Output oscillation is likely to occur.

The Bode diagram of FIG. 5 shows the relationship between the closed loop gain and the closed loop phase delay of the feedback control system in the DC stabilized power supply device 1 of FIG. Output capacitor C0
When an aluminum electrolytic capacitor is used for the gain curve, the gain curve is G1 and the phase curve is P1. In this case, there is no phase delay on the high frequency side and a large phase margin φa is secured,
Even if the gain (feedback gain) is increased, output oscillation does not occur.

However, when a ceramic capacitor is used as the output capacitor C0, the gain curve becomes G2 and the phase curve becomes P2, and the phase margin φb decreases due to the phase delay on the high frequency side, leading to output oscillation.

As a method of eliminating output oscillation, a method of securing a feedback phase margin by suppressing a feedback gain or suppressing a high frequency gain by adjusting a pole by phase compensation, or a phase advance means is provided in a part of the feedback system. A method of increasing the phase margin by providing it is conceivable.

The method of suppressing the feedback gain deteriorates the load fluctuation rate (output voltage-load current characteristic), which is an important characteristic of the stabilized DC power supply device. Further, in the method of suppressing the high frequency gain by the phase compensation, the transient response characteristic with respect to a steep load change is deteriorated, and it is possible to realize a highly accurate DC stabilized power supply device with a small error between the predetermined value and the output voltage V _out. Is disadvantageous with respect to.

As an example of a method for increasing the phase margin by providing a phase advance means in a part of the feedback system, the resistance R of the conventional DC stabilized power supply device 1 shown in FIG. 4 is used.
8, there is a method of providing a phase compensation capacitor Cp3 in parallel. The configuration in this case is shown in FIG. The same parts as those in FIG. 4 are designated by the same reference numerals and the description thereof is omitted. In this case,
As shown in (3), the gain curve is G3 and the phase curve is P3. By suppressing the phase delay at high frequency, the phase margin φc is increased and phase compensation can be performed. still,
The gain curves G1, G2, G3 are in agreement in the low frequency region (<f ₂ ) and the phase curves P1, P2, P3 are in agreement in the low frequency region (<f ₂ ).

This method uses a resistor R8 and a phase compensation capacitance Cp.
It is suitable for a fixed output type DC stabilized power supply device that can be configured as a monolithic IC having 3 built-in. However, to apply to the user resistors R7, arbitrary setting can be output variable DC stabilized power supply apparatus freely set the output voltage value R8 is corresponding to the resistance R ₈ of the phase compensation capacitance Cp3 the resistance R8 I had to change it. In particular, R ₈ <10
When it becomes kΩ, the Cp3 value becomes significantly large, which makes it difficult to form a monolithic IC.

In view of the above problems, it is an object of the present invention to provide a DC stabilized power supply device that does not cause output oscillation even if an output capacitor having a small equivalent series resistance is used. Another object of the present invention is to provide a stabilized DC power supply device that does not need to change the setting of the phase advance means even if the set value of the output voltage is changed.

[0029]

In order to achieve the above object, in a stabilized direct-current power supply device according to the present invention, an output transistor for outputting an input voltage as an output voltage according to a base current, and the output voltage Detecting means, a voltage signal output from the detecting means and a predetermined reference voltage are compared, a reference voltage source / error amplifying means for amplifying and outputting an error resulting from the comparison, and a reference voltage source / A base drive circuit is supplied with a current signal controlled by a first transistor provided in the error amplification means, and supplies the base current to the base of the output transistor according to the current signal to control the output transistor. An output capacitor provided on the output side of the detection means,
And a phase delay means provided between the collector and the base of the first transistor, and a voltage signal provided from the base of the first transistor and the reference voltage source and error amplifying means and output from the detecting means. The phase lead means is provided between the base of the second transistor and the base of the second transistor.

Further, the phase lead means may be a phase compensation capacitance, and the phase compensation capacitance may be a base-emitter capacitance of a third transistor whose collector and base are connected by a resistor or a conductor. Good. Also,
The phase compensation capacitance that is the phase delay means is a capacitance between the base and emitter of a fourth transistor whose collector and base are connected by a resistor or a conductor, and the third transistor and the fourth transistor are: The structure may be arranged in the same epitaxial island region.

Further, the detecting means may be a resistance voltage divider in which a plurality of resistors are connected in series, and at least one of the resistors may have a variable resistance value.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a stabilized DC power supply device according to an embodiment of the present invention. The same parts as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

The stabilized DC power supply device 2 includes a transistor Q
A phase compensation capacitance Cp2 is provided as a lead compensation circuit between the base of the transistor 3 and the base of the transistor Q4. As a result, the phase can be prevented from being delayed before the gain is reduced, so that the feedback stability is improved and the output oscillation is prevented.

In the DC stabilized power supply device shown in FIG.
A Bode diagram when a ceramic capacitor is used as the output capacitor C0 is shown in FIG. The gain curve is G4 and the phase curve is P4. In addition, the phase compensation capacitance Cp2 is set to 0 [p
F] (equivalent to the configuration of FIG. 4), the gain curve is G5 and the phase curve is P5. The gain curve G4,
G5 matches in the low frequency region (<f ₂ ), and the phase curves P4 and P5 also match in the low frequency region (<f ₂ ).

The transfer function of the feedback control system is the first
Has a pole, a second pole, and a zero. The first pole is formed by the output capacitor CO, and its cutoff frequency f ₁ is expressed by the equation (7). f ₁ ≈1 ÷ {2 × π × C _O × (R _L // Z _O )} (7) However, R _L // Z _O in the equation (7) is a load resistance R _L and DC stabilization. The parallel resistance value with the output impedance Z _O of the power supply device is shown. Further, C _O represents the capacitance of the output capacitor C0.

The second pole is formed by the phase compensation capacitance Cp1 and its cutoff frequency f ₂ is expressed by the equation (8). f ₂ ≈1 ÷ {2 × π × Cp1 × (1 + A _O ) × R ₂ } (8) However, A _O in the equation (2) indicates the gain of the transistor Q3.

The zero point is formed by the phase compensation capacitance Cp2, and its cutoff frequency f ₃ is expressed by the equation (9). _{f 3 ≒ 1 ÷ {2 ×} π × Cp2 × R 2} ... (9)

[0038] By making the zero point at the frequency f ₃ by a phase compensation capacitor Cp2 provided as a phase leading circuit to a reference voltage source and an error amplifier circuit 11, it is possible to increase the phase margin φ1 of the feedback control system, the output voltage V _OUT does not oscillate. Further, the cutoff frequency f ₃ is the resistance R7 or R8.
Since the resistance value of is constant even if it is varied, even if the resistors R7 and R8 are variable resistors in order to make the output of the DC stabilized power supply variable, the phase compensation capacitor Cp2 remains fixed and the phase remains unchanged. A large margin φ1 can be secured. As a result, the reference voltage source / error amplification circuit 11 can be easily integrated into an IC.

The stabilized direct current power supply device is usually integrated into an IC. A method of forming the phase compensation capacitance Cp2 when integrated into an IC will be described below. In most cases, the capacity of the IC is formed by using the depletion layer capacity when the pn junction is reverse biased. The pn junction is formed by an NPN type transistor.

Therefore, as shown in FIG. 3A, the collector and the base of the transistor Q10 are connected to form the capacitor Cp2 by the base-emitter capacitance of the transistor Q10. Therefore, it is equivalent to connecting a Zener diode between the base of the transistor Q4 and the base of the transistor Q3.

As a result, the voltage at the connection point c in the output voltage detection circuit 13, that is, the divided voltage V _out of the output voltage V _{out.
When adj} rises above “breakdown voltage V _{th of the} Zener diode + base-emitter forward voltage V _{BE3 of} the transistor Q3”, the base current is supplied to the transistor Q3, the transistor Q3 is turned on, and the transistors Q7 and Q8. Is cut off, and the reference voltage source / error amplification circuit 11 and the base drive circuit 12 are cut off. Therefore, the phase compensation capacitance Cp2 is output to the output voltage V _out.
Also has a protection function to prevent overvoltage.

Further, as shown in FIG. 3A, the collector and the base of the transistor Q9 are connected to each other to connect the phase compensation capacitance Cp.
Also, 1 may be formed by the base-emitter capacitance of the transistor Q9. With such a structure, the structure of the IC has a phase compensation capacitance Cp1 as shown in the sectional view of FIG.
And the phase compensation capacitance Cp2 can be arranged on the same n-type epitaxial island 5. As a result, the IC pattern can be arranged easily, and the cost can be reduced.
The sectional view of the IC structure shown in FIG. 3B shows only the parts of the phase compensation capacitors Cp1 and Cp2, and other circuit elements are omitted.

A procedure for manufacturing the IC structure shown in FIG. 3B will be described. An n-type epitaxial layer is grown on the p-type silicon substrate 3 by the CVD method or the like. Then CV
A silicon oxide film (not shown) is formed on the surface by the D method or the like. After that, the oxide film at the boundary of the partition to be insulated is removed by a photolithography process and an etching process, and p-type impurities are introduced by ion implantation until the p-type silicon substrate 3 is penetrated to form an insulating diffusion region 4.
As a result, the n-type epitaxial island 5 can be separated and independent.

By connecting the p-type silicon substrate 3 to the lowest potential, a reverse bias is applied to the pn junction between the p-layer (p-type silicon substrate 3 and the insulating diffusion region 4) and the n-layer (n-type epitaxial island 5). Therefore, the elements formed in each n-type epitaxial island 5 will be insulated.

Next, the transistors Q9 and Q10 are formed in the n-type epitaxial island 5. By performing the oxide film formation, the photolithography process, the etching process, and the ion implantation described above, the p layer 6 serving as the base of Q9 and Q10 is formed.
To form. After that, the oxide film formation, the photolithography process, the etching process, and the ion implantation described above are performed again, so that n having a low resistivity serving as a collector of Q9 and Q10 is obtained.
⁺ Layer 7 and n ⁺ layer 8 having a low resistivity to serve as the emitter of Q9
And an n ⁺ layer 9 having a low resistivity which serves as an emitter layer of Q10.
And are formed at the same time.

Further, the oxide film in the portions which become the electrodes of the emitter, the base and the collector is removed by a photolithography process and an etching process, and aluminum is vapor-deposited to form an aluminum electrode (not shown). The transistor Q
The terminal C connected to the base of No. 3 is connected to the collector common to the transistors Q9 and Q10 via an aluminum electrode. Similarly, the terminal B connected to the base of the transistor Q3 is connected to the transistor Q via the aluminum electrode.
9 and Q10 are connected to a common base. Also,
A terminal E ₁₀ connected to the connection point c of the output voltage detection circuit 13
Is a terminal E ₉ connected to the emitter of the transistor Q10 through the aluminum electrode and the collector of the transistor Q3.
Is connected to the emitter of the transistor Q9 via an aluminum electrode.

In this embodiment, the output capacitor C
However, the present invention is not limited to this, and can be applied to a stabilized DC power supply device using another type of capacitor as an output capacitor.

[0048]

According to the present invention, since the phase advance means is provided between the base of the first transistor and the base of the second transistor, the phase margin of the feedback control system is increased, and the feedback control system is increased. The stability of is improved. As a result, output oscillation does not occur even when a ceramic capacitor having a small equivalent series resistance is used as an output capacitor for surface mounting and downsizing of the stabilized DC power supply device. The same effect can be obtained when the phase advance means is a phase compensation capacitor.

Further, according to the present invention, the phase compensation capacitance which is the phase advance means is the capacitance between the emitter and the base of the third transistor in which the collector and the base are connected by the resistor or the conductor. It will be easier. This makes it possible to reduce the size and cost of the stabilized DC power supply device. Further, since the emitter-base capacitance of the third transistor is equivalent to a Zener diode, it is possible to prevent the output voltage V _{out from} becoming an overvoltage by providing a phase compensation capacitance which is a phase advance means.

Further, according to the present invention, since the third transistor and the fourth transistor forming the phase delay means are arranged in the same epitaxial island region, the IC pattern can be easily arranged. This makes it possible to further reduce the size and cost of the stabilized DC power supply device.

Further, according to the present invention, since at least one of the resistors forming the detecting means has a variable resistance value, it becomes a variable output type DC stabilized power supply device. Even if the resistance value is changed, the phase advance means is provided between the base of the first transistor and the base of the second transistor, so that the phase margin of the feedback control system does not change. This allows
It is possible to fix the phase compensation capacitance that is the phase advance means.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a stabilized DC power supply device according to an embodiment of the present invention.

FIG. 2 is a Bode diagram of the DC stabilized power supply device according to the embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a phase compensation capacitor.

FIG. 4 is a circuit diagram showing a configuration of a conventional DC stabilized power supply device.

FIG. 5 is a Bode diagram of a conventional DC stabilized power supply device.

FIG. 6 is a block diagram showing a configuration of a conventional DC stabilized power supply device.

FIG. 7 is a circuit diagram showing another configuration of a conventional DC stabilized power supply device.

[Explanation of symbols]

1 Conventional DC stabilized power supply 2 DC stabilized power supply 3 in one embodiment of the present invention 3 p-type silicon substrate 4 insulating diffusion region 5 n-type epitaxial layer 6 p-layer 7 to 9 n ⁺ layer 11 reference voltage source / error Amplifier circuit 12 Base drive circuit 13 Output voltage detection circuit 14 Output transistor 17 Reference voltage source 18 Error amplifier circuits Cp1 and Cp2 Phase compensation capacitors Q1 to Q10 Transistors R1 to R8 Resistance C0 Output capacitor _RL Load resistance

Claims (5)

(57) [Claims] 1. An output transistor for converting an input voltage into an output voltage corresponding to a base current and outputting the output voltage, a detecting means for detecting the output voltage, a voltage signal output from the detecting means, and a predetermined reference voltage. And a reference voltage source / error amplifying means for amplifying and outputting an error resulting from the comparison, and a current signal controlled by a first transistor provided in the reference voltage source / error amplifying means. A base drive circuit for controlling the output transistor by supplying the base current to the base of the output transistor in response to the current signal; and an output capacitor provided on the output side of the detection means. A stabilized direct-current power supply in which phase delay means is provided between the collector and the emitter of the first transistor, the base of the first transistor; Phase advance means is provided between the base of the second transistor, which is provided in the reference voltage source and error amplifying means and which is supplied to the base by the voltage signal output from the detecting means. DC stabilized power supply. 2. The stabilized DC power supply device according to claim 1, wherein the phase lead means is a phase compensation capacitor. 3. The DC stabilization according to claim 2, wherein the phase compensation capacitance is a capacitance between a base and an emitter of a third transistor whose collector and base are connected by a resistor or a conductor. Power supply. 4. A phase compensating capacitor as the phase delay means,
The third transistor and the fourth transistor are the base-emitter capacitance of the fourth transistor whose collector and base are connected by a resistor or conductor, and
The DC stabilized power supply device according to claim 3, wherein the DC stabilized power supply devices are arranged in the same epitaxial island region. 5. The detecting means is a resistance voltage divider in which a plurality of resistors are connected in series, and at least one of the resistors has a variable resistance value. DC stabilized power supply device.