JP3499861B2 - Manufacturing method of thin film transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter referred to as TFT) used as a switching element of an active matrix liquid crystal display or the like .
Ltd. Law on. More particularly, to a simple method for the structure of a TFT thereby reducing the off-state current.

[0002]

2. Description of the Related Art Conventionally, in order to reduce the off current of a TFT, an LDD (lightly doped drain) structure in which a source / drain region on the gate electrode side is a low concentration impurity region or an offset structure in which no impurity is introduced is used. .

24 to 25 show, for example, Japanese Patent Publication No. 3-3.
FIG. 8 is a cross-sectional view of a TFT having a conventional LDD structure shown in Japanese Patent No. 8755. In FIG. 24, reference numeral 1 is an insulating substrate, 2 is a semiconductor thin film formed on the insulating substrate 1 and serving as an active layer, for example, a Si thin film, 3 is a gate insulating film formed on the semiconductor thin film 2, and 4 is a gate insulating film. A gate electrode 5 formed on 3 is an LDD region which is a low-concentration impurity region obtained by doping the semiconductor thin film 2 with a low concentration of impurities such as P and B, and 6 is a high concentration of impurities such as P and B. Source / drain regions, 7 is a metal thin film used as a source electrode, 8 is a metal thin film used as a drain electrode, and 9 is a source electrode 7 and a drain electrode 8.
This is a contact hole for connecting the source / drain region 6 to each other.

Next, a conventional method of manufacturing an LDD structure will be described. A semiconductor thin film 2 made of a Si thin film is formed on the insulating substrate 1 (FIG. 24A). Then, for example, Si
The gate insulating film 3 made of O ₂ is formed by, for example, the thermal oxidation method or the sputtering method (FIG. 24B). On the gate insulating film 3, a gate electrode thin film made of, for example, a P-doped Si thin film is formed and patterned to form the gate electrode 4 (FIG. 24C). Using this gate electrode 4 as a mask, for example, P is ion-implanted at a low concentration to form an LDD region 5 (FIG. 24).
(D)). Then, a pattern wider than the gate electrode portion is formed on the gate electrode using the photoresist film 11 (FIG. 25E). Using this photoresist film 11 as a mask, high concentration P, for example, is ion-implanted into the semiconductor thin film 2 (FIG. 25F). As a result, the LDD region 5 in which P is lightly doped and the source / drain region 6 in which the impurity of P is heavily doped are formed. Then, a contact hole 9 is opened on the gate insulating film (see FIG. 2).
5 (g)), and then the source electrode 7 and the drain electrode 8 are simultaneously formed (FIG. 25 (h)).

Next, the operation will be described. With a voltage applied between the source electrode 7 and the drain electrode 8,
By changing the voltage applied between the source electrode 7 and the gate electrode 4, the drain current flowing between the source electrode 7 and the drain electrode 8 can be changed.
The TFT of (h) can be used as a switching element.

For example, when used as a switching element of an active matrix liquid crystal display, the drain current when the TFT is off needs to be at least less than the leak current of the liquid crystal. In particular, when a polycrystalline Si film is used as the semiconductor thin film 2 for forming the channel region 2a in order to increase the drain current at the time of turning on, because of the grain boundaries existing in the polycrystalline Si film, Field Enhanced Emission (Fi
eld enhanced emission) current flows, and the drain current when off increases. It is generally said that the off-state drain current is proportional to the number of dangling bonds existing in the crystal grain boundaries and the electric field strength near the drain. Therefore, in FIGS. 24 to 25, the LD doped with a low concentration of impurities for the purpose of reducing the electric field strength in the vicinity of the drain.
The D region 5 is formed, the width of the depletion layer formed between the channel region 2a and the source / drain region 6 is expanded, and the electric field strength is reduced. As a result, an LDD structure capable of reducing the drain current at the time of off is formed. ing.

Another method of forming the LDD structure of the conventional FET will be described. FIG. 26 shows, for example, Japanese Patent Publication No. 4-3.
It is a figure which shows the manufacturing process of LDD structure FET shown by 4819 publication. First, as shown in FIG.
After forming the field oxide film 24 on the surface of the substrate 25, the gate insulating film 3 is formed by, for example, a thermal oxidation method, and then a thin film for a gate electrode, which is a Si film doped with P at a high concentration, is formed and then patterned. By the gate electrode 4
To form. Then, by ion implantation, for example, P
Ions are implanted at a low concentration to form the LDD region 5 in which impurities are doped at a low concentration. At this time, the gate electrode 4
A channel region 2a is formed in the lower semiconductor layer. Next, as shown in FIG. 26B, an oxide film 26 is formed on the entire surface by, eg, CVD method. This CVD oxide film 26
Is etched by anisotropic etching to form sidewalls 27 with the CVD oxide film left on both sides of the gate electrode 4. Then, for example, P is ion-implanted at a high concentration (FIG. 26C). At this time, the high-concentration P ions are not implanted under the gate electrode 4 and the sidewalls 27 because they serve as a mask. As a result, the source / drain regions 6 are formed as shown in FIG.
And, the LDD region 5 in which ions are implanted at a low concentration can be formed. Then, source / drain electrodes (not shown) are formed in a normal process to form a MOS type semiconductor device. The operating principle is the TF of the LDD structure described above.
Same as described in T.

Further, as another method of forming an LDD structure with a MOSFET, for example, Japanese Patent Laid-Open No. 61-2120.
As disclosed in Japanese Unexamined Patent Publication No. 67-67224 and Japanese Unexamined Patent Publication No. 61-224459, a method of forming an LDD structure by self-alignment by thermally oxidizing a gate electrode made of polycrystalline Si or the like is disclosed. That is, after forming the gate electrode, a low-concentration impurity region is formed using the gate electrode as a mask, and then the gate electrode made of polycrystalline Si is thermally oxidized to form a silicon oxide layer wider than the gate electrode on the sidewall portion of the gate electrode. To do. Then, using the silicon oxide layer as a mask, impurities such as P are ion-implanted at a high concentration to form source / drain regions, thereby forming an LDD structure.

As another method of forming an LDD structure by self-alignment by thermally oxidizing the gate electrode, for example, as disclosed in Japanese Patent Laid-Open No. 61-214472, the gate electrode is thermally oxidized and then increased. The LDD structure is formed by forming the source / drain regions of the concentration impurity, then removing the oxide film of the gate electrode by etching, and performing ion implantation of the low concentration impurity again using the gate electrode as a mask.

[0010]

The TFT having the LDD structure according to the first method is an LDD having a low impurity concentration.
Two photolithography processes are required to separately form the region 5 and the source / drain region 6 having a high impurity concentration. In addition, if the length of the LDD region 5 having low impurities becomes too long, the resistance component in that region increases, so that FIG.
Accuracy is required for the alignment of the gate electrode 4 and the resist film 11 in 5 (e). In particular, LDD lightly doped to reduce the drain current when off
When the impurity concentration of the region 5 is further reduced, or when a so-called offset structure in which impurities are not intentionally introduced is used, if the length of the low concentration region or the offset region is too long, the resistance increases and Causes a decrease in drain current. Therefore, it is required to improve the alignment accuracy of the gate electrode 4 and the resist film 11 in FIG.
To manufacture a large device such as a liquid crystal display in which the size of the display unit exceeds several inches diagonally, a large-area exposure and an aligner with high alignment accuracy is required. There is no exposure machine that satisfies the above requirements so far, and the above requirements cannot be satisfied.

Further, according to the second method, the LDD structure can be formed by self-alignment in one photolithography step, but it is difficult to control anisotropic etching when forming the sidewall of FIG. Has a problem that the end point of anisotropic etching is difficult to determine and there is not much margin.
Especially when applied to a TFT, if the semiconductor layer is too thinly etched, the active layer is greatly damaged. In the case of a TFT, anisotropic etching must be performed on a large area substrate such as a liquid crystal display panel. Therefore, there is a problem that it is more difficult.

Further, according to the third method, since the LDD structure can be formed by oxidizing the gate electrode, self-alignment can be performed and the LDD structure can be formed by one photolithography process. The thermal oxide film of the gate electrode made of silicon, etc. is about 0.1 to 0.3 μm at the most, and an oxide film sufficient to form an LDD structure requiring a length of about 0.8 to 1 μm is required. There is a problem that the thickness cannot be obtained.

In any of the above methods, LDD
If the length of the region is too short or the impurity concentration is too high, the off current increases. Conversely, if the LDD region is too long or the impurity concentration is too low, the off current is suppressed, but the series resistance of the TFT increases. Therefore, the on-current also decreases and LDD
Although it is necessary to strictly control the length of the region and the impurity concentration, there is a problem that the process is complicated and cannot be completely controlled.

The above problems are exactly the same when a so-called offset structure is adopted in which the impurity concentration in the LDD region is made extremely small.

The present invention has been made in order to solve such a problem, and provides a method of manufacturing a TFT in which an LDD structure or an offset structure can be formed by a simple process and the length and impurity concentration of which can be easily controlled. The purpose is to

Still another object of the present invention is to increase the length of the LDD region, reduce the doping concentration of impurities in the LDD region, and the like without causing a significant decrease in the on-current, which is caused by the treatment. L that can reduce off current
And to provide a manufacturing method of the TFT of DD or offset structure.

[0017]

[Means for Solving the Problems] T of the invention according to claim 1.
The manufacturing method of FT is such that a semiconductor thin film is provided on an insulating substrate, and a gate electrode is provided on the semiconductor thin film via an insulating film,
The said semiconductor thin film impurity is introduced source / drain regions on both sides of the gate electrode is formed, the offset region does not introduce low concentrations not pure object region or impurities Gate electrode side of the source / drain region a thin film transistor manufacturing method that have a, after forming the source / drain regions and the low concentration impurity region or the offset region,
At least low-concentration impurity regions or ohmic regions of the semiconductor thin film
Impurity of low concentration by oxidizing the surface of the fusing area
Is to shall thinner than the thickness of the semiconductor thin film of the object area or thickness channelization <br/> channel region of the semiconductor thin film of the offset region.

[0018]

Further, the method for producing the TFT of the invention according to claim 2
Is a semiconductor thin film provided on an insulating substrate.
A gate electrode is provided on top of the insulating film, and the gate electrode is
Impurities are introduced into the semiconductor thin film on both sides of the pole to form the source.
/ Drain region is formed, and the source / drain region
Introduce a low concentration impurity region or impurities to the gate electrode side.
In the manufacturing method of thin film transistor having no offset area
The source / drain regions and low concentration impurities
After forming a region or an offset region, the semiconductor
At least low concentration impurity regions or offset regions of the thin film
And wherein the surface of the band to be thinner than the thickness of the semiconductor thin film of at least a low concentration impurity region or the thickness of the channel region of the semiconductor thin film of the offset region by etching
To do .

[0020]

According to the first and second aspects of the present invention, after forming the LDD region or the offset region, at least the LD
Since the semiconductor thin film in the D region or the offset region is thin, the junction area between the channel region and the LDD region or the offset region is small, and the off current can be reduced. Moreover, the on-current is 10 below the gate insulating film.
Since the current flows at about 0Å, the ON current is not reduced even if the thickness of the LDD region or the offset region is reduced. Further, since the thickness of the channel region is not thin, the crystal grain size can be increased, and from this aspect as well, it is possible to reduce only the off current without reducing the on current. As a result, the length of the LDD region or the offset region does not need much precision.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION A first method of forming an LDD structure or an offset structure of a TFT according to the present invention by a simple process is to change the thickness of an insulating film on the LDD structure part and the source / drain region part. The LDD region, which is a low-concentration region, and the source / drain region, which is a high-concentration region, are formed at once by one-time ion implantation. Since the thickness of the insulating film on the LDD region is different from that on the source / drain region,
Even if the ion implantation is performed with the same implantation energy and the same dose amount, the low concentration region and the high concentration region can be simultaneously formed.

As a method of changing the thickness of the insulating film, for example, a part of the gate insulating film is etched to form a step in the film thickness or to form the source / drain regions before forming the semiconductor film. A spacer made of, for example, silicon dioxide is provided at a position, a step is formed in the semiconductor layer to be formed after that, and a planarized silicon dioxide film or resist film is provided on the spacer to flatten the surface. A step can be formed in the distance from the surface of the resist film or the like to the surface of the semiconductor layer. As another method, by forming the gate electrode in a taper shape and oxidizing the surface thereof, the oxide film is also formed in a taper shape, and the distance from the surface of the semiconductor layer is the sum of the gate electrode film and the oxide film. Can be changed.

The second method of forming the LDD structure or offset structure of the TFT according to the present invention is to form the gate electrode in a self-aligned manner in a simple process. LD by changing the size of the gate electrode by selective etching, or by changing the size of the gate electrode by oxidation or etching after oxidation
A D structure or an offset structure is formed. Since the gate electrode is formed in a tapered shape, an LDD structure or an offset structure having a sufficient length can be obtained by etching or oxidation. As another method of self-aligning the gate electrode, the gate electrode is oxidized by an anodic oxidation method capable of forming a thick oxide film on the gate electrode,
In the case of the self-alignment method or the inverted stagger structure in which the gate electrode is formed on the transparent substrate side, by changing the exposure intensity from the transparent substrate side, even if the same gate electrode is used as a mask, different widths are used. The LDD structure can be formed by a method such as exposure.

Further, by forming the source / drain regions and the LDD structure vertically as another structure, ion implantation is required twice, but the photolithography process may be performed only once by self-aligning the gate electrode. Moreover, the thickness of the LDD region (the length in the direction of current flow) can be controlled accurately.

Further, the TFT according to the present invention, which has a structure for suppressing the off current without reducing the on current, has a small junction area between the source / drain regions and the LDD or offset structure. Since a normal on-state current flows through about 100 to 200 Å near the insulating film near the gate electrode, there is no effect even if the junction area with the source / drain region is reduced. On the other hand, since the off current does not originally flow near the insulating film, the off current contributes to the entire junction area. By reducing the junction area, the off current is suppressed and the on current is not affected at all.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail with reference to specific embodiments with reference to the drawings.

[Embodiment 1] FIGS. 1A to 1D show the present invention.
FIG. 5 is a process cross-sectional explanatory view showing an example of the manufacturing method of the TFT of FIG.
It As shown in FIG. 1A, an active layer is formed on the insulating substrate 1.
As a semiconductor thin film 2 made of, for example, Si
For example, it is formed by the CVD method and then SiO ₂From etc.
The gate insulating film 3 is formed by, for example, a thermal oxidation method or a sputtering method.
Or by a CVD method or the like. Next, gate insulation
To form a gate electrode on the film 3, for example, P
A gate electrode film 4a made of a thin Si thin film is formed.

Next, as shown in FIG. 1B, the gate electrode film 4a is subjected to dry etching using the resist film 11 as a mask, for example, using SF ₆ gas.
Is isotropically etched to form the gate electrode 4. At this time, the width of the gate electrode 4 becomes narrower than the width of the resist mask 11 due to the side etching.

Then, as shown in FIG. 1C, the gate insulating film 3 is partially anisotropically etched by dry etching using, for example, CHF ₃ gas with the resist film 11 as a mask. The step portion is formed at a position wider than the gate electrode 4. Thus, gate insulating films having different thicknesses are formed. At this time, the thick portion of the gate insulating film 3 (below the gate electrode) is, for example, 1500 to 3
000Å, the thickness of the thin part is, for example, 1000-1
It is about 500Å.

Next, as shown in FIG. 1D, the resist film 11 is removed, and then impurities such as P are ion-implanted into the semiconductor thin film 2 to form the source / drain regions 6. Since the amount of impurity implantation depends on the film thickness of the gate insulating film, since the film thickness of the gate insulating film 3 is large in the portion close to the gate electrode 4, the impurity injection becomes low and the LDD region 5 having the LDD region 5 is formed. The structure is formed.

Since the semiconductor thin film 2 is protected by the gate insulating film 3, the semiconductor thin film in the source / drain region 6 is not damaged. Although the insulating film having different film thickness at the time of ion implantation is described as the gate insulating film, other insulating films may be used. The same applies to the following examples.

[Embodiment 2] FIGS. 2A to 2D are process cross-sectional explanatory views showing another embodiment of the manufacturing method of the TFT of the present invention. The present embodiment is characterized in that the gate insulating film of Embodiment 1 is not formed as a single layer but as two layers made of different materials.

First, as shown in FIG. 2A, a semiconductor thin film 2 made of, for example, Si is formed as an active layer on an insulating substrate 1, and then Al ₂ O ₃ and Ta ₂ O ₅ are formed. A first gate insulating film 31 made of SiO ₂ , Si ₃ N ₄
A second gate insulating film 32 made of, for example, is sequentially formed by, for example, a sputtering method, a CVD method, an anodic oxidation method, or the like.
Then, a gate electrode film 4a made of, for example, a P-doped Si thin film is formed on the second gate insulating film 32.

Next, as shown in FIG. 2B, the gate electrode film 4a is isotropically etched by using the resist film 11 as a mask, for example, by dry etching using SF ₆ gas to form the gate electrode 4 as a mask. Form. At this time, the width of the gate electrode 4 becomes narrower than the width of the resist mask due to the side etching.

Next, as shown in FIG. 2 (c), a second etching is performed by dry etching using, for example, CHF ₃ gas.
The gate insulating film 32 is selectively anisotropically etched with the first gate insulating film 31 to form a step portion at a position wider than the gate electrode. Since the first gate insulating film 31 is not etched, the step difference does not depend on the etching accuracy.
Of the gate insulating film 32. Thus, the gate insulating films have different film thicknesses.

Next, as shown in FIG. 2D, after removing the resist film 11, impurities such as P are ion-implanted into the semiconductor thin film 2 to form the source / drain regions 6. The amount of impurities implanted depends on the thickness of the gate insulating film, and the portion near the gate electrode 4 has a large thickness of the gate insulating film 3, so that ion implantation of impurities is weak.
LD having LDD region 5 in which impurities are implanted at a low concentration
A D structure is formed.

The step (b) of the above-mentioned Examples 1 and 2
After the anisotropic etching of the gate electrode film 4a and the gate insulating film 3 by exchanging the order of (c) and (c), the gate electrode film 4a
Isotropic etching of a can also be performed.

[Embodiment 3] FIGS. 3 to 4 are process cross-sectional explanatory views showing still another embodiment of the method of manufacturing a TFT for forming an LDD region and a source / drain region by one-time ion implantation according to the present invention. In this example, a step is provided on the surface of the semiconductor film by forming a semiconductor film with a spacer interposed at the source / drain region formation location.

First, as shown in FIG. 3A, a spacer 13 is formed by forming a thin film of, for example, SiO ₂ on the insulating substrate 1 and then etching and patterning using a photoresist film as a mask.

Then, as shown in FIG. 3 (b), the spacer 13 is on the drain region or the source region, and the insulating substrate 1 between them is the channel region.
For example, the semiconductor thin film 2 made of Si or the like is formed. Next, as shown in FIG. 3C, for example, SiO _{2 is formed} by a thermal oxidation method or a sputtering method, and then a thin film for a gate electrode made of, for example, P-doped Si is formed, and a photoresist or the like is formed. The gate electrode 4 is formed by etching and patterning with the mask as a mask.
And the gate insulating film 3 are formed.

Next, as shown in FIG. 3D, an insulating thin film 12 such as SiO ₂ or Si ₃ N ₄ or a resist is formed.
And the insulating thin film 1 is formed as shown in FIG.
The upper surface of 2 is flattened by, for example, a sputter etch or an etch back method using a mask material.

Then, as shown in FIG. 4 (f), from the surface of the flattened insulating thin film 12, for example, the gate electrode 4 is formed.
Is used as a mask and the insulating thin film 12 is used as a relatively weak mask to ion-implant the semiconductor thin film 2 with impurities such as P.

At this time, the acceleration voltage for ion implantation is set to a voltage at which P does not pass through the gate insulating film 3.

As a result, in the region of the semiconductor thin film, the source / drain region 6 is formed in the upper region of the spacer 13 where the gate insulating film 3 is not present on the surface and is heavily doped with impurities such as P, and the vicinity of the gate electrode 4 is formed. However, since the thickness of the insulating thin film 12 becomes thicker as it approaches the gate electrode 4, the impurity concentration of P gradually decreases.

Then, as shown in FIG. 4 (g), a contact hole 9 is formed in the insulating thin film 12, and then, as shown in FIG.
As shown in (h), the drain electrode 7 and the source electrode 8 are formed.

Next, the operation of the TFT manufactured by the manufacturing method according to this embodiment will be described.

By changing the voltage applied to the source electrode 8 and the gate electrode 4 while the voltage is applied between the source electrode 8 and the drain electrode 7, the source electrode 8
The drain current flowing between the drain electrode 7 and the drain electrode 7 can be changed, and the TFT functions as a switching element.

When used as a switching element of an active matrix liquid crystal display, a TFT is used.
It is necessary to reduce the drain current when the TFT is turned off. Therefore, the resistance when the TFT is turned off needs to be at least higher than the specific resistance of the liquid crystal. In particular, when a polycrystalline Si film is used as the Si thin film for forming the semiconductor thin film of the active layer in order to increase the drain current at the time of ON, the crystal grain boundaries existing in the polycrystalline Si film are used. Therefore, field-enhanced emission current flows, and drain current at off increases. It is generally said that the off-state drain current is proportional to the number of dangling bonds existing in the crystal grain boundaries and the electric field strength near the drain region 6. The TFT according to the present embodiment has an LDD structure in which the impurity concentration of P gradually changes from the source / drain region 6 to the channel end portion, and the electric field strength near the drain region 6 can be weakened. It is possible to reduce the drain current when the transistor is off. Further, the LDD structure in which the electric field strength is gradually weakened can be achieved by one-time ion implantation.

Although the spacer 13 is formed in the tapered shape in the above-mentioned embodiment, it is not always necessary to form the tapered shape.
It may be formed in a rectangular shape. In this case, the semiconductor thin film 2 is formed in steps, but the flattened insulating thin film 12 thereon also has steps, and the insulating thin films 12 are formed on both sides of the gate electrode by one ion implantation. Thick and constant low concentration L
A DD area is formed.

Further, by using the LDD structure, the off current can be reduced and the on / off ratio can be increased.

[Embodiment 4] Another embodiment in which the LDD structure is formed by one-time ion implantation by changing the thickness of the insulating film will be described. This embodiment is an example in which a gate electrode is formed on the substrate side, and a LDD structure is formed by ion implantation once for a TFT having a so-called inverted stagger structure in which a semiconductor thin film is formed thereon.

FIGS. 5A to 5D are process cross-sectional explanatory views showing Embodiment 4 of the method for manufacturing a TFT of the present invention.

As shown in FIG. 5A, the gate electrode 4 is formed on the insulating transparent substrate 1. Next, the gate insulating film 3 made of SiO ₂ or the like is formed by, for example, the sputtering method or the CVD method. Next, the semiconductor thin film 2 made of a Si thin film or the like is formed by, for example, the sputtering method or the CVD method. Next, the protective layer 19 made of Ta ₂ O ₅ , SiO ₂ , Si ₃ N ₄ or the like is formed by, for example, sputtering or a CVD method. Next, a resist layer 11a is formed by coating,
The resist mask 11 is formed by self-alignment with the gate electrode 4 by backside exposure of the insulating transparent substrate 1. At this time, the exposure amount is adjusted so that the width of the resist mask 11 substantially matches the width of the gate electrode 4.

Next, as shown in FIG. 5B, the protective film 19 is partially etched using the resist mask 11 by anisotropic dry etching using, for example, SF ₆ gas to obtain a step portion. To form. At this time, the protective film 1
It is desirable to leave 9 in order to protect the semiconductor thin film 2.

Next, as shown in FIG. 5C, after removing the resist mask 11, a resist layer 11a is formed again by coating. After that, by exposing the back surface of the insulating transparent substrate 1 again, the resist mask 1 is self-aligned with the gate electrode 4.
1b is formed. At this time, the exposure amount is adjusted so that the width of the resist mask 11b is narrower than the width of the gate electrode 4.

Next, as shown in FIG. 5D, an impurity such as P is ion-implanted into the semiconductor thin film 2 using the resist mask 11b. The impurity implantation amount depends on the film thickness of the protective film 19, and since the film thickness of the protective film 19 is large in the portion close to the gate electrode 4, the TFT having the LDD structure having the LDD region 5 in which the impurity is injected at a low concentration is used. Is formed.

In the patterning of the resist layer 11a by the exposure, the width of the mask can be controlled accurately by adjusting the exposure amount.

[Embodiment 5] FIGS. 6A to 6D are process cross-sectional explanatory views showing still another embodiment in which an LDD structure is formed by ion-implanting an inverted stagger structure TFT once.

As shown in FIG. 6A, the gate electrode 4 is formed on the insulating transparent substrate 1. Next, the gate insulating film 3 made of SiO ₂ or the like is formed by, for example, the sputtering method or the CVD method. Next, the semiconductor thin film 2 made of a Si thin film or the like is formed by, for example, the sputtering method or the CVD method. Next, the protective film 19 made of Ta ₂ O ₅ , SiO ₂ , Si ₃ N ₄ or the like is formed by, for example, a sputtering method or a CVD method. Next, a resist layer 11a is formed by coating, and the back surface of the insulating transparent substrate 1 is exposed to expose the gate electrode 4
To form a resist mask 11 by self-alignment. At this time, the exposure amount is adjusted so that the width of the resist mask 11 substantially matches the width of the gate electrode 4.

Next, as shown in FIG. 6B, the protective film 19 is partially etched using the resist mask 11 by anisotropic dry etching using SF ₆ gas, for example, to obtain a step portion. To form. At this time, the protective film 1
It is desirable to leave 9 in order to protect the semiconductor thin film 2.

Next, as shown in FIG. 6C, the resist mask 11 is etched by isotropic dry etching in a gas atmosphere such as O ₂ . The width of the resist mask 11b formed at this time is narrower than the width of the gate electrode 4. The reduction amount of the mask size can be controlled accurately by the etching time.

Next, as shown in FIG. 6D, impurities such as P are ion-implanted into the semiconductor thin film 2 using the resist mask 11b. Since the implantation amount of impurities depends on the film thickness of the protective film 19, the LDD in which the film thickness of the protective film 19 is large and the impurity is injected at a low concentration in the portion close to the gate electrode 4.
An LDD structure TFT having a region 5 is obtained.

[Embodiment 6] FIG. 7 shows a TFT having an inverted stagger structure.
FIG. 9 is a cross-sectional explanatory view showing still another embodiment in which the LDD structure is formed by one-time ion implantation.

In this embodiment, the protective film 19 is composed of two layers, and the upper second protective film 19b is the lower first protective film 1.
9a and the material that can be selectively etched, the protective films 19a, 19a
The amount of ion implantation into the source / drain region 6 and the LDD region 5 can be controlled accurately by adjusting the film thickness of b. The first
Examples of the protective film 19a and the second protective film 19b include a group consisting of SiO ₂ , Si ₃ N _4, etc. and Al.
By selectively using a group consisting of ₂ O ₃ , Ta ₂ O _5, etc., it is possible to selectively etch with high selectivity.

[Embodiment 7] FIG. 8 is a cross sectional view showing each step of still another embodiment of the method of manufacturing a TFT for forming an LDD region and a source / drain region by one-time ion implantation according to the present invention. In this embodiment, by forming the gate electrode in a tapered shape, the range of the oxide film formed as the sidewall of the gate electrode is widened.

As shown in FIG. 8A, after forming a semiconductor thin film 2 made of Si or the like as an active layer on the insulating substrate 1, SiO ₂ is mainly formed by a thermal oxidation method, a sputtering method or a CVD method. The gate insulating film 3 as a component is, for example, 1
Form about 400Å. Next, as shown in FIG. 8B, S doped with P, for example, is formed on the gate insulating film 3.
A gate electrode thin film made of i or the like is formed and patterned by etching using a photoresist film as a mask to form the gate electrode 4. At this time, the gate electrode 4
The end face shape of is formed into a tapered shape.

As a method of forming the end surface of the gate electrode in a tapered shape, for example, after patterning a resist film on the gate electrode film, baking is performed at 120 to 250 ° C. for about 30 minutes to form an end portion of the resist film. However, it is possible to form a tapered shape by sagging. The taper angle θ (see FIG. 8B) is equal to the LDD region length of 0.
In order to form about 8 to 1 μm, it is preferable to form about 5 to 15 °. After that, as shown in FIG. 8C, the gate electrode 4 is thermally oxidized to form the thermal oxide film 14 on the upper surface and the side surface of the gate electrode. At this time, as described above, the thermal oxide film 1 is formed by reducing the taper angle θ.
Even if the film thickness d ₁ of 4 is thin, the width d _{2 in the} lateral direction can be increased. Next, as shown in FIG. 8D, P, for example, is ion-implanted at a high concentration into the semiconductor thin film 2 for a channel using the gate electrode 4 as a mask. As a result, a TFT having an LDD structure can be formed by the source / drain regions 6 in which the impurity P is highly doped and the LDD region 5 in which the impurity P is gradually decreased.

Also in this embodiment, since the mask made of the oxide film around the gate electrode at the time of ion implantation becomes thicker with the gate electrode toward the center of the gate electrode, the impurity concentration due to the ion implantation on the gate electrode side. It is possible to form an LDD region that is low and has a higher impurity concentration as the distance from the gate electrode increases, by performing ion implantation once.

[Embodiment 8] FIG. 9 is a cross-sectional view showing each step of still another embodiment of the method of manufacturing a TFT for forming an LDD region and a source / drain region by one-time ion implantation according to the present invention. The present embodiment is different in that a metal film such as aluminum or tantalum is used in place of the impurity-doped Si as the gate electrode thin film of the above-described seventh embodiment, and an oxide film is formed by anodic oxidation.

As shown in FIG. 9A, after a semiconductor thin film 2 made of Si or the like to be an active layer is formed on the insulating substrate 1, for example, SiO ₂ is formed by a thermal oxidation method, a sputtering method or a CVD method. The gate insulating film 3, which is the main component,
For example, about 1400Å is formed. Next, as shown in FIG. 9B, a thin film of, for example, aluminum is formed on the gate insulating film 3, and is patterned by etching using the photoresist film as a mask to form the gate electrode 41. At this time, the end surface of the gate electrode 41 is formed in a tapered shape. The tapered shape can be formed in the same manner as in the seventh embodiment. After that, Figure 9
As shown in (c), the gate electrode 41 is anodized to form an anodic oxide film 15 on the upper surface and side surfaces of the gate electrode. Anodization is performed, for example, at a current of 1 to 100 mA / cm ² per unit area of the gate electrode surface area at 300 to 400 mA.
By applying a voltage of V, an oxide film of about 5200Å can be obtained. It should be noted that when the gate electrode is tapered as described above, it is possible to increase the width d _{2 in the} lateral direction by reducing the taper angle, even if the thickness d ₁ of the anodic oxide film 15 is small. Is the same as. Next, as shown in FIG. 9D, P, for example, is ion-implanted at a high concentration into the semiconductor thin film 2 made of Si or the like of the active layer using the gate electrode 41 as a mask. As a result, the source / drain regions 6 heavily doped with the impurity P are formed.
A TFT having an LDD structure can be formed by the LDD region 5 which is doped so that the impurity P is gradually reduced in concentration.

Even if the aluminum as the gate electrode 41 at this time is replaced with tantalum, the LDD structure can be realized by anodic oxidation in the same manner.

In this embodiment, since a metal film made of aluminum or tantalum is used as the gate electrode and the oxide film is formed by anodic oxidation, a thick oxide film can be easily formed unlike the thermal oxide film. . Further, since the thickness of the oxide film can be accurately controlled by the time and current for performing anodic oxidation, it can be formed to a predetermined thickness and the length of the offset structure can be accurately formed.

[Embodiment 9] FIG. 10 shows an embodiment of a method of manufacturing the TFT of the present invention in which an LDD structure (two ion implantations) having an accurate length or an offset structure is formed by self-alignment using a gate electrode. FIG.

As shown in FIG. 10A, after forming a semiconductor thin film 2 made of Si or the like as an active layer on an insulating substrate 1, SiO ₂ is mainly formed by a thermal oxidation method, a sputtering method or a CVD method. The gate insulating film 3 as a component is formed, for example, at about 1400Å. Next, as shown in FIG. 10B, a thin film of, for example, aluminum is formed on the gate insulating film 3 and is patterned by etching using the photoresist film as a mask to form the gate electrode 41. After that, as shown in FIG. 10C, the gate electrode 41 is anodized to form the anodic oxide film 15 on the upper surface and the side surface of the gate electrode 41. Next, as shown in FIG. 10D, the semiconductor thin film 2 is formed using the gate electrode 41 as a mask.
Then, ion implantation of P or the like is performed at a high concentration. As a result, the source /
An offset structure having a drain region 6 and an offset region 10 between the ends of the gate electrode can be formed. At this time, even if the gate electrode 41 is replaced with tantalum instead of aluminum, the offset structure can be similarly realized by anodic oxidation.

As in the eighth embodiment, a thick oxide film can be formed by anodic oxidation and the thickness can be easily controlled.

[Embodiment 10] FIG. 11 is a cross sectional view for explaining still another embodiment of the method for manufacturing a TFT of the present invention. In this embodiment, by performing the annealing after the ion implantation of the source / drain regions in an oxygen atmosphere,
The offset structure is formed by oxidizing a part of the gate electrode without increasing the number of steps.

First, in FIG. 11A, a semiconductor thin film 2 made of Si or the like to be an active layer is formed on an insulating substrate 1. Next, as shown in FIG. 11B, for example, Si
A gate insulating film 3 made of O ₂ or the like is formed. Further, on the gate insulating film 3, for example, P-doped doped Si
The gate electrode 4 is formed as shown in FIG. 11C by forming a thin film for a gate electrode made of, for example, and then patterning. Using this gate electrode 4 as a mask, for example, P is ion-implanted to form source / drain regions 6 in the semiconductor thin film 2 as shown in FIG. After the ion implantation, annealing is performed to recover the irradiation damage at the time of implantation. However, by performing this step in an oxygen atmosphere, the oxide film 14 isotropically formed on the surface of the gate electrode, and an insulating layer is provided. A TFT having an offset region 10 of ΔL in 11 (e) can be manufactured. After that, as shown in FIG. 11F, an interlayer insulating film 18 made of SiO ₂ or the like is formed, and then the source / drain electrodes 7 and 8 are formed.

Annealing is usually performed at about 850 to 900 ° C. for about 1 hour or more. In this embodiment, this annealing is performed in an oxygen atmosphere to oxidize the gate electrode without increasing the number of steps and to perform the offset structure. Is characterized by forming. An oxide film having a thickness of about 1000 to 2000Å can be formed by performing heat treatment under the above conditions in an oxygen atmosphere. For example, as shown in FIG. 11 (g), the gate electrode 4 should be patterned in a tapered shape. As a result, as shown in FIG.
In the step of ion implantation, the LDD region 5 whose impurity concentration is successively lowered can be formed at one time with the source / drain region 6, and the offset region 10 is formed by performing an annealing treatment in an oxygen atmosphere. You can Moreover, since the gate electrode 4 has a tapered shape,
The width ΔL of the offset region can be increased to 2-3 times the thickness of the oxide film.

[Embodiment 11] FIG. 12 shows still another embodiment of the manufacturing method of the TFT of the present invention. In this embodiment, the LDD structure is obtained by forming the offset structure in the tenth embodiment. That is, up to the annealing step after ion implantation for forming the source / drain regions of the TFT, the steps of the tenth embodiment (FIG. 11A to FIG.
(E)), and thereafter, the oxide film 14 on the surface of the gate electrode 4 is removed by etching, and then ion implantation is performed, so that the LDD region 5 is formed as shown in FIG. It is possible to easily obtain the TFT that has. After that, as shown in FIG. 12B, the interlayer insulating film 18 and the source / drain electrodes 7 and 8 are formed.

That is, also in this embodiment, since the oxide film is formed on the gate electrode by the annealing process after the ion implantation, an extra process is not required and an oxide film having an accurate thickness can be obtained. Two ion implantation steps are required to form the LDD region, but the gate electrode used as a mask can be formed by removing the oxide film after oxidizing, so that self-alignment is possible.

Also in this embodiment, by forming the gate electrode 4 into a tapered shape, as shown in FIG.
The LDD region 5 can be formed of the medium-concentration region 5a and the low-concentration region 5b having a concentration gradient, and the width thereof can be widened as described above.

[Embodiment 12] FIG. 13 shows still another embodiment of the manufacturing method of the TFT of the present invention. In the present embodiment, the annealing for forming the LDD structure in Embodiment 11 is performed in an oxygen atmosphere to further form an offset region next to the LDD region. That is, up to the step of ion implantation for forming the LDD regions in the source / drain regions of the TFT, the process of the eleventh embodiment (FIG. 11A).
(E) and FIG. 12 (a), the subsequent annealing is performed in an oxygen atmosphere to form the oxide film 16 isotropically again on the surface of the gate electrode.
As shown in (a), the LDD region 5 and the offset region 1
It is possible to easily manufacture a TFT having a double structure of 0.
After that, as shown in FIG. 13B, the interlayer insulating film 18,
The source / drain electrodes 7 and 8 are formed.

Also in this embodiment, by forming the gate electrode 4 into a tapered shape, as shown in FIG.
The LDD region 5 can be formed by the medium concentration region 5a and the low concentration region 5b having a concentration gradient, and the offset region 10 can be further provided. Further, the width of the LDD region and the offset region can be formed wider as described above.

[Embodiment 13] Still another embodiment of the manufacturing method of the TFT of the present invention is shown in FIGS. In this embodiment, the LDD region or the offset region is formed by self-alignment by directly etching the gate electrode by, for example, dry etching without oxidizing the gate electrode.

First, as shown in FIG. 14A, a semiconductor thin film 2 made of Si or the like serving as an active layer is formed on an insulating substrate 1.
To form. Next, as shown in FIG.
On the gate insulating film 3 made of O ₂ or the like, for example, a gate electrode thin film 4 made of doped Si doped with P or the like.
Form a. Next, as shown in FIG. 14C, photolithography for forming the gate electrode 4 is performed. At this time, the photoresist film 17 is post-baked at, for example, 120 ° C. (about 30 minutes after the photoresist pattern is formed. Heat treatment) to drip the end face. SF in this state
When the gate electrode thin film 4a is etched by plasma etching using a gas such as ₆ or CF ₄ or CHF ₃ (which may also be mixed with oxygen), the resist film 17 is also etched and the end portion of the resist film 17 is etched. Since it is formed thin, the end face of the resist film 17 recedes, and as shown in FIG. 14D, the tapered gate electrode 4 can be formed. By using the gate electrode 4 as a mask, for example, P is ion-implanted at a high concentration.
As shown in (e), the source / drain regions 6 are formed in the semiconductor thin film 2.

Next, the second part shown in FIGS.
Enters the stage of the process, as shown in FIG. 15 (f), SF ₆
And CF ₄ gas (sometimes further mixed oxygen) to reduce the gate electrode 4 by a predetermined distance by plasma etching using. Since the gate electrode is tapered, the end portion is thin, and the end surface recedes with etching. This receding area becomes an LDD area or an offset area as described later. Next, using this gate electrode 4 as a mask, for example, P is ion-implanted at a low concentration. As a result, the LDD region 5 in which the impurity P is doped in a low concentration, the source / drain region 6 in which the impurity P is implanted in a high concentration, and the channel region 2a below the gate electrode are formed in FIG.
It is formed as shown in FIG. The resist film formed in FIG. 14C may be left until the stage of FIG. 15G or may be removed after the process of FIG. 14D. When removing, the gate electrode 4 is made thicker in consideration of the etching amount.

After that, the LD is processed in the same manner as the other embodiments.
A D structure TFT is formed. If the low-concentration ion implantation shown in FIG. 15G is not performed, the LDD region 5 becomes an offset region in which impurity doping is not intentionally performed.
A TFT having an offset structure can be obtained.

In this embodiment, the end face of the gate electrode 4 is formed in a tapered shape, and the end face is receded by etching, and ion implantation is performed before and after this etching. Since the end face retreat amount corresponds to the LDD width or the offset width, it is important to control this.

The taper shape of the gate electrode according to the first step of this embodiment depends on the end surface shape of the photoresist film, which can be easily controlled by controlling the film thickness of the photoresist film and the post bake temperature. . In addition, the formation of the taper shape by plasma etching and the control of the amount of end face receding are
It is preferable to perform the etching under the condition that the under-etching is small and the anisotropy is relatively strong.

As another method for forming a tapered shape,
Etching while rotating the substrate by tilting the beam with an ion shower, or by using chromium as the gate electrode and forming it by wet etching by utilizing the poor adhesion to the resist film, and other known methods. It can be appropriately adopted.

[Embodiment 14] Next, another embodiment in which the LDD region is formed by self-alignment by etching the gate electrode with the above-described tapered gate electrode, the same as FIG. ~ (E) and FIG.
Description will be given with reference to process cross-sectional views of (f) to (i).
In this embodiment, an example using Al for the gate electrode is shown.

First, in FIG. 14C, a film of Al to be the gate electrode 4 is formed by sputtering or the like. Next, FIG.
Photolithography is performed to form the gate electrode 4 as shown in (c). At this time, a photoresist film is applied to, for example, 9
Post bake at about 0 ° C. In this state, the sagging of the resist end surface is small. Next, using this resist film as a mask, while the substrate is rotated, etching is performed obliquely with inert Ar ions. As a device in this case,
Instead of a normal parallel plate type reactive plasma etching apparatus, an ion shower etching apparatus in which the ionization chamber and the etching chamber are separated and the directionality of ions is enhanced is used. When ions are obliquely incident, the vicinity of the resist film becomes
Since the shadow of the resist film reduces the etching rate more than others, the pattern end surface becomes a tapered shape, and a tapered gate electrode 4 is formed as shown in FIG. Using this gate electrode 4 as a mask, for example, P is ion-implanted at a high concentration to form source / drain regions 6 in the semiconductor thin film 2 as shown in FIG. Here, inert Ar is used for taper etching of the gate electrode, but chlorine-based gas may be used to provide reactivity.

Next, the second one shown in FIGS.
As shown in FIG. 15F, the Al gate electrode 4 is reduced in size by a predetermined dimension by plasma etching using a chlorine-based gas, as shown in FIG. Since the gate electrode has a taper, the end portion is thin, and the end surface recedes with etching. Next, using this gate electrode 4 as a mask, for example, P is ion-implanted at a low concentration. As a result, the LDD region 5 in which the impurity P is lightly doped and the source / drain region 6 in which the impurity P is heavily doped are formed as shown in FIG.

Although the gate electrode is made of polysilicon or Al in the above embodiment, Cu, C may be used instead.
It may be a metal such as r, W or Mo. The method for forming the taper is not particularly limited as long as it has good controllability. For example, by taking advantage of the poor adhesion to Cr with respect to the resist film, it can be formed by side etching by wet etching, or any other known method can be appropriately adopted.

Although the TFT has been described in the above embodiment, it may be a bulk MOS transistor or a MOSIC in which it is integrated, and the same effect as that of the above embodiment can be obtained.

[Embodiment 15] Next, another embodiment will be described in which the gate electrode is self-aligned and the LDD structure is formed by performing ion implantation twice. This embodiment shows an example of a simple manufacturing method of an LDD structure by self-alignment for a TFT having an inverted stagger structure in which a gate electrode is first formed on a transparent substrate and a semiconductor thin film is formed thereon.

First, as shown in FIG. 16A, the gate electrode 4 is formed on the insulating transparent substrate 1. Next is SiO
_The gate insulating film 3 made of ₂ etc.
It is formed by the CVD method or the like. Next, the semiconductor thin film 2 made of a Si thin film or the like is formed by, for example, the sputtering method or the CVD method. Next, the resist layer 11a is applied and molded, and the back surface of the insulating transparent substrate 1 is exposed to self-align with the gate electrode 4 to form the resist mask 11. At this time, the exposure amount is adjusted so that the width of the resist mask 11 substantially matches the width of the gate electrode 4.

Next, as shown in FIG. 16B, using the resist mask 11, impurities such as P are ion-implanted into the semiconductor thin film 2 at a high concentration to form the source / drain regions 6.

Next, as shown in FIG. 16C, after removing the resist mask 11, a resist layer 11a is formed again by coating, and the back surface of the insulating transparent substrate 1 is exposed to self-align with the gate electrode 4. Forming a resist mask 11b. At this time, the exposure amount is adjusted so that the width of the resist mask 11b is narrower than the width of the gate electrode 4.

Next, as shown in FIG. 16D, an impurity such as P is again ion-implanted into the semiconductor thin film 2 at a low concentration using the resist mask 11b. As a result, a TFT having an LDD structure having the LDD region 5 in which impurities are injected at a low concentration is formed.

A similar LDD structure can be formed by performing the back surface exposure twice and the ion implantation amount in the opposite order.

[Embodiment 16] FIGS. 17 (a) to 17 (d) show steps of a further embodiment in which the gate electrode is self-aligned in the TFT having the inverted stagger structure and the LDD structure is formed by twice ion implantation. FIG.

First, as shown in FIG. 17A, the gate electrode 4 is formed on the insulating substrate 1. Next, the gate insulating film 3 made of SiO ₂ or the like is formed by, for example, sputtering or CVD.
It is formed by the method. Next, the semiconductor thin film 2 made of a Si thin film or the like is formed by, for example, the sputtering method or the CVD method. Next, a resist layer 11a is formed by coating, and the resist mask 11 is formed by self-alignment with the gate electrode 4 by exposing the back surface of the insulating transparent substrate 1. At this time, the exposure amount is adjusted so that the width of the resist mask 11 substantially matches the width of the gate electrode 4.

Next, as shown in FIG. 17B, using the resist mask 11, impurities such as P are ion-implanted into the semiconductor thin film 2 at a high concentration to form the source / drain regions 6.

Next, as shown in FIG. 17C, the resist mask 11 is etched by isotropic dry etching using O ₂ or the like. The width of the resist mask 11b formed by this etching becomes narrower than the width of the gate electrode 4. The reduction amount of the mask size can be controlled by the etching time.

Next, as shown in FIG. 17D, impurities such as P are again ion-implanted into the semiconductor thin film 2 at a low concentration using the resist mask 11b. As a result, a TFT having an LDD structure having an LDD region 5 in which impurities are injected at a low concentration can be obtained.

[Embodiment 17] FIG. 18 is a view showing an embodiment of the LDD structure of the TFT of the present invention. In this embodiment, the high concentration region and the low concentration region of the source / drain region are formed in the vertical direction, which is, so to speak, a vertical LDD structure TFT.

In FIG. 18, the source / drain electrodes 7 and 8 formed on the insulating substrate 1 and the semiconductor thin film are formed, and the gate insulating film 3 and the gate electrode 4 are formed thereon. Further, source / drain regions 5 and 6 in which impurities such as P and B are ion-implanted are formed in the semiconductor thin film. Here, the amount of impurities in the source / drain regions 5 near the gate electrode is smaller than the amount of impurities in the source / drain regions 6 connected to the source / drain electrodes 7 and 8. The current flow in the semiconductor layer at the time of off flows from the drain electrode 8 through the region 6 containing a large amount of impurities, the region 5 containing a small amount of impurities, and the vicinity of the interface of the gate insulating film 3 in the channel region 2a. Then, the source electrode 7 is passed through the region 5 containing a small amount of impurities and the region 6 containing a large amount of impurities.
Flows to. In this way, since the LDD structure of the source / drain regions of the semiconductor thin film 2 is formed in the film thickness direction, which is the direction of current flow, the off current can be reduced.

The thickness of the semiconductor thin film is, for example, 500.
The source / drain high-concentration region 6 can be formed to, for example, about 50 to 3000 Å, and the source / drain low-concentration region 5 can be formed to about 500 to 5000 Å.

According to the manufacturing method of the above-mentioned embodiment, in the ion implantation into the semiconductor thin film 2 using the gate electrode 4 as a mask, a high energy of, for example, about 100 keV is applied, and 1015 / c is applied.
A step of implanting impurities at a high concentration with a dose amount of about m ² and a step of implanting impurities at a low concentration with a dose amount of about 1013 / cm ² at a low energy of about 30 to 50 keV are performed. In this case, the thickness of the gate insulating film 3 was about 500Å. In this way, by controlling the energy of ion implantation, impurities can be implanted at an arbitrary depth of the film. Ion implantation of high-concentration impurities with high energy can form high-concentration source / drain regions 6 at deep positions. On the other hand, ion implantation of low-concentration impurities with low energy is performed by using low-concentration source /
The drain region, that is, the LDD region 5 can be formed. Either ion implantation may be performed first.

In the above-described embodiment, the resist mask is formed by one photolithography process, and the vertical LDD structure can be formed in the source / drain regions by ion implantation under different conditions. Therefore, the mask for forming the LDD structure is used. It is possible to increase the number and eliminate the need for highly accurate mask alignment.

[Embodiment 18] FIG. 19 is a sectional view showing another embodiment of the vertical LDD structure of the TFT of the present invention.

The gate insulating film 3 and the gate electrode 4 are formed on the semiconductor thin film formed on the insulating substrate 1.
The source / drain regions 5 and 6 of the semiconductor thin film are composed of a region 5 having a small amount of impurities on the surface side close to the gate electrode 4 and a region 6 having a large amount of impurities on the bottom surface side. Further, the gate insulating film 3 and a part of the region 5 having a small amount of impurities are removed, and the source / drain electrodes 7 and 8 are formed on the source / drain regions 6 having a high impurity concentration. The current flow in the semiconductor thin film at the time of off is such that it flows from the drain electrode 8 through the high impurity concentration region 6 and the low impurity concentration region 5 to the vicinity of the interface of the gate insulating film 3. Since the LDD structure is formed in the film thickness direction of the drain region, off current can be reduced.

In this embodiment, the source / drain electrodes 7 and 8 are provided on the exposed surface of the high concentration impurity region 6 by removing a part of the gate insulating film 3 and the low concentration impurity region 5. It differs from Example 17 in the point. According to this embodiment, since the gate electrode 4 and the source / drain electrodes 7 and 8 are both provided on the front surface side, the connection is convenient.

In the manufacturing method of this embodiment, first, as in the case of Embodiment 17, in the ion implantation into the semiconductor thin film 2 using the gate electrode 4 as a mask, a step of implanting an impurity with high energy and a high concentration, and a low energy. Then, the step of implanting impurities at a low concentration is performed. Either of the two ion implantations may be performed first. Ion implantation of high-concentration impurities with high energy is performed by the source / drain regions 6 of high-concentration impurities.
Can be formed. On the other hand, the low-energy low-concentration impurity ion implantation is performed with low-concentration impurity source / drain regions.
That is, the LDD region 5 can be formed. Next, the gate insulating film 3 and the low concentration impurity source / drain regions, that is, a part of the LDD region 5 are removed to expose the high concentration impurity source / drain regions 6, and the source / drain electrodes 7 and 8 are provided. Obtained by

[Embodiment 19] FIG. 20 is a sectional view showing still another embodiment of the vertical LDD structure of the TFT of the present invention. This embodiment is an example in which a vertical LDD structure is applied to an inverted stagger structure in which a gate electrode is provided on the substrate side.

As shown in FIG. 20, the transparent insulating substrate 1
The gate insulating film 3 and the semiconductor thin film are formed on the gate electrode 4 formed thereon. The source / drain regions 5 and 6 of the semiconductor thin film which are self-aligned with the gate electrode 4 by the back surface exposure are composed of a region 5 near the gate electrode 4 having a small amount of impurities and a region 6 having a large amount of impurities on the surface side.
Further, the region 6 having a large amount of impurities is the source / drain electrode 7,
8 is connected. The current flow in the semiconductor thin film at the time of off is from the drain electrode 8 to the high impurity concentration region 6 to the low concentration region 5 and then to the gate insulating film 3 in the channel region 2a.
Since the LDD structure is formed in the film thickness direction of the source / drain regions 5 and 6 of the semiconductor thin film, the off current can be reduced. Since the gate electrode is on the substrate side in the structure of this embodiment,
Unlike 7 and 18, a low concentration impurity region (LDD region) is formed on the deep side of the semiconductor thin film, and a high concentration region is formed on the surface side. Therefore, during ion implantation, high implantation energy is used with a small dose amount, and low implantation energy is used with a large dose amount.

In the manufacturing method of this embodiment, after the semiconductor thin film is formed,
Taking advantage of the characteristics of the transparent insulating substrate 1, a resist mask self-aligned with the gate electrode 4 is formed by backside exposure using the gate electrode 4 as a mask. In ion implantation into the semiconductor thin film using the resist mask, for example, 100
a step of implanting impurities at a low concentration with a high energy of about keV and a dose of about 1013 / cm ^2, and a low energy of about 30 to 50 keV, for example, 1
The step of implanting impurities at a high concentration of about 015 / cm ² is performed. Ion implantation of high-concentration low-concentration impurities can form source / drain regions of low-concentration impurities, that is, LDD regions 5. On the other hand, ion implantation of high-concentration impurities with low energy can form the source / drain regions 6 of high-concentration impurities. The region 6 having a high impurity concentration is connected to the source / drain electrodes 7 and 8 to obtain a TFT.

In this embodiment, since the resist mask self-aligned with the gate electrode 4 is formed by backside exposure, it is not necessary to perform highly accurate mask alignment.

[Embodiment 20] FIGS. 21 to 22 show the T of the present invention.
The cross section explanatory drawing of the manufacturing process of another example of FT is shown. In this embodiment, in addition to the LDD structure or the offset structure, another measure is added to further reduce the off current. In order to reduce the off current in the LDD structure or the offset structure, there is a method of increasing the LDD length or the offset length. However, if the LDD length or the offset length is made too long, the off current can be reduced, but the on current is also reduced, and the TFT characteristics are deteriorated. There is a problem. In this embodiment, the on-current flows only in the range of a thickness of about 100 Å at the interface between the gate insulating film and the semiconductor thin film, while the off-current flows over the entire junction area between the channel region and the source / drain region of the semiconductor thin film. The junction area between the channel region and the source / drain regions is reduced, paying attention to the fact that the junction region flows.
In this case, if the semiconductor thin film is thinned from the beginning,
If polysilicon is used for the channel region, its crystal grains also become small and the current characteristics are deteriorated, which is not preferable. Especially in order to obtain a lot of current as a semiconductor thin film,
Polysilicon is used instead of amorphous silicon, but in the case of polysilicon, it is necessary to increase the crystal grain size. Therefore, after forming a relatively thin semiconductor thin film, the junction area between the channel region and the source / drain region is reduced.

Next, one embodiment of a method of manufacturing a TFT in which the semiconductor thin film in the LDD structure or the offset structure is thinner than the semiconductor thin film in the channel region will be described with reference to FIGS. 21 to 22, 1 is an insulating substrate made of quartz or the like, 2 is a semiconductor thin film made of Si or the like used as an active layer, 3 is a gate insulating film formed on the semiconductor thin film 2, and 4 is a gate insulating film. The gate electrodes 5 formed on the LDD 5 are LDDs formed by lightly doping impurities such as P and B formed on the semiconductor thin films on both sides of the gate electrodes.
A region, 6 is a source / drain region doped with impurities at a high concentration, 7 is a source electrode, 8 is a drain electrode, 9 is a source / drain region 6 and a source electrode 7 or a drain electrode 8 doped with impurities at a high concentration. A contact hole for connection with the photoresist film, 11 is a photoresist film used for forming an LDD region during ion implantation, and 20 is at least a channel region 2a, a gate insulating film 3, a gate electrode 4,
It is an oxide film formed on the TFT surface by thermal oxidation after forming the LDD region 5 or the offset region and the source / drain regions 6.

A method of manufacturing the TFT will be described. First, FIG.
As shown in (a), a Si thin film is formed on the insulating substrate 1 by low pressure CVD and patterned to form an active body layer of the semiconductor thin film 2. Then, as shown in FIG. 21B, the surface of the semiconductor thin film 2 is thermally oxidized at, for example, 1000 ° C., thereby forming the gate insulating film 3 made of a silicon oxide film on the semiconductor thin film 2.

A thin film for gate electrode made of, for example, Si doped with P is formed on the gate insulating film 3, and a photoresist film 11 for forming a gate electrode pattern is formed on the Si thin film. Then, the Si thin film is dry-etched using SF ₆ gas using the photoresist film 11 as a mask to form the gate electrode 4. At this time, if dry etching is performed under the conditions of, for example, high frequency power of 0.25 W / cm ² and gas pressure of 40 mTorr, FIG.
As shown in FIG. 1 (c), the eaves structure is formed by side etching.

At the time of this etching, although it is originally isotropic etching, the etching in the vertical direction proceeds rapidly, and etching is performed using the resist film 11 as a mask in the depth direction of the P-doped Si thin film that is the gate electrode thin film. .
Since SF _{6 of the} etching gas is turned into plasma, S
i The thin film is etched to the bottom surface, and the gate insulating film 3
When exposed to, the plasma emission of fluorine radicals becomes stronger. Si under the photoresist film 11 that has been performed so far
Since the side etching of the thin film is performed only slightly, the side etching can be accurately performed by continuing the etching for a certain time from the time when the plasma emission is observed, and the eaves structure of an arbitrary length can be formed.

The etching for forming the gate electrode 4 can be carried out by dry etching using CF ₄ gas, SF ₆ or a mixed gas of CF ₄ and O _{2 in} addition to the SF ₆ gas described above. It can also be performed by wet etching using hydrofluoric acid or nitric acid.

Next, as shown in FIG. 21D, for example, P is ion-implanted at a high concentration to form the source / drain regions 6. At this time, as shown in FIG. 21D, ions are not implanted under the eaves formed of the resist film.

Next, after removing the photoresist film 11, as shown in FIG. 21 (e), by the second ion implantation, the regions not ion-implanted in FIG. 21 (d) at both ends of the gate electrode. Ions are implanted at a low concentration to form LDD regions 5.

Then, the entire substrate formed up to the step of FIG. 21E is thermally oxidized at, for example, 950 ° C. to form the thermal oxide film 20 on the entire film. When thermal oxidation is performed, for example, FIG.
At the interface between the LDD region 5 and the gate insulating film 3 shown in (e), this interface is eroded and reduced by thermal oxidation.
This reduced distance d ₃ is d ₃ = 0.44, where t is the thickness of the thermal oxide film formed by thermal oxidation in FIG.
It is known to be denoted by t. By this processing, L
At least the film thickness of the DD region can be reduced. At this time, in the channel region 2a below the gate electrode 4, since the gate electrode 4 serves as a mask for preventing oxygen from being supplied during the thermal oxidation, thermal oxidation is not performed, and as a result, the film thickness is not reduced. As a result, as shown in FIG. 22F, a TFT structure in which the LDD region 5 and the source / drain region 6 are thinner than the channel region 2a and the insulating film 20 which is thicker than the gate insulating film 3 is formed on the whole is obtained. . The increased thickness d ₃ of the oxide film, that is, the reduced thickness of the semiconductor thin film is 50 to 1 depending on the thickness of the semiconductor thin film 2.
It is sufficient if the thickness is about 00Å, and it is very effective if the thickness is about half the thickness of the semiconductor thin film. Further, there is impurity diffusion from the source / drain region 6 to the LDD region 5 during the heat treatment, but since it is about 1000 to 2000 Å at most, it does not affect the characteristics.

As shown in FIG. 22G, contact holes 9 are formed in the insulating film 20 on the source / drain regions 6.

As shown in FIG. 22H, the source electrode 7 and the drain electrode 8 connected to the source / drain region 6 through the contact hole 9 are formed.

The TFT of the present invention manufactured in this way
The operation of will be described. The drain current flowing between the source electrode 7 and the drain electrode 8 is changed by changing the voltage applied between the source electrode 7 and the gate electrode 4 while the voltage is applied between the source electrode 7 and the drain electrode 8. The TFT shown in FIG.
Can be used as a switching element.

When used as a switching element of an active matrix liquid crystal display, TF
The drain current when T is off must be at least equal to or less than the liquid crystal leakage current. Especially, semiconductor thin film 2
If a polycrystalline Si film is used as the material for the
Due to the crystal grain boundaries existing in the i film, the field enhanced emission current flows, and the drain current at the time of off increases.

It is generally said that the drain current at the off time is proportional to the dangling bond existing at the crystal grain boundary and the electric field strength near the drain. Therefore, in order to reduce the drain current at the time of off, it is necessary to reduce the electric field strength in the vicinity of the drain, and the TFT shown in FIG. 22H has an LDD structure in order to weaken the electric field strength. There is.

However, in the LDD structure, in order to further reduce the drain current at the time of off, it has been generally performed to lengthen the LDD length or reduce the doping concentration of impurities in the LDD region. As described above, the LDD region functions as a series resistance of the TFT when it is on, which causes a problem of reducing the on-current. Therefore, in this structure, the film thickness of the LDD portion is thinned by the thermal oxidation method to reduce the cross-sectional area of the junction portion, thereby further reducing the off current. Of course, in order to reduce the cross-sectional area of the joint portion, the film thickness of the semiconductor thin film 2 formed at the time of FIG. 1A can be made thin from the time of film formation. In this case, for example, Kobayashi et al. "Journal of Applied Physic"
s), Vol. 65, 1989, p. 2541, there is a problem that the crystal grain size to be formed becomes small. In general, when the crystal grain size becomes small, the number of crystal grain boundaries that act as a barrier to the movement of electrons increases, which causes a decrease in the drain current during ON.

In the method shown in FIGS. 21 to 22, since the film thickness of the LDD region 5 and the source / drain region 6 is thin because the thermal oxidation is performed after the formation of the TFT, the gate electrode 4 of As described above, the film thickness of the lower channel region 2a does not become thin because the gate electrode 4 acts as a mask during the thermal oxidation. Therefore, the film thickness of the channel region 2a can be made thicker as compared with the case where the film thickness of the channel region 2a is simply made, and as a result, the crystal grain size can be made larger, so that the drain current at the time of ON can be prevented from decreasing and the junction portion can be prevented. The cross-sectional area can be reduced and the drain current at the time of off can be reduced.

In this embodiment, LD is formed by thermal oxidation.
Although the D region 5 and the source / drain regions are thinned, the semiconductor thin film may be thinned by etching by wet etching or dry etching instead of the thermal oxidation method, and the insulating film may be provided again on the surface.

[Embodiment 21] In Embodiment 20, FIG.
As shown in (f), the TFT was directly thermally oxidized, but the gate electrodes 4 to P made of, for example, a P-doped Si film or the like used as a gate electrode at the time of thermal oxidation.
To prevent impurities such as that coming off, as shown in FIG. 23, TF with the protective film 21, for example made of SiO ₂
The T may be covered and then thermally oxidized. By doing so, the reduction in resistance of the gate wiring can be improved.

[Embodiment 22] In Embodiments 20 and 21, the LDD region 5 was doped with L at a low concentration.
Although the DD structure has been described, this portion may be an offset structure in which the LDD region 5 is not intentionally doped with impurities by skipping the step of FIG. In this case, the same effect as in Examples 20 and 21 can be obtained.

[0139]

According to the present invention, an LDD region or an offset region and a high concentration source / drain region can be formed by self-aligning a gate electrode without requiring a special photolithography process. A TFT having an LDD structure or an offset structure with high accuracy can be obtained by a simple process.

By forming the insulating film or the protective film thicker on the gate electrode side and thinner on the source / drain region side, the LDD region and the high-concentration source / drain region are simultaneously formed by one ion implantation. It is possible to form the TFT, and it is possible to obtain the TFT having the LDD structure with high accuracy in a smaller number of steps.

Further, by making the thickness of the semiconductor thin film in at least the LDD region or the offset region smaller than the thickness of the channel region, it is possible to reduce only the off current without reducing the on current, and further reduce the off current. The TFT can be obtained by a simple manufacturing method.

As a result, an inexpensive and high-performance TFT can be obtained, which greatly contributes to cost reduction and high performance of a flat panel display device such as an active matrix liquid crystal display.

[Brief description of drawings]

FIG. 1 is a cross-sectional explanatory diagram showing a manufacturing process of a TFT according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional explanatory diagram showing a manufacturing process of a TFT according to a second embodiment of the present invention.

FIG. 3 is an explanatory cross-sectional view showing the first half of the manufacturing process of the TFT according to the third embodiment of the present invention.

FIG. 4 is a cross-sectional explanatory view showing the latter half of the manufacturing process of the TFT according to the third embodiment of the present invention.

FIG. 5 is a cross-sectional explanatory diagram showing a manufacturing process of a TFT according to a fourth embodiment of the present invention.

FIG. 6 is a cross-sectional explanatory diagram showing a manufacturing process of a TFT according to a fifth embodiment of the present invention.

FIG. 7 is a sectional explanatory view showing a manufacturing process of the TFT according to the sixth embodiment of the present invention.

FIG. 8 is an explanatory cross-sectional view showing the manufacturing process of the TFT according to the seventh embodiment of the present invention.

FIG. 9 is a cross-sectional explanatory view showing the manufacturing process of the TFT of Example 8 of the invention.

FIG. 10 is a cross-sectional explanatory view showing the manufacturing process of the TFT of Example 9 of the invention.

FIG. 11 is a cross-sectional explanatory view showing the manufacturing process of the TFT of Example 10 of the invention.

FIG. 12 is a cross sectional explanatory view showing the manufacturing process of the TFT according to example 11 of the present invention.

FIG. 13 is a cross-sectional explanatory view showing the manufacturing process of the TFT of Example 12 of the invention.

FIG. 14 is a cross-sectional explanatory view showing the first half of the manufacturing process of the TFT of Example 13 of the invention.

FIG. 15 is a cross sectional explanatory view showing the latter half of the manufacturing process of the TFT of Example 13 of the invention.

FIG. 16 is a cross-sectional explanatory view showing the manufacturing process of the TFT of Example 15 of the invention.

FIG. 17 is a cross-sectional explanatory view showing the manufacturing process of a TFT of Example 16 of the present invention.

FIG. 18 is a cross-sectional explanatory diagram of a TFT according to example 17 of the present invention.

FIG. 19 is a cross-sectional explanatory diagram of a TFT of Example 18 of the present invention.

FIG. 20 is a cross-sectional explanatory diagram of a TFT according to example 19 of the present invention.

FIG. 21 is a cross sectional view showing the first half of the manufacturing process of the TFT according to Example 20 of the present invention.

22A and 22B are cross-sectional explanatory views showing the second half of the manufacturing process of the TFT of Example 20 of the present invention.

FIG. 23 is a cross-sectional explanatory diagram of a TFT of Example 21 of the present invention.

FIG. 24 is an explanatory cross-sectional view showing the first half of a conventional TFT manufacturing process.

FIG. 25 is a cross-sectional explanatory view showing the latter half of the conventional TFT manufacturing process.

FIG. 26 is a cross-sectional explanatory view showing a manufacturing process of a conventional LDD-structure MOSFET.

[Explanation of symbols]

1 insulating substrate, 2 semiconductor thin film, 2a channel region,
3 gate insulating film, 4 gate electrode, 5 LDD region (low concentration impurity region), 6 source / drain region, 1
0 offset region, 12 flattening insulating film, 13 spacer, 14 thermal oxide film, 19 protective film, 31 first gate insulating film, 32 second gate insulating film.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yu Nishimura 8-1-1 Tsukaguchi Honcho, Amagasaki City Mitsubishi Electric Corporation Material Devices Laboratory (72) Inventor Hisatoshi Kusumi 8-1-1 Tsukaguchi Honcho, Amagasaki City No. Mitsubishi Electric Corp. Material Devices Laboratory (72) Inventor Masami Hayashi 8-1-1 Tsukaguchi Honcho, Amagasaki City Mitsubishi Electric Corp. Material Devices Laboratory (56) Reference JP-A-3-165575 (JP, 165575) A) JP-A-4-62876 (JP, A) JP-A-4-196490 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (2)

(57) [Claims] 1. A semiconductor thin film is provided on insulation substrate, a gate electrode is provided via an insulating film on the semiconductor thin film,
Is the semiconductor thin film is introduced impurity source / drain regions on both sides are formed of the gate electrode, the offset region low concentration was not pure product area or do not introduce impurities into the gate electrode of the source / drain region A method of manufacturing a thin film transistor having, comprising forming the source / drain regions and the low concentration impurity regions or offset regions, and then oxidizing at least the surface of the low concentration impurity regions or offset regions of the semiconductor thin film to form the low concentration impurity regions or A method of manufacturing a thin film transistor, characterized in that the thickness of the semiconductor thin film in the offset region is smaller than that of the semiconductor thin film in the channel region. 2. A semiconductor thin film is provided on an insulating substrate,
A gate electrode is provided on the semiconductor thin film via an insulating film,
Impurities are introduced into the semiconductor thin film on both sides of the gate electrode.
To form a source / drain region, and the source / drain region is formed.
Low concentration impurity region or impurity on the gate electrode side of the in region
Thin-film transistors with offset regions that do not introduce matter
A method of manufacturing a source / drain region and a low concentration impurity region
After forming the offset region, a small amount of the semiconductor thin film is formed.
Surface of low concentration impurity region or offset region at least
Preparation of thin film transistors and forming thinner than the thickness of the semiconductor thin film of at least a low concentration impurity region or the thickness of the channel region of the semiconductor thin film of the offset region by etching.