JP3500213B2 - Image processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that compensates for image quality deterioration that occurs during input / output coordinate conversion.

[0002]

2. Description of the Related Art In order to rotate an image based on an image signal obtained by an image pickup means such as a CCD, digital image data is stored in a memory, and necessary image data is read out at a read address determined according to the rotation mode. Read from the memory,
A coordinate conversion circuit that performs predetermined arithmetic processing is used.

For example, as shown in FIG. 11, an image pickup element (referred to as a line sensor) L such as a CCD arranged along a main scanning reference axis direction (y axis) is sub-scanned in a direction perpendicular to the y axis. Image reading devices that read the subject image G by moving in the (x-axis) direction are used in various fields. In such an image reading apparatus, electrical scanning is performed with the arrangement direction of the line sensor L as the main scanning direction, and mechanical scanning is performed by mechanically moving the line sensor L in the x-axis direction.
The 3D image is being read.

By the way, since the installation angle of the line sensor with respect to the sub-scanning axis usually causes a deviation angle θ, the read image is also distorted. In order to correct this distortion and obtain correct image data, the coordinate conversion circuit as described above is usually used.

In the case of FIG. 11, the obtained image is distorted in a parallelogram. In order to correct this distortion, the input image data is stored in the memory, and the read address at the time of reading is the actual address X, Y. On the other hand, X ′ = X + Y · tan θ (1) Y ′ = Y / cos θ (2)

By the way, a decimal value is often generated in the values obtained by the equations (1) and (2), but the image data stored in the memory is a discrete value and its address is an integer value. Therefore, when a fractional part occurs in the read address, linear interpolation calculation is performed using the data of the integer addresses of the surrounding four points surrounding the obtained address position to obtain the output image data.

Specifically, in the obtained output address (X ', Y'), the data D (X ', Y') to be obtained if the integer part Xa, Ya and the decimal part of each value are xa, ya. Is
Based on the relationship shown in FIG. 12, D (X ′, Y ′) = (1−xa) (1−ya) D (Xa, Ya) + xa (1−ya) D (Xa + 1, Ya) + (1 -Xa) yaD (Xa, Ya + 1) + xaya D (Xa + 1, Ya + 1) (3)

The above-described interpolation calculation is performed by, for example, FIG.
This can be realized by the coordinate conversion circuit shown in. In FIG. 13, the image data input from the input terminal In is sequentially written in the memories 42 to 45 via the selector 41 controlled by the memory controller 46. This writing is for storing the pixel data of four adjacent points, and the pixel data is alternately stored in the memories 42 and 43 in the main scanning direction by one pixel data and in the sub scanning direction by one pixel data in the memory 4 alternately.
It is distributed and stored in 4 and 45. In the address conversion unit 47, the integer part of the address obtained by the equations (1) and (2) is sent to the memory controller 46, and the memory 4
The 4-point pixel data stored in 2-45 are sequentially read out and sent to the 4-point interpolation calculation section to obtain the interpolation data based on the equation (3).

Multipliers 49 to 5 constituting a four-point interpolation calculation unit
The interpolation coefficients generated by the interpolation coefficient generator 48 based on the decimal part from the address converter 47 are supplied to 2, 55 and 56 as the multiplied coefficients. Memories 42-45
The pixel data of the four adjacent points read from is supplied to multipliers 49 to 52, respectively, and is multiplied by a predetermined interpolation coefficient. The outputs from the multipliers 49 and 50 are added by the adder 53 and then multiplied by a predetermined interpolation coefficient in the multiplier 55. Similarly, the outputs from the multipliers 51 and 52 are added by the adder 54 and then multiplied by a predetermined interpolation coefficient in the multiplier 56. Finally, the multipliers 55 and 56
The respective outputs of 1 are added by the adder 57 to obtain the image pixel data between the four points which are subjected to the desired interpolation calculation.

[0010]

By the way, the image data obtained by the above-mentioned interpolation calculation coordinate conversion is generally accompanied by the deterioration of the frequency characteristic. FIG. 14 shows, as an example, the frequency response characteristics (horizontal axis represents frequency, vertical axis represents attenuation amount, Fs is sampling frequency) of image data obtained by 4-point pixel interpolation when the interpolation coefficient is 0.5. It is shown. As is clear from FIG. 14, the higher the frequency, the greater the attenuation, and the image quality deteriorates.

Therefore, an object of the present invention is to provide an image processing apparatus capable of compensating for the deterioration of the frequency characteristic due to the interpolation operation and suppressing the deterioration of the image quality.

[0012]

In order to solve the above-mentioned problems, the image processing apparatus according to the present invention deals with input image data.
Based on the corresponding real pixel data representing multiple real pixels
Interpolation pixel data to represent each interpolation pixel
Do not include a calculation unit that is designed to generate
Coordinate conversion means and the output of the above-mentioned calculation section of this coordinate conversion means.
Fill that can exhibit high-frequency emphasis characteristics for force data
The output pixel data that has been subjected to
Image processing including filter means for obtaining data
The device is a device in which the coordinate conversion means converts the coordinate-converted image.
Image data and the form of the operation executed in the operation unit
Is configured to output the data defining the state, the
The filter means is for calculating the above-mentioned calculation from the coordinate conversion means.
Based on the data that defines the morphology, the above coordinate conversion was performed.
Adaptively variable control of high-frequency emphasis characteristics for image data
It is configured to perform such compensation.

Here, the coordinate conversion means is used for the interpolation operation.
Based on the decimal part of the interpolation coefficient applied to
It is adapted to generate data defining the morphology.

[0014]

[0015]

[0016]

[0017]

According to the present invention, interpolation pixel data is generated by interpolation calculation based on a plurality of actual pixel data, and the output data generated by this calculation is subjected to high-frequency emphasis filtering processing and output to perform interpolation. The deterioration of the frequency characteristic due to the calculation is compensated.

[0018]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block configuration diagram showing a configuration of an image processing apparatus on which the present invention is based .

The image data input from the input terminal In is subjected to coordinate conversion processing such as rotation by the coordinate conversion circuit 1 as shown in FIG. 13, and then the deteriorated high frequency component is emphasized by the high frequency emphasis filter 2. The high frequency component is compensated and output. As the high-frequency emphasis filter 2, a one-dimensional or two-dimensional filter, for example, a Laplacian filter or the like can be used.

[0020] One embodiment of the present invention is shown below, which adaptively compensate for changes in the damping characteristics due to the interpolation coefficient (fractional part of the conversion address) that changes due to the position of the pixel data to be compensation operation Is.

As shown in FIG. 14, the frequency characteristic is deteriorated by the interpolation calculation, but this deterioration changes depending on the value of the interpolation coefficient. FIG. 2 shows changes in the attenuation amount with respect to the interpolation coefficient when the input frequency is Fs / 4. As is clear from FIG. 2, when the interpolation coefficient is “0” and “1”, the conversion output is not interpolated as a result, so no deterioration occurs, but the deterioration occurs as the distance from “0” and “1” increases. When the interpolation coefficient is "0.5", the maximum deterioration occurs.

This embodiment adaptively compensates for the deterioration of the frequency characteristic which changes according to the value of the interpolation coefficient, and its block diagram is shown in FIG.

In this embodiment, a coordinate conversion circuit 1 and a high-frequency emphasis filter 3 similar to those in FIG. 1 are provided, and the high-frequency emphasis filter 3 corresponds to the decimal part of the interpolation coefficient output from the coordinate conversion circuit 1. A coefficient conversion circuit 4 for adaptively changing the filter coefficient of is provided.

FIG. 4 shows a configuration example of a 3 × 3 spatial filter for the high-frequency emphasis filter 3. The high-frequency emphasis filter 3 includes 1H delay elements 11 and 12 having a delay function for one line and delay elements 13 to 1 having a delay function for one pixel.
6, the multipliers 17 to 21, the coefficient conversion circuit 22, the addition / subtraction circuit 23, and the adder 24. The coefficient conversion circuit 22 (corresponding to the coefficient conversion circuit 4 in FIG. 3) generates predetermined interpolation coefficients A, B, and C to be described later based on the decimal part of the interpolation coefficient.

The input image data includes the delay element 13 and 1H.
The signals are input to the delay element 11, delayed by 1 pixel and 1H, and output. The output from the delay element 13 is multiplied by the coefficient B generated from the coefficient conversion circuit 22 in the multiplier 17, and the result is input to the-terminal of the addition / subtraction circuit 23. The output of the 1H delay element 11 is multiplied by the coefficient C from the coefficient conversion circuit 22 in the multiplier 20 and input to one terminal of the addition / subtraction circuit 23. The output of the 1H delay element 11 is delayed by a total of 2 pixels by the delay elements 14 and 16 and then output by the multiplier 1
9 is multiplied by the coefficient C from the coefficient conversion circuit 22,
It is input to the-terminal of the adder / subtractor circuit 23. The output from the delay element 14 is also multiplied by the coefficient A in the multiplier 18 and input to the + terminal of the addition / subtraction circuit 23. The output from the 1H delay element 11 is delayed by 1H by the 1H delay element 12, further delayed by one pixel by the delay element 15, and then multiplied by the coefficient B by the multiplier 21, and the negative terminal of the adder / subtractor circuit 23. Entered in. The interpolation coefficients A to C are determined in correspondence with the pixels as shown in FIG. 5, and the input to each multiplier in FIG. 4 is for each corresponding pixel.

The five pieces of data input to the adder / subtractor circuit 23 are added and subtracted to extract the contour portion of the input image. The operation output from the adder / subtractor circuit 23 is output by the adder 24.
The output from the delay element 14 is added and output. The addition in the adder 24 is a process of adding the pixel data of interest to be originally output to the contour data. The filter characteristics are adaptively changed by changing the coefficients A, B, and C supplied to the multipliers 17 to 21 of the filter.
The high-frequency emphasis filter 3 can obtain a desired filter characteristic by setting the interpolation coefficients A, B, and C.

Next, the coefficient conversion circuit 22 of the coordinate conversion circuit 1
The filter coefficients A, B, and C in will be described with reference to FIGS. 6 and 7. In the following description, it is assumed that the decimal part of the interpolation coefficient is 1 bit.

In FIG. 6, the actual pixel (memory 4 in FIG.
(Corresponding to the read data from 2 to 45) is a large black circle, the output interpolated by the coordinate conversion is as shown in the figure.
4 of (0,0), (0,1), (1,0), (1,1)
Two states occur with the same probability. The state of (0,0) is
Actually, the actual pixel data stored in the interpolation memory of the coordinate conversion circuit is output as it is. The other three states (3
As for (point), since it is not an actual pixel, it is an interpolation calculation output based on the data of four surrounding points. Therefore, the coefficients A, B and C as the filter coefficients are from (0, 0) to (1,
It changes for each state of 1).

In the case of the state (0,0), as shown in FIG. 7A, all the filter coefficients are "0" and the state (1,0).
In the case of, the pixel coefficients are interpolated in the X direction and not in the Y direction, and the filter coefficient is as shown in FIG.
As shown in (B), only the X direction is emphasized. Further, in the case of the state (0, 1), the interpolation is not performed in the X direction but only in the Y direction, so that the coefficient for high-frequency emphasis is set in the Y direction as shown in FIG. 7C. To be done. Furthermore, in the case of the state (1, 1), interpolation is performed in both the X direction and the Y direction, so that filter coefficients that are emphasized in both directions are set as shown in FIG. 7D.

FIG. 8 shows a concrete circuit example of the coefficient conversion circuit 22 when the interpolation coefficient bit is 1 bit.

When the fractional part xa, ya of the input interpolation coefficient is 0, 0, the filter coefficients A to C are all 0, and similarly 1, 0
In the case of, the logic circuit generates a combination of coefficients such that the coefficient A is 2, B is 0, and C is 1. This logic circuit has AND gates 31 to 3 as shown in FIG.
3 and an OR gate 34. In addition, this circuit further includes 1H delay elements 35 to 37 for further delaying by one line.
And delay elements 38 to 40 for delaying by one pixel.

The interpolation coefficient fractional parts xa and ya are delayed by 1H by the 1H delay elements 35 and 36, respectively, further delayed by one pixel by the delay elements 38 and 39, and output as coefficients C and B. The fractional parts xa and ya are input to the gate circuits 31 to 33, respectively, and the outputs of the gate circuits 32 and 33 are O.
It is input to the R gate 34. The outputs of the gate circuits 31 and 34 are output as A2 and A1, the ground output is output as A0, and are input to the 1H delay element 37 as 3-bit data. In the high-frequency emphasis filter, a delay time of 1H + 1 pixels occurs before the target pixel data is filtered. Therefore, the filter coefficients A to C also require delay times equal to this, and the 1H delay elements 35 to 37 and 1
The pixel delay elements 38 to 40 perform this delay.

The fractional part xa of the interpolation coefficient in FIG.
The relationship between ya and the outputs A2, A1, A0 and the coefficients A, B, C is shown in FIG. xa is the filter coefficient C, and ya
Corresponds to B, and the 3-bit data of A0 to A3 corresponds to the filter coefficient A.

As described above, in this embodiment, as shown in FIG.
As shown in, the pixel to be interpolated, that is, the deterioration of the high frequency characteristic due to the coordinate conversion using the interpolation coefficient, by changing the filter coefficient corresponding to the interpolation coefficient,
That is, high-frequency deterioration is appropriately compensated by generating interpolation state data, and optimal compensation is always possible without performing compensation for real pixels without deterioration.

Still another embodiment of the present invention is one in which the delay element groups 35 to 40 of the embodiment shown in FIG. 8 are omitted to reduce the hardware scale, and its configuration diagram is shown in FIG. There is.

The deviation angle when a linear sensor as shown in FIG. 11 is attached is usually small. For example, the amount of deviation of the mounting angle is usually about ± 1 degree, and the value obtained by using the coordinate conversion circuit shown in FIG. 8 is, for example, the coordinate (40, 30) before conversion is (40.52, 30.004
6).

On the other hand, when the interpolation coefficient for the coordinate that follows this pixel by one line and one pixel is obtained, that is, by substituting the X and Y coordinates (41, 31) for calculation, the converted coordinates are obtained. Is (41.5411, 31.004
7). As can be seen from the data of the fractional part, there is almost no difference in the correction coefficient obtained when the delay element for 1H and the delay element for one pixel are passed, and as shown in FIG. Even if there is no element group, the image finally output is an image that is not much different from that in FIG.

The effects of the gist of the above-described embodiment will be listed below in comparison with the conventional one.

(1) Computation means adapted to respectively generate interpolation pixel data for representing each interpolation pixel based on corresponding corresponding real pixel data representing a plurality of real pixels, and this calculation. An image processing apparatus including a coordinate conversion circuit including a filter unit for performing a filtering process for providing high-frequency emphasis characteristics to the output data of the unit to obtain output pixel data, The deteriorated pixel can be compensated.

(2) Computation means for producing interpolation pixel data for representing each interpolation pixel on the basis of each corresponding real pixel data representing a plurality of real pixels, and this computation An image processing apparatus comprising a coordinate conversion circuit including: a filter unit for obtaining output pixel data by subjecting output data of the unit to filtering processing capable of exhibiting a high-frequency emphasis characteristic, The filter means is constructed so that its high-frequency emphasis characteristic is adaptively variably controlled (including when high-frequency emphasis is not performed) depending on the interpolation calculation by the above-mentioned calculation means. It is possible to compensate only for the pixels that have deteriorated by the interpolation calculation, and further high image quality can be expected.

(3) The calculating means of (2) has an interpolation state data generating means for generating the interpolation state data representing the interpolation calculation at the time point of the same calculating means and supplying it to the filter means. According to such an image processing apparatus, high-frequency compensation can be performed with small-scale hardware.

(4) A delay time corresponding to the interpolation calculation and / or the filtering process is provided in the transmission line for supplying the interpolation state data generated by the interpolation state data generating unit of (3) to the filter unit. According to the image processing device in which the delay means is inserted, it is possible to perform the high-frequency deterioration compensation with high accuracy.

(5) The image processing, wherein the interpolation state data generating means of (3) or (4) is adapted to generate the interpolation state data based on the decimal part of the interpolation coefficient applied to the interpolation calculation. According to the device, it is possible to perform appropriate high frequency deterioration compensation with small-scale hardware without detecting deterioration.

[0044]

As described above, according to the image processing apparatus of the present invention, the deterioration of the image quality can be suppressed by compensating the deterioration of the frequency characteristic due to the interpolation calculation.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a configuration of an image processing apparatus on which the present invention is based .

FIG. 2 is a diagram showing how the frequency characteristics deteriorate with respect to the interpolation coefficient when the input frequency is Fs / 4.

3 is a block diagram showing an embodiment of an image processing apparatus of the present invention.

FIG. 4 is a diagram showing a configuration example of a high-frequency emphasis filter 3 of the embodiment shown in FIG.

FIG. 5 is a diagram for explaining an interpolation coefficient in the embodiment shown in FIG.

FIG. 6 is a diagram for explaining filter coefficients A, B, and C of the coefficient conversion circuit 22 of the coordinate conversion circuit 1 in the embodiment shown in FIG.

FIG. 7 is a diagram for explaining filter coefficients A, B, and C of the coefficient conversion circuit 22 of the coordinate conversion circuit 1 in the embodiment shown in FIG.

8 is an interpolation coefficient bit of 1 in the embodiment shown in FIG.
It is a concrete circuit diagram of the coefficient conversion circuit 22 in the case of bits.

9 is a diagram showing the relationship between the decimal parts xa and ya of the interpolation coefficient in FIG. 8, outputs A2, A1 and A0, and coefficients A, B and C.

FIG. 10 is a configuration block diagram showing still another embodiment of the present invention.

FIG. 11 is a diagram showing scanning by an image reading apparatus that reads an image by conventional main scanning and sub-scanning.

FIG. 12 is a diagram for explaining the principle of coordinate conversion in a conventional interpolation calculation.

FIG. 13 is a diagram showing an example of a coordinate conversion circuit for interpolation calculation.

FIG. 14 is a frequency response characteristic diagram showing deterioration of frequency characteristics of image data obtained by interpolation calculation coordinate conversion.

[Explanation of symbols]

1 Coordinate conversion circuit A few high-pass filters 11, 12, 35-371 1H delay element 13-16, 38-40 1 pixel delay element 17-21 Multiplier 22 Coefficient conversion circuit 23 Addition / subtraction circuit 24 adder

Claims (2)

(57) [Claims] 1.For input image dataRepresents multiple real pixels
Display one interpolation pixel based on each corresponding actual pixel data.
To generate interpolation pixel data by interpolation calculation
OperationCoordinate conversion means including partsAnd this
ofCoordinate conversion means aboveCalculationDepartmentHigh range for the output data of
Apply filtering processing that can exhibit emphasis characteristics
High frequency component was compensatedThe file to obtain the output pixel data
Luther meansEquipped withImage processing device,The coordinate conversion means is configured to convert the coordinate-converted image data and
The data that defines the form of the calculation executed in the calculation unit.
Configured to output The filter means isThe performance from the coordinate conversion means
Data that defines the form of arithmeticRelying onThe above coordinate conversion
Image dataThe high-frequency emphasis characteristic can be adaptively changed
ControlMake compensation likeIs configured as
An image processing device characterized by the above. 2. The coordinate conversion means determines the form of the calculation based on the decimal part of the interpolation coefficient applied to the interpolation calculation.
Claim that is designed to generate data to determine
Item 1. The image processing device according to item 1 .