JP3500985B2 - Clock system switching circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock system switching circuit, and more particularly to a clock system switching circuit which maintains clock continuity during system switching in a redundant configuration.

[0002]

2. Description of the Related Art A conventional clock system switching circuit of this type is
Regarding the clock signals supplied to the device adopting the redundant configuration, the phases of the clock signals of the active system and the standby system are matched in advance. Then, for example, when a failure occurs in the clock system of the active system, the clock signal supplied to the device is switched to the normal clock of the standby system by the switching signal generated based on the clock loss detection signal.

FIG. 8 shows an outline of the configuration of a conventionally proposed clock system switching circuit. This clock system switching circuit has a first system and a second system as redundant configurations, and both have the same configuration. The first system will be described below. The first system input clock 10 ₁ is PL
It is input to L (Phase Locked Loop) 11 ₁ . PLL1
1 _1, the voltage controlled oscillator (Voltage Controlled Oscillat
or: Hereinafter, abbreviated as VCO. ) 12 ₁ oscillation clock 13 ₁
And synchronous control of the first system input clock 10 ₁ . VC
O12 ₁ oscillation clock 13 ₁ output from the even 1 / n frequency dividing circuit 14 ₁ are inputted, generates the first system divided clock 15 ₁ oscillation clock 13 ₁ is divided. The first system divided clock 15 ₁ is input to the selection unit 16. Further, the oscillation clock 13 ₁ is the counter 17 ₁
Is input to and generates a pulse synchronized with this oscillation clock. The pulse output from the counter is input to the control unit of the other system. That is, the counter 17 ₁ of the first system
The pulse 18 ₁ output by the second system is input to the control unit 19 ₂ of the second system and the pulse 1 output by the counter 17 ₂ of the second system is output.
8 ₂ is input to the control unit 19 ₁ of the first system.

Control unit 19₁Is the current system or standby system
Can be identified, and it is identified as the active system.
Need to be synchronized with the standby system clock when
Pulse 18₂1 / n frequency divider 14₁And coun
17₁Supply to On the other hand, the own system is the standby system
If it is determined that there is a clock of the other system that is the active system.
Pulse 18 to synchronize₂1 / n frequency divider 1
Four₁And counter 17 ₁To supply to. In addition, control
Part 19₁Is generated by a clock loss detection signal, etc.
Implementation that indicates the system switching information and package implementation status
Based on information, etc., the local system is the active system or the standby system.
Determine if

The output clock 21 is selectively selected from the divided clocks thus generated in each system based on the switching signal 20 generated by the clock break detection signal or the like in the selector 16.

FIG. 9 shows the signal waveform of each part of the clock system switching circuit shown in FIG. Here, it is assumed that the active system is the second system and the first system is in phase with the clock signal of the second system. 9A is a timing chart of the first system input clock 10 ₁ , FIG. 9B is a timing chart of the second system input clock 10 ₂ , and FIG. 9C is a timing chart of the oscillation clock 13 ₁ . 6D is a timing chart of the oscillation clock 13 ₂ , FIG. 7E is a timing chart of the first system division clock 15 ₁ , FIG. 6F is a timing chart of the pulse 18 ₂ , and FIG. ) Is the second system divided clock 1
5 ₂ timing chart, switching signal 20 is shown in FIG.
Of the output clock 21.
The respective timing charts are shown. That is, the first and, as shown in the diagram (a) and (b)
When the second system input clocks 10 ₁ and 10 ₂ are not in phase with each other, they are independently VCOs 12 ₁ and 12 _2.
As a result, the oscillation clocks 13 ₁ and 13 ₂ are output ((c) and (d) in the figure).

[0007] Here, as _{the 2} second system of counter 17 is active system counts the input of the oscillation clock 13 ₂ generates a pulse 18 ₂ at a predetermined timing as shown in FIG. (F) To do. This pulse 18 ₂ is notified to the control unit 19 ₁ of the first system. Since the first system is a standby system, the pulse 18 ₂ is directly input to the 1 / n frequency dividing circuit 14 ₁ and the counter 17 ₁ as a reset pulse signal. As a result, the 1 / n frequency dividing circuit 14 ₂ generates the second system frequency dividing clock 15 ₂ which is frequency-divided by 1 / n in synchronization with the oscillation clock 13 ₂ ((g) in the figure). On the other hand, 1 / n
The frequency dividing circuit 14 ₁ generates a _first system frequency-divided clock 15 ₁ divided by 1 / n in synchronization with the reset pulse signal and the oscillation clock 13 ₁ ((e) in the figure).

Therefore, when the system selected by the switching signal 20 is switched from the second system to the first system as shown in FIG. 6 (h), as shown in FIG. g)
As shown in (1), the phases of the first system divided clock 15 ₁ and the second system divided clock 15 ₂ are already in phase. Therefore, even if these frequency-divided clocks are switched by the selector 16 by the switching signal 20, the output clock signal 21 is generated as shown in FIG. There is no loss of continuity during system switching.

A technique relating to such a clock system switching circuit is disclosed in, for example, Japanese Patent Laid-Open No. 4-267652, "Clock phase synchronization system".

Another technique relating to such a clock system switching circuit is, for example, Japanese Patent Laid-Open No. 23001 / 2-1003.
As disclosed in Japanese Unexamined Patent Publication No. 8 "Clock system switching circuit", the changing points of the clocks of the active system and the standby system are converted into pulses and delayed until a position where the clock level is in a steady state. Then, the change-point pulse signal is used to retime a switching signal for performing system switching of the clock signals of the active system and the standby system, and the switching timing of the active system and the standby system clock is controlled by this retiming signal. As a result, it is possible to prevent the occurrence of “clock crack” in the conventional switched output clock.

[0011]

[Patent Document 1] Japanese Unexamined Patent Application Publication No.
In the technique disclosed in Japanese Laid-Open Patent Publication No. 267652, a counter circuit is used to output a reset pulse so as to synchronize clock signals of other systems, which causes a problem that the circuit configuration becomes large. .
In addition, since system switching is performed with an asynchronous switching signal, as the frequency of the clock signal improves, differences such as gate delay and wiring delay between the two systems cannot be ignored. However, there is a problem in that it is impossible to maintain the continuity of the clock signal at the time of switching, because such a clock crack occurs.

Further, in the technique disclosed in Japanese Patent Laid-Open No. 2-130018, the switching signals are synchronized to maintain the continuity of the clock signal at the time of selection. Since the delay circuit is used to generate the pulse for the system, it is necessary to change the time to be delayed according to the amount of deviation of the clock signals of the active system and the standby system. This requires more complicated consideration when the manufacturing conditions are different. Further, this technique has a problem that the continuity of the clock signals at the time of switching cannot be maintained when the clock signals of the active system and the standby system are 180 degrees out of phase with each other.

Therefore, an object of the present invention is to provide a clock system switching circuit that maintains the continuity of clock signals during system switching, regardless of the amount of deviation between the clock signals of the active system and the standby system.

[0014]

According to a first aspect of the present invention, there are provided: (a) first frequency dividing means for dividing the input clock of the first system; and (b) the first frequency dividing means. First level change detecting means for detecting a change in logic level of the first divided clock generated by frequency division, and (c) second dividing means for dividing the input clock of the second system. (D) second level change detecting means for detecting a change in the logic level of the second frequency-divided clock generated by frequency division by the second frequency dividing means, and (e) this second level change detecting means. a first preset means for presetting the frequency division output of the first frequency dividing means with the detection result of level change detection means, (f) minute second frequency dividing means in the detection result of the first level change detecting means second preset means for pre <br/> set division output, based on (g) a predetermined switching signal Selecting means for selectively selecting one of the first and second frequency-divided clocks, and (h) one of the first and second frequency-divided clocks as one of the rising and falling edges. A multiplying means for synchronously multiplying, and (i) a switching signal when the selecting means is selected by retiming the switching signal at the other edge different from the edge of the multiplied clock generated by being multiplied by this multiplying means. And a retiming means for controlling the clock system switching circuit.

That is, according to the invention of claim 1,
And a clock system switching circuit having a second system, the clocks input to the respective systems are frequency-divided by the first and second frequency dividing means, respectively, to generate the first and second frequency-divided clocks. At that time, thereby detecting a change in the logic level of the first divided clock in the first level change detecting means, to preset the divided output of <br/> second frequency dividing means in the detection result. Further, the second level change detection means detects a change in the logic level of the second frequency-divided clock, and the frequency division output of the second frequency division means is preset according to the detection result. The first and second frequency-divided clocks thus generated have the same phase, and the output clock is generated by being selectively selected by the selection means by a predetermined switching signal.
Moreover, in the invention according to claim 1, the generation of the switching signal for performing the switching control by the selecting means is performed by synchronizing either one of the first and second divided clocks with one of the rising edge and the falling edge. Therefore, the switching signal is multiplied by the multiplying means, and the retiming means retiming the switching signal at the other edge different from the edge synchronized at the time of multiplication of this multiplied clock. It is possible to avoid the switching control performed in step 1 and maintain the continuity of the clock signal during system switching.

According to a second aspect of the invention, (a) first frequency dividing means for dividing the input clock of the first system which is self-propelled, and (b) frequency dividing by the first frequency dividing means. First level change detecting means for detecting a change in the logic level of the first divided clock generated by the above; and (c) second dividing means for dividing the input clock of the second system, D) This second
Second level change detecting means for detecting a change in the logic level of the second divided clock generated by dividing by the frequency dividing means, and (e) a disconnection state of the input clock of the first system. Disconnection state determining means, and (f) when the disconnection state determining means determines that the input clock of the first system is in the disconnection state, the detection result of the second level change detecting means is the first. a first preset means for presetting the frequency division outputs of the frequency dividing means, (g) a second preset the divided output of the second frequency dividing means in the detection result of the first level change detecting means
And (h) selecting means for selectively selecting one of the first and second frequency-divided clocks based on a predetermined switching signal, and (ii) the first and second frequency-divided clocks. Multiplication means for multiplying either one in synchronization with one of the rising and falling edges,
(E) Clock system switching between the retiming means for generating the switching signal at the time of selection by the selecting means by retiming the switching signal at the other edge different from the edge of the multiplied clock generated by multiplication by this multiplying means. Prepare for the circuit.

That is, in the invention according to claim 2, the first
And a clock system switching circuit having a second system, the clocks input to the respective systems are frequency-divided by the first and second frequency dividing means, respectively, to generate the first and second frequency-divided clocks. At that time, the first level change detection means detects the change in the logic level of the first divided clock, and the second level change detection means detects the change in the logic level of the second divided clock. . Furthermore, the disconnection state determination means determines the disconnection state of the input clock of the first system, and when the disconnection state is determined, the first level is detected by the detection result of the change in the logic level by the second level change detection means. The frequency division output of the frequency division means is reset. On the other hand, regardless of the determination result of the disconnection state,
The frequency division output of the second frequency dividing means is preset by the detection result of the change in the logic level of the frequency division clock. The first and second frequency-divided clocks thus generated have the same phase, and the output clock is generated by being selectively selected by the selection means by a predetermined switching signal. Moreover, in the invention according to the second aspect, the generation of the switching signal for performing the switching control by the selection means synchronizes one of the first and second divided clocks with one of the rising edge and the falling edge. Therefore, the switching signal is multiplied by the multiplying means, and the retiming means retiming the switching signal at the other edge different from the edge synchronized at the time of multiplication of this multiplied clock. It is possible to avoid the switching control performed in step 1 and maintain the continuity of the clock signal during system switching.

According to a third aspect of the invention, (a) first frequency dividing means for frequency-dividing the input clock of the self-propelled first system;
(B) First level change detecting means for detecting a change in the logic level of the first frequency-divided clock generated by frequency division by the first frequency dividing means, and (c) input of the second system. A second frequency dividing means for dividing the clock; and (d) a second level change for detecting a change in the logical level of the second divided clock generated by the second frequency dividing means. detection means, (e) and the cross-sectional state discriminating means for discriminating the disconnection state of the input clock of the first system, (f) the input clock of the first system I <br/> by this disengaged state discrimination means Determined as a state other than disconnection
Output of the first frequency dividing means is input to the first system
While it is self-propelled as it is by the clock,
Second when the input clock is determined to be disconnected state
Level change detection means of the second divided clock is
The first divided clock at the timing when a change in
A first preset means for presetting the second divided clock in phase, (g) a first level change detecting means first
Timing that detects a change in the logic level of the divided clock of 1
A second divided clock first frequency division clock and peers in ring
Second presetting means for presetting a phase, and (h) first and second divided clocks based on a predetermined switching signal.
The clock system switching circuit is provided with selection means for selectively selecting one of the two.

That is, according to the third aspect of the invention, in the clock system switching circuit having the first and second systems, the clock input to each system is divided by the first and second frequency dividing means, respectively. The first and second divided clocks are generated. At that time, the first level change detection means detects the change in the logic level of the first divided clock, and the second level change detection means detects the change in the logic level of the second divided clock. . Further, the disconnection state determination means determines the disconnection state of the input clock of the first system, and when the disconnection state is determined, the second level change detection means causes the second frequency division.
At the timing when a change in the clock logic level is detected,
The divided clock of 1 is pre-phased with the second divided clock.
I have it set . In addition, the disconnection state determination means makes the first
When it is determined that the input clock of the system is not in the disconnected state
The output of the first frequency dividing means is the input clock of the first system.
I am trying to make it self-propelled as it is. Further , regardless of the determination result of the disconnection state, the detection result of the change in the logic level of the first frequency-divided clock by the first level change detection means is preset in the frequency-divided output of the second frequency-division means. . The first and second frequency-divided clocks thus generated are determined to be in the disconnected state of the input clock of the first system.
At this time, they are in phase with each other, and an output clock is generated by selectively selecting them by a selecting means by a predetermined switching signal.

[0020] In the present invention of claim 4, wherein, in the clock system switching circuit of claim 3, wherein, in synchronization with one of the first and second divided clock to one edge of its rising and falling edges Multiplication means to multiply by
Re-timing means for generating the switching signal of the selecting means by retiming the switching signal at the other edge different from the edge of the multiplied clock generated by being multiplied by the multiplying means.

That is, in the invention according to claim 4, the generation of the switching signal for performing the switching control by the selecting means is performed by the first and second
One of the divided clocks is multiplied by the multiplying means in synchronization with one of the rising and falling edges, and the other edge different from the edge synchronized at the time of multiplying the multiplied clock by the retiming means. It is generated by retiming the switching signal with.

According to the invention of claim 5, claims 1 to 1
In the clock system switching circuit according to any one of the items 3 , the first and second level change detecting means are characterized by detecting rising or falling.

[0023] That is, in the invention of claim 5, wherein the first and second level change detecting means, since in detecting the rising or falling, it is possible to simplify the circuit configuration.

[0024]

DETAILED DESCRIPTION OF THE INVENTION

[0025]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows a principle configuration of a clock system switching circuit according to an embodiment of the present invention. This clock system switching circuit has a first system and a second system which are both redundant and have the same structure. The first system input clock 30 ₁ is frequency-divided by the frequency divider circuit 31 ₁ and output to the selector 33 as the first system frequency-divided clock 32 ₁ . In addition, the second system input clock 30 ₂ is applied to the frequency dividing circuit 3
The frequency is divided by 1 ₂ and output to the selector 33 as the second system divided clock 32 ₂ . Each of the frequency dividing circuits 31 ₁ and 31 ₂ divides its own input clock, and is preset by pulse signals 34 ₁ and 34 ₂ synchronized with the frequency dividing clocks of other systems. Further, these first and second system divided clocks 32 ₁ , 3
A switching signal 35 for selectively selecting from 2 ₂ is input asynchronously, and is generated as a retiming switching signal 37 by the retiming circuit 36. This retiming switching signal 37 is used for the first and second system divided clocks 3
Retiming is performed so that the system does not switch at the rising or falling of 2 ₁ and 32 ₂ . Then, in the selector 33, this retiming switching signal 37
Depending on the first or second system divided clock 32 ₁ , 32 ₂
Is selected and output as the output clock 38.

[0027] In the clock-based switching circuit having such a configuration, the input clock waveform 39 _1, 39 ₂ first and the second system input clock 30, as shown in _1, 30 ₂ are each divider 31 _1, 31 Divided by ₂ . Divider circuit 31 ₁ , 3
The first and second system divided clocks 32 ₁ and 32 ₂ generated by 1 ₂ are input to the selector 33. At this time, the pulse signal 34 ₁ generated in synchronization with the _first system division clock 32 ₁ is input to the _second system frequency dividing circuit 31 ₂ . Then, the frequency-divided signal is preset by the frequency-dividing circuit 31 ₂ which divides the frequency of the _second system input clock 30 ₂ . As a result, the second system divided clock 32 ₂ has the same phase as the _first system divided clock 32 ₁ as the divided clock waveforms 40 ₁ and 40 ₂ . Alternatively, the pulse signal 34 ₂ generated in synchronization with the _second system division clock 32 ₂ is input to the _first system frequency dividing circuit 31 ₁ . Then, the frequency dividing signal is preset by the frequency dividing circuit 31 ₁ which divides the frequency of the _first system input clock 30 ₁ . As a result, the first system divided clock 32 ₁ becomes like the divided clock waveforms 40 ₁ and 40 ₂ , and has the same phase as the _second system divided clock 32 ₂ .

The main part of the configuration of the clock system switching circuit in this embodiment will be described below.

FIG. 2 shows the essential parts of the clock system switching circuit of this embodiment shown in FIG. However, the same parts as those of the clock system switching circuit shown in FIG. The first system input clock 30 ₁ is input to the frequency dividing circuit 41 ₁ . The frequency dividing circuit 41 ₁ is composed of a binary counter capable of preset input, divides the first system input clock 30 ₁ to generate the first system divided clock 32 ₁ , and selects the selector 3
3 and the differential circuit 42 ₂ of the second system. The differentiating circuit 42 ₂ receives the first system division clock 3
The differential result of 2 ₁ can be output as a pulse, and the changing point of the divided clock is output as a pulse in the differentiating circuit in this embodiment. The differentiated output pulse from the differentiating circuit 42 ₂ is the frequency dividing circuit 41 ₂ of the second system.
Has been entered in.

The frequency dividing circuit 41 ₂ is composed of a binary counter capable of preset input. When the second system input clock 30 ₂ is input, the frequency dividing circuit 41 ₂ divides this frequency and the differential output pulse from the differentiating circuit 42 ₂ is inputted. The second that inputs the load value
The system divided clock 32 ₂ is generated. As a result, the frequency dividing circuit 41 ₂ divides the frequency of the _second system input clock 30 ₂ and outputs the _second system frequency dividing clock 32 ₂ synchronized with the change point of the _first system frequency dividing clock 32 _1. can do. The second system divided clock 32 ₂ is input to the first system differentiating circuit 42 ₁ and the selector 33. The differentiating circuit 42 ₁ can output the differentiated result of the input second system divided clock 32 ₂ as a pulse. In the differentiating circuit of the present embodiment, the changing point of the divided clock is pulsed. Output as. The differential output pulse from the differentiating circuit 42 ₁ is input to the frequency dividing circuit 41 ₁ of the first system.

In the frequency dividing circuit 41 ₁ , the second circuit is used as described above.
The system input clock 30 ₂ is input and frequency-divided. At this time, the first system frequency-divided clock 32 ₁ which receives the differential output pulse from the differentiator 42 ₂ as the load value is generated. As a result, the frequency dividing circuit 41 ₁ divides the frequency of the _first system input clock 30 ₁ and outputs the _first system frequency dividing clock 32 ₁ synchronized with the change point of the _second system frequency dividing clock 32 _2. can do.

The first and second generated in this way
The system divided clocks 32 ₁ and 32 ₂ are also input to the selector 43. The selector 43 uses the retiming switching signal 37 obtained by retiming the switching signal 35 by the retiming circuit 36 to generate the first and second system divided clocks 32.
Selectable from among ₁ and 32 ₂ and selected Divided clock 4
4 is output. The selected divided clock 44 is input to the retiming circuit 36. In the retiming circuit 36, the switching signal 35 is retimed based on the selected divided clock 44 to generate a retiming switching signal 37. At this time, the selected divided clock 44 is multiplied, and switching is performed at a position where the logical level of the divided clock is stable while avoiding rising and falling of the first and second system divided clocks 32 ₁ and 32 _2. Will be retimed.

The selector 33 uses the retiming switching signal 37 as described above to generate the first and second divided clocks 3.
Output clock 38 by selecting one from 2 ₁ and 32 ₂
Is output as a reference clock of an external device (not shown).

FIG. 3 specifically shows an example of the configuration of the differentiating circuit 42 ₁ shown in FIG. Differentiating circuit 42 ₁ ,
Both 42 ₂ have the same structure. The differentiating circuit 42 ₁ is a delay-type flip-flop (Delayed-Flip Flop: D-
Abbreviated as FF. ) 45 ₁ , a NOT circuit 46 _1, and a 2-input AND circuit 47 ₁ . The first system input clock 30 ₁ is input to the clock terminal (CK) of the D-FF 45 ₁ . The second system divided clock 32 ₂ is input to the data terminal (D). Then, the second system divided clock 32 _{2 that} is synchronized with the first system input clock 30 ₁ and is output from the output terminal (Q) is
After being logically inverted at 6 ₁ , it is input to one input terminal of the 2-input AND circuit 47 ₁ . This 2-input AND circuit 47 ₁
The second system divided clock 32 ₂ is input to the other input terminal of the. The 2-input AND circuit 47 ₁ is
The logical product of the signals input from the terminals is calculated by the differential output pulse 4
Output as 8 ₁ .

With such a configuration, the differential output pulse 48 which is the logical product of the signal obtained by delaying the second system divided clock 32 ₂ by one clock of the first system input clock 30 ₁ and the signal before the delay. ₁ is a rising edge detection pulse of the _second system divided clock 32 ₂ .

FIG. 4 specifically shows an example of the configuration of the retiming circuit 36 shown in FIG. The retiming circuit 36 includes a multiplication circuit 49 and a D-FF 50 that latches the signal at the D terminal at the falling edge of the signal input to the CK terminal. Selectable division clock 44
Is input to the multiplication circuit 49 and is multiplied by 2 in this embodiment in synchronization with the rising edge of the selective frequency-divided clock 44. The multiplied clock 51 that has been multiplied by 2 in the multiplication circuit 49 is DF
The switching signal 35 input to the CK terminal of the F50 and input to the D terminal is latched at its falling edge, and its output is output from the Q terminal as the retiming switching signal 37.

[0037] Thus the first or second system divided clock 32 _1, 32 ₂ with the selected divided clock 44 of the same phase 2
At the falling edge of the multiplied clock 51, the switching signal 35
Is re-timed so that switching is not performed near the rising and falling edges of the first and second divided clocks 32 ₁ and 32 ₂ .

FIG. 5 shows the retiming circuit 36 shown in FIG.
3 shows an outline of the signal waveform of each part. Figure 5
(A) is a timing chart of the selective division clock 44,
FIG. 7B is a timing chart of the multiplied clock 51,
FIG. 7C shows a timing chart of the switching signal 35, and FIG. 7D shows a timing chart of the retiming switching signal 37. That is, as described above, the selective division clocks of the same phase as the first and second system division clocks 32 ₁ and 32 ₂ which are divided by the division circuit of each system in synchronization with the division clocks of the other system. 44 ((a) in the figure) is multiplied by 2 in synchronization with the rising edge of the selected frequency-divided clock 44 by the multiplication circuit 49, and the multiplication clock 5 as shown in (b) of the figure is obtained.
1 is generated. Then, in the D-FF 50, the switching signal 35 asynchronously input is latched at the falling edge as shown in FIG.
The retiming switching signal 37 shown in FIG. 7D is output to the selectors 33 and 43.

In this way, the first and second system divided clocks 32 ₁ and 32 ₂ are multiplied in synchronization with the rising edge of the selective divided clock 44 having the same phase, and the asynchronous switching signal 35 is generated at the falling edge thereof. The retiming prevents the selectors 33 and 43 from switching the system near the rising or falling of the first and second system divided clocks 32 ₁ and 32 ₂ . As a result, it is possible to suppress the generation of abnormal pulses that occur during system switching and stabilize the operation of the system.

In the clock system switching circuit having such a configuration, as described above, the phases of the first and second system divided clocks 32 ₁ and 32 ₂ are respectively changed to the phase of the divided clock of the own system to the other system. By synchronizing with the frequency-divided clock, the continuity of the clock signal at the time of system switching is maintained. Therefore, the outline of the phase synchronization operation of the clock system switching circuit in this embodiment will be described with reference to FIG.

FIG. 6 shows the outline of the phase synchronization operation of the clock system switching circuit in this embodiment. 11A is a timing chart of the input clock 30 ₁ of the first system, FIG. 9B is a timing chart of the differential output pulse 48 ₁ generated by the differentiation circuit 42 ₁ of the first system, and FIG. ) Is a timing chart of the input clock 30 ₂ of the second system, and FIG. 7D is a differentiation circuit 42 ₂ of the second system.
Differential output pulse 48 _second timing chart produced by drawing (e) the first system divided clock 32 ₁ in the timing chart, FIG. (F) the second system divided clock 32 _second timing chart , Respectively. That is, in the frequency dividing circuit 41 ₁ , after being preset by the first system differential output pulse 48 ₁ (the same figure (b)), the first system input clock 30 ₁ (the same figure (a))
The first system divided clock 32 _{1 which} is divided in synchronism with is output ((e) in the same figure).

Then, the differential circuit 42 _{2 of} the second system generates the second system differential output pulse 48 ₂ in which the rising edge of the _first system divided clock 32 ₁ is detected (FIG. 7 (d)). ). In the frequency dividing circuit 41 ₂ , the frequency is preset by the second system differential output pulse 48 ₂ ((d) in the figure) and then divided in synchronization with the _second input clock 30 ₂ ((c) in the figure). The generated second system divided clock 32 ₂ is output ((f) in the same figure).

As described above, the clock system switching circuit according to the present embodiment divides the first and second system input clocks 30 ₁ and 30 ₂ having different phases from each other by the frequency dividing circuits 41 ₁ and 41 _{2 of the} respective systems. Divide by. At that time, each system has a differentiating circuit, and each frequency dividing circuit is capable of presetting a differential output pulse which detects a change point of the clock after frequency division of the other system as a load value input. The first frequency-divided clock 32 ₁ generated by the frequency-dividing circuits 41 ₁ and 41 ₂ of each system is generated as a frequency-divided clock that is synchronized with the change point of the _second frequency-divided clock 32 ₂ , and the second frequency-divided clock 32 ₁ is generated. Clock 32 ₂ is the first
It is generated as a divided clock synchronized with the changing point of the divided clock 32 ₁ . The switching control of the selector 33 that selectively selects one of these divided clocks is performed by multiplying _{one of the first} and _second divided clocks 32 ₁ and 32 ₂ in synchronization with the rising edge, and The retiming switching signal 37 is retiming the switching signal 35 that is asynchronously input at the falling edge. As a result, the switching control that is performed near the rising or falling of the divided clocks 32 ₁ and 32 ₂ can be avoided, and the continuity of the clock signal can be maintained during system switching. Further, even if either of the input clocks of the first or second system is brought into the clock interruption state due to a failure or the like, it is possible to synchronize both divided clocks at the time of the restoration thereof and maintain an appropriate redundant configuration. Further, since the phase adjustment is performed based on the divided clock having the low frequency, even if the clock frequency is improved, the synchronization can be easily achieved as compared with the phase adjustment based on the clock before the division. .

Modification

The clock system switching circuit in this embodiment is
As described above, even if the input clock of either the first system or the second system goes into a clock-disconnected state due to a failure or the like, in order to synchronize the phases at the time of recovery, the system of one system is separated. There was a "thinking" of returning the divided clock to the divided clock generation of the other system.
However, depending on mounting conditions, manufacturing conditions, and signal input conditions, there is a possibility that both divided clocks may be in an oscillating state in which unstable operation continues. Therefore, the clock system switching circuit in the present modification is characterized in that a kind of guard circuit is provided in either the first system or the second system.

FIG. 7 shows the outline of the configuration of the clock system switching circuit in this modification. However, the same parts as those of the clock system switching circuit in the present embodiment shown in FIG. 2 are designated by the same reference numerals, and the description thereof will be appropriately omitted. In the clock system switching circuit according to this modification, the differential output pulse 48 ₁ output from the differentiating circuit 42 ₁ is input to the selector 60. "0" is fixedly input to the other side of the selector 60, and can be selectively selected by the selector control signal 61. The selection output 62 is used as the load value input of the frequency dividing circuit 41 ₁ in this embodiment. As the selector control signal 61, the first system abnormality detection signal generated based on the clock disconnection state of the first system detected by the abnormality detection unit (not shown) is used, and the first system input clock is normally Try to run.

As a result, under normal conditions, the selector control signal 61 is selected so that "0" is constantly input to the frequency dividing circuit 41 _1, and the differential output pulse of the _second system frequency dividing clock 32 ₂ is selected. Is not reflected in the first system. Therefore, the second system adjusts the phase of the divided clock according to the phase of the first system. On the other hand, when an abnormality in the first system is detected, the selector 60 reflects the frequency-divided clock of the second system in the first system so that the first system can divide the frequency-divided clock of the second system. The phase is adjusted to match the phase of. By providing the guard circuit including the selector 60 in this manner, the differential output pulse of the divided clock of the first system is steadily provided to the second system and the differential output pulse of the divided clock of the second system is constantly provided to the second system. The simultaneous input to the first system is prevented to prevent the operating state of the clock system switching circuit in this modification from becoming unstable.

The clock system switching circuits in the present embodiment and the modification are constructed so as to synchronize with each other in the first and second systems. For example, only the first system is used as the second system. It is also possible to achieve simplification of the circuit by simply synchronizing the circuits.

[0049]

As described above, according to the invention described in claim 1, one of the two systems is disconnected due to a failure or the like.
Even if it becomes, match the phases of the clocks of both systems.
Moreover, since the phase is adjusted based on the divided clock with the low frequency, even if the clock frequency is improved, the synchronization is easier than the phase based on the clock before the division. Can be taken.
Furthermore, regardless of the phase shift of the input clocks of both systems, the continuity of the output clocks at the time of system switching can be maintained with a very simple configuration. Also, for both divided clocks
Switching control performed near rising or falling
To avoid the continuity of the clock signal during system switching.
Can be kept.

Further , according to the invention of claim 2, the steady state
The level change detection result of the divided clock of the first system is
To the second system, the detection result of the level change of the divided clock of the second system
Avoids being input to the first system at the same time
Occurs depending on the mounting conditions, manufacturing conditions, and signal input conditions.
It is possible to suppress the occurrence of oscillation state that may
Preventing the operating state of the switching circuit from becoming unstable
You can Also, the rise of both divided clocks or
System switching by avoiding the switching control performed near the falling edge
It is possible to maintain continuity of the clock signal with time.

According to the third aspect of the present invention, the level change detection result of the divided clock of the first system is steadily applied to the second system and the level change detection result of the divided clock of the second system is detected. there the first system, since avoids simultaneously input, suppressing mounting conditions and production conditions, the generation of oscillating state that may occur in dependence on the signal input condition, the clock-based switching circuitry It is possible to prevent the operating state of the device from becoming unstable.

Further, according to the invention of claim 4,
It is possible to avoid the switching control performed near the rising or falling of both divided clocks and maintain the continuity of the clock signal at the time of system switching.

Further, according to the invention of claim 5, the first
And second level change detecting means, since in detecting the rising or falling, it is possible to simplify the circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a principle configuration of a clock system switching circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an outline of a configuration of a clock system switching circuit in the present embodiment.

FIG. 3 is a block diagram showing a main part of the configuration of a differentiating circuit in the present embodiment.

FIG. 4 is a block diagram showing a main part of a retiming circuit according to the present exemplary embodiment.

FIG. 5 is a timing chart showing operation waveforms of respective parts of the retiming circuit in the present embodiment.

FIG. 6 is a timing chart showing a synchronizing operation of the clock system switching circuit in the present embodiment.

FIG. 7 is a block diagram showing an outline of a configuration of a clock system switching circuit in a modified example of the present invention.

FIG. 8 is a block diagram showing an outline of a configuration of a conventionally proposed clock system switching circuit.

9 is a timing chart showing the operation of the clock system switching circuit shown in FIG.

[Explanation of symbols]

30 ₁ First system input clock 30 ₂ Second system input clock 31 ₁ , 31 ₂ , 41 ₁ , 41 ₂ Dividing circuit 32 ₁ First system dividing clock 32 ₂ Second system dividing clock 33, 43 selector 34 ₁ , 34 ₂ pulse signal 35 switching signal 36 retiming circuit 37 retiming switching signal 38 output clock 39 ₁ , 39 ₂ input clock waveform 40 ₁ , 40 ₂ divided clock waveform 42 ₁ , 42 ₂ differentiating circuit 44 selection Divided clock 48 ₁ and 48 ₂ differential output pulse

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 7/00 H03K 5/00 H04L 1/22

Claims (5)

(57) [Claims] 1. A first frequency-dividing input clock of a first system
Frequency dividing means and a first frequency dividing means generated by dividing the frequency by the first frequency dividing means.
A first level change detecting means for detecting a change in the logic level of the divided clock, a second dividing means for dividing the input clock of the second system, and a frequency dividing means for dividing the input clock by the second dividing means. Generated and generated second
Second level change detecting means for detecting a change in the logic level of the divided clock, and a first level presetting the divided output of the first frequency dividing means based on the detection result of the second level change detecting means. Presetting means, second presetting means for presetting the frequency-divided output of the second frequency-dividing means according to the detection result of the first level change detecting means, and the first and second based on a predetermined switching signal. Selecting means for selectively selecting one of the divided clocks, and multiplication for multiplying either one of the first and second divided clocks in synchronization with one of rising and falling edges thereof. Means and a switching signal at the time of selection of the selecting means by retiming the switching signal at the other edge different from the edge of the multiplied clock generated by being multiplied by the multiplying means. Clock system switching circuitry, characterized by comprising a retiming means for generating. 2. A first frequency dividing means for dividing an input clock of a free-running first system, and a first frequency dividing means for dividing the input clock by the first frequency dividing means.
A first level change detecting means for detecting a change in the logic level of the divided clock, a second dividing means for dividing the input clock of the second system, and a frequency dividing means for dividing the input clock by the second dividing means. Generated and generated second
Second level change detecting means for detecting a change in the logic level of the divided clock, a disconnection state determining means for determining the disconnection state of the input clock of the first system, and the first state by the disconnection state determining means. First presetting means for presetting the frequency-divided output of the first frequency-dividing means based on the detection result of the second level-change detecting means when it is determined that the input clock of the system is disconnected. Second presetting means for presetting the frequency-divided output of the second frequency-dividing means on the basis of the detection result of the first level-change detecting means, and one of the first and second frequency-dividing clocks based on a predetermined switching signal. Selecting means for selectively selecting the frequency dividing means, and multiplying means for multiplying either one of the first and second divided clocks in synchronization with one of the rising and falling edges thereof. Retiming means for generating a switching signal at the time of selection by the selecting means by retiming the switching signal at the other edge different from the edge of the multiplied clock generated by being multiplied by the multiplying means. Clock system switching circuit. 3. A first frequency dividing means for dividing an input clock of a free-running first system, and a first frequency dividing means for dividing the input clock by the first frequency dividing means.
A first level change detecting means for detecting a change in the logic level of the divided clock, a second dividing means for dividing the input clock of the second system, and a frequency dividing means for dividing the input clock by the second dividing means. Generated and generated second
Second level change detecting means for detecting a change in the logic level of the divided clock, a disconnection state determining means for determining the disconnection state of the input clock of the first system, and the first state by the disconnection state determining means. When it is determined that the input clock of the system is a state other than the disconnected state, the output of the first frequency dividing means is self-running by the input clock of the first system, while the input clock of the first system is in the disconnected state. When it is determined that the first divided clock has the same phase as the second divided clock at the timing when the second level change detection means detects the change in the logic level of the second divided clock. First preset means for presetting the second divided clock at the timing when the first level change detection means detects a change in the logic level of the first divided clock. A second presetting means for presetting the same phase as the clock; and a selecting means for selectively selecting one of the first and second divided clocks based on a predetermined switching signal. Clock system switching circuit. 4. A multiplication means for multiplying either one of the first and second divided clocks in synchronization with one of the rising and falling edges thereof, and a multiplication means for multiplying by the multiplication means. 4. The clock system switching circuit according to claim 3, further comprising retiming means for generating a switching signal of the selecting means by retiming the switching signal at the other edge different from the edge of the multiplied clock. 5. The clock system switching circuit according to claim 1, wherein the first and second level change detecting means detect a rising edge or a falling edge.