JP3501059B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which operates in synchronization with a clock signal, for example, LS.
The present invention relates to a semiconductor integrated circuit that is suitable for a configuration such as I (large-scale integrated circuit).

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit which operates in synchronization with a clock signal, one clock signal is supplied to each internal sequential circuit so that these sequential circuits operate at the same timing. This type of semiconductor integrated circuit is, for example, incorporated as a part of an LSI, and as shown in FIG. 5, conventionally, is a delay type device that captures an input signal Si1 in synchronization with a clock signal ck and outputs an output signal S11. It has a flip-flop (hereinafter referred to as “D-FF”) 11. On the output side of D-FF11,
A combination circuit 12 that receives the output signal S11 and another signal (not shown) and outputs the output signal S12 is connected. The combination circuit 12 is, for example, AND circuits 12a and 12
b, 12c, 12d, 12e, which are sequentially connected in series. AND circuits 12a, 12b, 12c,
Another logic circuit (not shown) is connected to the other input terminals of 12d and 12e. The combination circuit 12 has the maximum propagation delay time T12 in this semiconductor integrated circuit. Therefore, the cycle of the clock signal ck is set to the propagation delay time T12 or more. AND circuit 12e
The output terminal of the D-FF which takes in the output signal S12 in synchronization with the clock signal ck and outputs the output signal S13.
13 is connected.

Further, this semiconductor integrated circuit has an input signal S
It has a D-FF 21 which takes in i2 in synchronization with the clock signal ck and outputs an output signal S21. D-FF
A combination circuit 22 for inputting the output signal S21 and another signal (not shown) and outputting the output signal S22 is connected to the output side of the circuit 21. The combination circuit 22 is, for example, AN
It has D circuits 22a, 22b and 22c, which are sequentially connected in series. AND circuits 22a, 22b, 22c
Another logic circuit (not shown) is connected to the other input terminal. The combination circuit 22 has a propagation delay time T22.
(However, T22 ≦ T12). AND circuit 2
The output signal S22 is fed to the clock signal c at the output terminal of 2c.
D- which captures in synchronization with k and outputs an output signal S23
The FF 23 is connected.

Further, the semiconductor integrated circuit is provided with a D-FF 31 which takes in the input signal Si3 in synchronization with the clock signal ck and outputs the output signal S31.
The output side of the D-FF 31 is connected to a combination circuit 32 which inputs the output signal S31 and another signal (not shown) and outputs the output signal S32. The combination circuit 32 has, for example, an AND circuit 32a, and another logic circuit (not shown) is connected to the other input terminal of the AND circuit 32a. The combination circuit 32 has a propagation delay time T32 (where T32 ≦ T22). AND circuit 32a
The output terminal of the D-FF which takes in the output signal S32 in synchronization with the clock signal ck and outputs the output signal S33.
33 is connected.

FIG. 6 is a time chart of signals at various parts for explaining the operation of the semiconductor integrated circuit of FIG. 5, in which the vertical axis represents the logic level and the horizontal axis represents time. The operation of the semiconductor integrated circuit of FIG. 5 will be described with reference to this figure. At time t1, the input signal Si1 is captured by the D-FF 11 in synchronization with the clock signal ck,
The output signal S11 is output from F11. Output signal S1
1 is input to the combination circuit 12, and the propagation delay time T12
Is passed, the output signal S12 from the combination circuit 12
Is output. At time t2, the output signal S12 is
It is taken into the D-FF 13 in synchronization with the clock signal ck, and the D-FF 13 outputs the output signal S13.

At time t1, the input signal Si2
Is taken into the D-FF 21 in synchronization with the clock signal ck, and the D-FF 21 outputs the output signal S21.
The output signal S21 is input to the combination circuit 22, and after the propagation delay time T22 has elapsed, the output signal S22 is output from the combination circuit 22. At time t2, the output signal S22 is synchronized with the clock signal ck and the D-FF 23
And the output signal S23 is output from the D-FF 23. Further, at time t1, the input signal Si3
Is taken into the D-FF 31 in synchronization with the clock signal ck, and the output signal S31 is output from the D-FF 31.
The output signal S31 is input to the combination circuit 32, and after the propagation delay time T32 has elapsed, the combination circuit 32 outputs the output signal S32. At time t2, the output signal S32 is synchronized with the clock signal ck and the D-FF 33
And the output signal S33 is output from the D-FF 33.

[0007]

However, the conventional semiconductor integrated circuit described above has the following problems.
In the conventional semiconductor integrated circuit, the clock signal ck is DF
F11,13,21,23,31,33 are commonly supplied to these D-FFs 11,13,21,23,31,
33 operates at the same timing. However, in recent years, the number of sequential circuits such as flip-flops that operate simultaneously in synchronization with a clock signal has increased dramatically due to the progress of LSIs in semiconductor integrated circuits. Therefore, there is a problem that power supply noise due to simultaneous operation of these sequential circuits increases and malfunction occurs. Further, when the propagation delay time of the combinational circuit connected between two certain sequential circuits is extremely short, there is a problem that a malfunction occurs due to the racing between these sequential circuits.

The present invention has been made in view of the above circumstances, and provides a semiconductor integrated circuit in which malfunction is prevented by reducing power supply noise and avoiding racing between a plurality of sequential circuits. Has an aim.

[0009]

In order to solve the above-mentioned problems, the invention according to claim 1 takes in first input data in synchronization with a clock signal, outputs first output data, and outputs the first output data. A first flip-flop that holds the first output data until the edge of the next cycle of the clock signal arrives; and a first propagation delay time T1 corresponding to the minimum value of the cycle of the clock signal. A first combination circuit for inputting one or a plurality of second input data including one output data and performing a predetermined process to output second output data; and the first combination circuit in synchronization with the clock signal. A second flip-flop that receives the second output data, outputs the third output data, and holds the third output data until the edge of the next cycle of the clock signal comes; The third A third flip-flop that receives the input force data, outputs the fourth output data, and holds the fourth output data until the edge of the next cycle of the clock signal arrives; and the second propagation delay time T2 ( However, T2
≦ T1), which inputs a single or a plurality of fourth input data including the fourth output data, performs a predetermined process, and outputs fifth output data; A fourth flip-flop which takes in the fifth output data in synchronization with the clock signal, outputs sixth output data, and holds the sixth output data until the edge of the next cycle of the clock signal comes. A semiconductor integrated circuit including a third propagation delay time T3 (where T3 ≦ T1-T
2) is provided, and a delay circuit for delaying the clock signal and giving it to the third flip-flop is provided.

The invention according to claim 2 relates to the semiconductor integrated circuit according to claim 1, wherein the delay circuit is composed of a variable delay circuit in which the propagation delay time T3 is adjusted based on a given control signal. It is characterized by

According to a third aspect of the present invention, the first input data is fetched in synchronization with the clock signal to output the first output data, and the first output data is the edge of the next cycle of the clock signal. A first flip-flop for holding the first input data and a propagation delay time T1 corresponding to the minimum value of the cycle of the clock signal, and inputting one or more second input data including the first output data. A first combination circuit for performing a predetermined process to output second output data, and taking in the second output data in synchronization with the clock signal to output third output data, A second flip-flop that holds the third output data until the edge of the next cycle of the clock signal arrives; and a third flip-flop that takes in the third input data in synchronization with the clock signal and outputs the fourth output data. , A third flip-flop that holds the fourth output data until the edge of the next cycle of the clock signal arrives, and a fourth propagation delay time T4 (however, T4
≦ T1), which inputs a single or a plurality of fourth input data including the fourth output data, performs a predetermined process, and outputs fifth output data; A fourth flip-flop which takes in the fifth output data in synchronization with the clock signal, outputs sixth output data, and holds the sixth output data until the edge of the next cycle of the clock signal comes. A semiconductor integrated circuit having a fifth propagation delay time T5, delaying the clock signal, and applying the delayed clock signal to the third flip-flop.
And the sixth propagation delay time T6 (where T6 ≧
A second delay circuit having T4 + T5-T1 and T6 <T5) and delaying the clock signal and applying the delayed clock signal to the fourth flip-flop is provided.

A fourth aspect of the present invention relates to the semiconductor integrated circuit according to the third aspect, wherein the first delay circuit adjusts the propagation delay time T5 based on a given first control signal. The second variable delay circuit is composed of a first variable delay circuit, and the second variable delay circuit is composed of a second variable delay circuit in which the propagation delay time T6 is adjusted based on a given second control signal. Is characterized by.

According to a fifth aspect of the present invention, the first input data is fetched in synchronization with the clock signal to output the first output data, and the first output data is the edge of the next cycle of the clock signal. A first flip-flop that holds the first output data and a first flip-flop having the first propagation delay time T1 corresponding to the minimum value of the cycle of the clock signal, and a second input or a plurality of second inputs including the first output data. A first combination circuit that inputs data, performs a predetermined process and outputs second output data, and takes in the second output data in synchronization with the clock signal and outputs third output data And a second flip-flop that holds the third output data until the edge of the next cycle of the clock signal comes, and a fourth output data that takes in the third input data in synchronization with the clock signal. Out And holding the fourth output data until the edge of the next cycle of the clock signal comes
And a second propagation delay time T2 (provided that T2 ≦ T1), and input a single or a plurality of fourth input data including the fourth output data and perform a predetermined process. A second combination circuit for outputting fifth output data; and, taking the fifth output data in synchronization with the clock signal, outputting sixth output data, and outputting the sixth output data by the clock. A semiconductor integrated circuit including a fourth flip-flop that holds the edge of the next cycle of the signal, and a propagation delay time is adjusted based on a given first control signal to delay the clock signal. And a first variable delay circuit for giving to the first flip-flop, and a propagation delay time is adjusted based on the given second control signal to delay the clock signal and give it to the second flip-flop. A second variable delay circuit that adjusts a propagation delay time based on a given third control signal, delays the clock signal, and provides the third flip-flop to the third flip-flop. 4th given
And a fourth variable delay circuit for adjusting the propagation delay time based on the control signal, delaying the clock signal, and providing the delayed clock signal to the fourth flip-flop.

[0014]

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a circuit diagram showing an electrical configuration of a main part of a semiconductor integrated circuit according to a first embodiment of the present invention. In the semiconductor integrated circuit of this form, as shown in FIG.
Is taken in in synchronization with the clock signal ck to output the output signal S4.
A first flip-flop that outputs 1 (for example, DF
F) 41 is included. The output side of the D-FF 41 is connected with a first combination circuit 42 which inputs the output signal S41 and another signal (not shown) and outputs the output signal S42. The combination circuit 42 is, for example, an AND circuit 42a,
It has 42b, 42c, 42d, and 42e, which are sequentially connected in series. AND circuits 42a, 42b, 42
Other logic circuits (not shown) are connected to the other input terminals of c, 42d, and 42e. The combination circuit 42 has the maximum propagation delay time T42 in this semiconductor integrated circuit. Therefore, the cycle of the clock signal ck is set to the propagation delay time T42 or more. AND circuit 4
The output signal S42 is supplied to the output terminal of 2e as the clock signal c.
Second, which takes in in synchronization with k and outputs an output signal S43
The flip-flop (for example, D-FF) 43 is connected.

Further, this semiconductor integrated circuit has an input signal S
It has a third flip-flop (for example, D-FF) 51 which takes in i2 in synchronization with the delayed clock signal S54 and outputs the output signal S51. A second combination circuit 52 that inputs the output signal S51 and another signal (not shown) to the output side of the D-FF 51 and outputs the output signal S52.
Are connected. The combination circuit 52 has, for example, AND circuits 52a, 52b, 52c, which are sequentially connected in cascade. Other logic circuits (not shown) are connected to the other input terminals of the AND circuits 52a, 52b, 52c. The combination circuit 52 has a propagation delay time T52 (where T52 ≦ T42). AND circuit 52c
A fourth flip-flop (for example, D-FF) 53 that receives the output signal S52 in synchronization with the clock signal ck and outputs the output signal S53 is connected to the output terminal of the. The clock input terminal C of the D-FF 51 is connected to the delay circuit 54 which inputs the clock signal ck and outputs the delayed clock signal S54. The delay circuit 54 has, for example, buffers 54a and 54b, which are sequentially connected in cascade. The delay circuit 54 has a propagation delay time T54 (where T54 ≦ T42−T52).

Further, the semiconductor integrated circuit is provided with a D-FF 61 which takes in the input signal Si3 in synchronization with the delayed clock signal S64 and outputs the output signal S61. A combination circuit 62 that inputs the output signal S61 and another signal (not shown) and outputs the output signal S62 is connected to the output side of the D-FF 61. Combination circuit 6
2 has, for example, an AND circuit 62a, and the AND circuit 6a
Another logic circuit (not shown) is connected to the other input terminal of 2a. The combination circuit 62 has a propagation delay time T6.
2 (however, T62 ≦ T52). The output terminal of the AND circuit 62a is connected to the D-FF 63 which takes in the output signal S62 in synchronization with the delayed clock signal S65 and outputs the output signal S63. The clock input terminal C of the D-FF 61 is connected to the delay circuit 64 that inputs the clock signal ck and outputs the delayed clock signal S64. The delay circuit 64 includes, for example, a buffer 64a,
It has 64b, 64c, 64d, 64e, and 64f, and these are sequentially connected in cascade. Delay circuit 64
Has a propagation delay time T64. The clock input terminal C of the D-FF 63 is connected to the delay circuit 65 that inputs the clock signal ck and outputs the delayed clock signal S65. The delay circuit 65 is, for example, a buffer 65.
a and 65b, which are sequentially connected in cascade. The delay circuit 65 has a propagation delay time T65 (where T65 ≧ T62 + T64−T42, and T65 <T
64).

FIG. 2 is a time chart of signals of respective parts for explaining the operation of the semiconductor integrated circuit of this embodiment.
The vertical axis represents the logic level, and the horizontal axis represents the time. The operation of the semiconductor integrated circuit of this embodiment will be described with reference to this figure. At time t1, the input signal Si1 is taken in by the D-FF 41 in synchronization with the clock signal ck,
The output signal S41 is output from the D-FF 41. The output signal S41 is input to the combination circuit 42, and after the propagation delay time T42 has elapsed, the combination circuit 42 outputs the output signal S42. At time t2, the output signal S
42 is taken into the D-FF 43 in synchronization with the clock signal ck, and the output signal S43 is output from the D-FF 43.

At time t3 when the propagation delay time T54 has elapsed from time t1, the input signal Si2 is taken in by the D-FF 51 in synchronization with the delayed clock signal S54.
An output signal S51 is output from the D-FF 51. The output signal S51 is input to the combination circuit 52, and after the propagation delay time T52 has elapsed, the output signal S52 is output from the combination circuit 52. At time t2, the output signal S
52 is taken into the D-FF 53 in synchronization with the clock signal ck, and the output signal S53 is output from the D-FF 53. In this case, since the propagation delay time T52 is shorter than the propagation delay time T42, the delayed clock signal S54 is shorter than the clock signal ck by the propagation delay time T54 (however, T54
This semiconductor integrated circuit operates normally even if it is delayed by ≦ T42−T52).

Further, from the time t1, the propagation delay time T64
At time t4 when has elapsed, the input signal Si3 is taken in by the D-FF 61 in synchronization with the delayed clock signal S64, and the D-FF 61 outputs the output signal S61.
The output signal S61 is input to the combination circuit 62, and at the time t5 when the propagation delay time T62 has elapsed, the combination circuit 62 is input.
Outputs an output signal S62. At time t5 when the propagation delay time T65 has elapsed from time t2, the output signal S
62 is a D-FF6 in synchronization with the delayed clock signal S65.
3 and the output signal S63 is output from the D-FF 63. In this case, the delay clock signal S64 is longer than the propagation delay time T64 (however, T64
This semiconductor integrated circuit operates normally even if it is delayed by ≦ T42 + T65−T62).

As described above, in the first embodiment,
Since the operation timings of the D-FFs 41, 43, 51, 53, 61, 63 are not all the same, the power supply noise due to the simultaneous operation is reduced, and the malfunction of the semiconductor integrated circuit can be prevented. Further, in this embodiment, since the propagation delay time T65 is shorter than the propagation delay time T64, even if the propagation delay time T62 of the combination circuit 62 is extremely short, malfunction due to racing between the D-FF61 and the D-FF63. Can be prevented.

Second Embodiment FIG. 3 shows a second embodiment of the present invention.
2 is a circuit diagram showing an electrical configuration of a main part of the semiconductor integrated circuit according to the embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are designated by common reference numerals. In the semiconductor integrated circuit of this form, as shown in FIG.
The variable delay circuit 44 is connected to the clock input terminal C of 41. The variable delay circuit 44 is a circuit that adjusts the propagation delay time T44 of the clock signal ck based on the control signal S70a and outputs the delayed clock signal S44. D
The variable delay circuit 4 is connected to the clock input terminal C of the FF43.
5 is connected. The variable delay circuit 45 controls the control signal S
70b based on the propagation delay time T4 of the clock signal ck
5 is a circuit that adjusts 5 and outputs the delayed clock signal S45.

Further, in this semiconductor integrated circuit, instead of the delay circuit 54 in FIG. 1, a variable delay circuit 55 having a different structure is used.
Is provided. The variable delay circuit 55 controls the control signal S7.
0c based on the propagation delay time T55 of the clock signal ck
Of the delay clock signal S55 and outputs the delayed clock signal S55. The variable delay circuit 56 is connected to the clock input terminal C of the D-FF 53. The variable delay circuit 56 is a circuit that adjusts the propagation delay time T56 of the clock signal ck based on the control signal S70d and outputs the delayed clock signal S56. Further, in this semiconductor integrated circuit, variable delay circuits 66 and 67 having different configurations are provided in place of the delay circuits 64 and 65 in FIG. Variable delay circuit 66
Is a circuit that adjusts the propagation delay time T66 of the clock signal ck based on the control signal S70e and outputs the delayed clock signal S66. The variable delay circuit 67 has a control signal S
70f based on the propagation delay time T6 of the clock signal ck
7 is a circuit for adjusting 7 and outputting the delayed clock signal S67. Variable delay circuits 44, 45, 55, 56, 66, 6
A delay setting circuit 70 is connected to 7. The delay setting circuit 70 is composed of, for example, a read-only memory or the like, and the control signal S70 is based on the given setting value in.
a, S70b, S70c, S70d, S70e, S70
It is a circuit that outputs f. Others are the same as that of FIG.

FIG. 4 is a circuit diagram showing an example of the variable delay circuit 44. The variable delay circuit 44 uses the clock signal c
A buffer 44 that inputs k and outputs an output signal S44a
a. A selector 44b that selects the clock signal ck or the output signal S44a based on the control signal S70a and outputs the output signal S44b is connected to the output side of the buffer 44a. A buffer 44c that inputs the output signal S44b and outputs the output signal S44c is connected to the output side of the selector 44b, and the output signal S44c is input and the output signal S44 at the output side of the buffer 44c.
A buffer 44d that outputs d is connected. A selector 44e that selects the output signal S44b or the output signal S44d based on the control signal S70a and outputs the output signal S44e is connected to the output side of the buffer 44d.

On the output side of the selector 44e, the output signal S
A buffer 44f that inputs 44e and outputs an output signal S44f is connected, and a buffer 44g that inputs the output signal S44f and outputs an output signal S44g is connected to the output side of the buffer 44f. The output signal S44g is input to the output side of the buffer 44g to output the output signal S44h.
Is connected to a buffer 44h for outputting
The output signal S44h is input to the output side of h to output the output signal S44.
A buffer 44i that outputs 44i is connected. A selector 44j that selects the output signal S44e or the output signal S44i based on the control signal S70a and outputs the output signal S44 is connected to the output side of the buffer 44i. The variable delay circuits 45, 55, 56, 66, 67 also have the same configuration as the variable delay circuit 44.

The operation of the semiconductor integrated circuit of this embodiment differs from the operation of the semiconductor integrated circuit of the first embodiment in the following points. That is, the 3-bit control signal S70a
Is set to "111", the selector 44b selects the clock signal ck, the selector 44e selects the output signal S44b, and the selector 44j selects the output signal S44e, and the propagation delay time T44 is set to zero. Similarly, the control signal S
70b is set to "111", for example, and the propagation delay time T
45 is set to 0. The control signal S70c is, for example, "1".
01 "and the propagation delay time T55 is set to the same value as the propagation delay time T54 of the first embodiment. The control signal S70d is set to" 111 "and the propagation delay time T56 is set to 0, for example. The control signal S70e is set to, for example, “000”, the propagation delay time T66 is set to the same value as the propagation delay time T64 of the first embodiment, and the control signal S70f is set to, for example, “101” to propagate the signal. The delay time T67 is set to the same value as the propagation delay time T65 of the first embodiment, and the same operation as that of the first embodiment is performed in this setting state.

As described above, in the second embodiment,
Each D-FF 41, 45, 51, 5 in the semiconductor integrated circuit
Variable delay circuits 44, 45, 5 are provided for each of 3, 61, 63
5, 56, 66 and 67 are provided respectively, and the respective propagation delay times are set by the delay setting circuit 70.
In addition to the advantages of the above embodiment, each D-FF 41, 45, 5
There is an advantage that the labor of adding a delay circuit to 1, 53, 61, 63 later can be saved, and even if the semiconductor integrated circuit is changed, the resetting can be easily performed.

The embodiment of the present invention has been described in detail above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and there are design changes and the like within the scope not departing from the gist of the present invention. Also included in the present invention. For example, D-
The FFs 41, 45, 51, 53, 61, 63 may be any circuits as long as they are sequential circuits that operate based on the clock signal ck. Further, the internal configuration of the combination circuits 42, 52, 62 may be any circuit as long as it constitutes a combination circuit. However, the combination circuit 42 has the maximum propagation delay time T42 in the semiconductor integrated circuit. In addition, the delay circuits 54, 64, 65 and the variable delay circuit 44,
The internal configuration of 45, 55, 56, 66, 67 may be any circuit as long as it produces a propagation delay time.

[0029]

As described above, according to the configuration of the present invention, the operation timings of the respective flip-flops are not the same, so that the power supply noise caused by the simultaneous operation can be reduced and the semiconductor integrated circuit Malfunctions can be prevented.
Further, since the propagation delay time T6 is shorter than the propagation delay time T5, even if the propagation delay time T4 of the second combination circuit is extremely short, the racing between the third flip-flop and the fourth flip-flop can be performed. Malfunctions can be prevented. Furthermore, since a variable delay circuit is provided in advance for each flip-flop in the semiconductor integrated circuit and each propagation delay time is set by the delay setting circuit, there is no need to add a delay circuit to each flip-flop later. Further, it is possible to omit the setting and to easily reset the semiconductor integrated circuit even if the semiconductor integrated circuit is changed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an electrical configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the semiconductor integrated circuit.

FIG. 3 is a circuit diagram showing an electrical configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a variable delay circuit 44.

FIG. 5 is a circuit diagram showing an electrical configuration of a conventional semiconductor integrated circuit.

FIG. 6 is a time chart for explaining the operation of the semiconductor integrated circuit.

[Explanation of symbols]

41, 43, 51, 53, 61, 63 D-FF 42, 52, 62 Combination circuit 44, 45, 55, 56, 66, 67 Variable delay circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 19/003-19/096 G06F 1/10-1/12

Claims (5)

(57) [Claims] 1. A first input data is received in synchronization with a clock signal to output first output data, and the first output data is held until an edge of the next cycle of the clock signal comes. 1 flip-flop, a first propagation delay time T1 corresponding to the minimum value of the cycle of the clock signal, and a predetermined input by inputting one or a plurality of second input data including the first output data. And a first combinational circuit that outputs the second output data by performing the process of step 1), captures the second output data in synchronization with the clock signal, outputs the third output data, and outputs the third output data. A second flip-flop for holding the output data until the edge of the next cycle of the clock signal arrives; a third flip-flop for fetching the third input data in synchronization with the clock signal to output a fourth output data; 4 output data A third flip-flop for holding the data until the edge of the next cycle of the clock signal arrives, a second propagation delay time T2 according to equation (1), and a singular number containing the fourth output data or A second combination circuit for inputting a plurality of fourth input data and performing a predetermined process to output a fifth output data; and a second combination circuit for fetching the fifth output data in synchronization with the clock signal. And a fourth flip-flop for outputting the sixth output data and holding the sixth output data until the edge of the next cycle of the clock signal comes, a third integrated circuit according to equation (2) is provided. A semiconductor integrated circuit comprising a delay circuit having a propagation delay time T3, which delays the clock signal and applies the delayed clock signal to the third flip-flop. T2 ≦ T1 (1) T3 ≦ T1-T2 (2) 2. The semiconductor integrated circuit according to claim 1 , wherein the delay circuit is composed of a variable delay circuit in which the propagation delay time T3 is adjusted based on a given control signal. 3. A first input data is received in synchronization with a clock signal to output first output data, and the first output data is held until an edge of the next cycle of the clock signal comes. 1 flip-flop, a first propagation delay time T1 corresponding to the minimum value of the cycle of the clock signal, and a predetermined input by inputting one or a plurality of second input data including the first output data. And a first combinational circuit that outputs the second output data by performing the process of step 1), captures the second output data in synchronization with the clock signal, outputs the third output data, and outputs the third output data. A second flip-flop for holding the output data until the edge of the next cycle of the clock signal arrives; a third flip-flop for fetching the third input data in synchronization with the clock signal to output a fourth output data; 4 output data A third flip-flop that holds the data until the edge of the next cycle of the clock signal comes, and a fourth propagation delay time T4 according to equation (3), and a singular number including the fourth output data or A second combination circuit for inputting a plurality of fourth input data and performing a predetermined process to output a fifth output data; and a second combination circuit for fetching the fifth output data in synchronization with the clock signal. And a fourth flip-flop that outputs the sixth output data and holds the sixth output data until the edge of the next cycle of the clock signal comes. A first delay circuit having a propagation delay time T5, which delays the clock signal and gives it to the third flip-flop, and a sixth propagation delay time T6 according to equation (4), Delay before A semiconductor integrated circuit comprising: a second delay circuit provided to the fourth flip-flop. T4 ≦ T1 (3) T6 ≧ T4 + T5-T1 and T6 <T5 (4) 4. The first delay circuit is provided with a first first
Of the first variable delay circuit, the propagation delay time T5 of which is adjusted based on the control signal of the second delay circuit. 4. The semiconductor integrated circuit according to claim 3 , comprising a second variable delay circuit which is adjusted. 5. A first input data is fetched in synchronization with a clock signal to output first output data, and the first output data is held until an edge of the next cycle of the clock signal arrives. 1 flip-flop, a first propagation delay time T1 corresponding to the minimum value of the cycle of the clock signal, and a predetermined input by inputting one or a plurality of second input data including the first output data. And a first combinational circuit that outputs the second output data by performing the process of step 1), captures the second output data in synchronization with the clock signal, outputs the third output data, and outputs the third output data. A second flip-flop for holding the output data until the edge of the next cycle of the clock signal arrives; a third flip-flop for fetching the third input data in synchronization with the clock signal to output a fourth output data; 4 output data A third flip-flop that holds the data until an edge of the next cycle of the clock signal comes, and a second propagation delay time T2 according to equation (5), and a singular number including the fourth output data or A second combination circuit for inputting a plurality of fourth input data and performing a predetermined process to output a fifth output data; and a second combination circuit for fetching the fifth output data in synchronization with the clock signal. A fourth flip-flop for outputting the sixth output data and holding the sixth output data until the edge of the next cycle of the clock signal arrives. A first variable delay circuit for delaying the clock signal to give it to the first flip-flop, and a propagation delay time adjusted on the basis of the given second control signal. A second variable delay circuit for delaying the clock signal and giving it to the second flip-flop; and a propagation delay time adjusted on the basis of the given third control signal to delay the clock signal. A third variable delay circuit for giving to the third flip-flop; a propagation delay time adjusted on the basis of the given fourth control signal, and delaying the clock signal to give it to the fourth flip-flop. And a variable delay circuit of No. 4. T2 ≦ T1 (5)