JP3501101B2 - Semiconductor device evaluation method and semiconductor device manufacturing method using this evaluation method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of evaluating a semiconductor device by evaluating the amount of scraping of a semiconductor substrate in a contact hole, and a method of manufacturing a semiconductor device using such an evaluation method.

[0002]

2. Description of the Related Art A contact hole in a semiconductor device is an important part for forming an electrode (wiring) of a device. The contact hole is formed by forming an insulating film on the semiconductor substrate and then performing dry etching or the like by a photolithography technique. At this time, the contact hole may not be opened to the semiconductor substrate unless the etching condition has a sufficient margin due to the variation of the thickness of the insulating film and the decrease of the etching rate due to the change of equipment over time.

Conventionally, in the management of this contact hole, a test pattern similar to that of a device contact hole is formed on a semiconductor substrate, and it is judged from the resistance value in this contact hole whether or not a current is applied. It was done by checking whether or not it was opened.

However, in this method, since only the resistance value in the contact hole is measured, it is understood that the etching condition for the contact hole is bad only when the product becomes defective. Therefore, in order to change the etching conditions before the product becomes defective, the semiconductor substrate is cut in the thickness direction and the cross-section inspection is performed to measure the scraped amount of the semiconductor substrate and confirm the etching margin. .

[0005]

However, since this cross-section inspection is very time-consuming and is an inspection performed by destroying the semiconductor substrate, it is a unit (hereinafter, referred to as LOT) that goes through each manufacturing process of the device at the same time. It was difficult to carry out a cross-section inspection for each unit, and it was only possible to do it regularly.
However, in order to maintain high reliability and yield of products, it is necessary to inspect the amount of scraping of the semiconductor substrate more frequently.

In view of the above problems, the present invention provides a semiconductor device evaluation method capable of evaluating the amount of scraping of a semiconductor substrate in a contact hole without destroying the semiconductor substrate, and a semiconductor device using such an evaluation method. It aims at providing the manufacturing method of.

[0007]

The inventors of the present invention have noticed that the current amplification factor of the bipolar transistor changes depending on the amount of scraping of the semiconductor substrate in the contact hole for the emitter of the bipolar transistor. The details will be described below. FIG. 2 schematically shows the emitter of the bipolar transistor. Although the illustrated example is an NPN type bipolar transistor, a PNP type bipolar transistor can be similarly applied to the present invention.

As shown in FIG. 2, the surface (1) of the semiconductor substrate in the base (P ⁻ ) region (43) of the semiconductor substrate is
The emitter (N ⁺ ) region (45) is formed on the side a), and the insulating film (6) formed on the surface of the semiconductor substrate is etched at the emitter (N ⁺ ) region (45) to form the emitter. A contact hole (73) is formed. Further, the interface between the contact hole and the semiconductor substrate is open to the semiconductor substrate. The semiconductor substrate (emitter (N ⁺ ) region (4
5)) is in a dented state due to shaving, and the distance from the surface (1a) of the semiconductor substrate to the bottom of the dent is defined as the shaving amount (L) of the semiconductor substrate. Then, the wiring (83) is embedded in the contact hole and is in contact with the semiconductor substrate.

The current amplification factor in a bipolar transistor is determined by the ratio of collector current and base current.
Further, the injection efficiency of the electrons injected from the wiring (83) to the emitter (N ⁺ ) region (45) when the bipolar transistor is turned on is determined by the wiring (83) and the emitter (N ⁺ ).
It is determined by the impurity concentration at the interface with the region (45). In general, the impurity concentration of the emitter region (N ⁺ ) is higher in the upper layer and lower in the lower layer.

Therefore, as the amount of scraping in the emitter contact hole (73) increases, the emitter (N
^Since it comes into contact with the wiring (83) in the lower layer of the ( ⁺ ) area (45), the wiring (83) and the emitter (N ⁺ ) area (4
The impurity concentration at the interface with 5) decreases, the collector current decreases, and the value of the current amplification factor decreases. Thus, by measuring the current amplification factor, the amount of scraping of the semiconductor substrate in the contact hole for the emitter can be evaluated.

In view of the above, according to the first aspect of the present invention, there is provided a method for evaluating a semiconductor device, which comprises forming an insulating film (6) on a semiconductor substrate (1) and etching the insulating film to form a contact hole. The current amplification factor of the bipolar transistor (2) formed on the semiconductor substrate is measured to evaluate the amount of abrasion of the semiconductor substrate due to etching in the contact hole.

According to the present invention, as described above, the amount of scraping of the semiconductor substrate in the contact hole (73) for the emitter of the bipolar transistor can be evaluated by measuring the current amplification factor. If the relationship between the amount of semiconductor substrate abrasion in the contact hole for the emitter and the current amplification factor, and the relationship between the amount of semiconductor substrate abrasion in the emitter contact and the amount of semiconductor substrate abrasion in the contact hole to be evaluated are obtained, then Can evaluate the amount of scraping of the semiconductor substrate in the contact hole only by measuring the current amplification factor without breaking the semiconductor substrate.

In the invention of claim 1, a bipolar transistor formed in a device used as a product may be used. However, as in the invention of claim 2, as a test pattern for evaluating a semiconductor device. Alternatively, a bipolar transistor may be formed separately from the device formed on the semiconductor substrate.

Further, in this case, as in the third aspect of the invention, as the bipolar transistor, a contact hole for evaluating the amount of scraping of the semiconductor substrate and a contact hole for an emitter (7) having the same etching characteristics.
3) is used, if the relationship between the amount of shaving of the semiconductor substrate in the contact hole for the emitter and the current amplification factor is obtained in advance, it is possible to evaluate the amount of shaving of the semiconductor substrate from the current amplification factor. It is possible to evaluate the amount of abrasion of the semiconductor substrate.

According to a fourth aspect of the invention, in the invention according to any one of the first to third aspects, a plurality of bipolar transistors are formed and contact holes for a plurality of emitters in each bipolar transistor are formed. It is characterized in that it is formed by changing at least one of the following:

According to the present invention, when various contact holes are formed in the device, various bipolar transistors having contact holes for the emitter corresponding to the conditions such as the shape thereof are formed to form the contact of the device. You can evaluate the holes. In addition, particularly in the process development stage, various kinds of bipolar transistors are formed on the semiconductor substrate and the current amplification factor is measured to evaluate the etching rate according to conditions such as the shape of the contact hole and destroy the semiconductor substrate. It is possible to design an appropriate manufacturing process without doing anything.

In order to form a device on the semiconductor substrate (1), an insulating film (6) is formed on the semiconductor substrate and the insulating film is partially etched. In the method of manufacturing a semiconductor device in which a contact hole for a device is thereby formed, a bipolar transistor (2) is formed in a semiconductor substrate, and the scraping amount of the semiconductor substrate in the contact hole (73) for the emitter of the bipolar transistor and the current amplification factor. After performing a preliminary step for obtaining the relationship between the contact hole and the emitter for the device, the insulating film formed on the semiconductor substrate is partially etched to form the device and the bipolar transistor on the semiconductor substrate. Device formation process for forming contact holes for the bipolar transistor Measure the amplification factor, and based on the relationship between the amount of scraping of the semiconductor substrate and the current amplification factor obtained in the preliminary process, perform the device inspection process to evaluate the amount of scraping of the semiconductor substrate in the contact hole for the device The method is characterized in that a step of adjusting etching conditions in the device forming step is performed based on the scraped amount of the semiconductor substrate in the contact hole for the device.

This makes it possible to determine the amount of abrasion of the semiconductor substrate in the contact hole for the device without destroying the semiconductor substrate only by measuring the current amplification factor. A semiconductor device can be manufactured under various conditions.

The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) An embodiment of the present invention will be described below. In this embodiment, an SOI wafer is used as a semiconductor substrate, and contact holes of devices as products formed on the SOI wafer are evaluated. Specifically, an NPN-type bipolar transistor (hereinafter simply referred to as NP) serving as a test pattern is formed in an SOI wafer.
The contact hole is evaluated by providing an N transistor) separately from the device.

The evaluation of this contact hole was carried out at the interface between the contact hole and the SOI wafer.
It is performed based on the amount by which the I wafer is cut (hereinafter, simply referred to as the amount of Si cut). Further, the present embodiment can be applied not only to the contact holes of transistors but also to the evaluation of contact holes of various devices.

First, the configuration of the semiconductor device of this embodiment will be described. Various desired devices are formed in the device formation region of the SOI wafer, an insulating film is formed on the device, and a contact hole is formed in this insulating film. This contact hole is for electrically connecting the device and an external circuit, and wiring metal is arranged in the contact hole. The purpose of the present embodiment is to confirm the etching margin by evaluating the amount of Si scraped in this contact hole and to evaluate the semiconductor device. Hereinafter, this contact hole is referred to as an evaluation contact hole.

Further, an NPN transistor to be a test pattern is formed in a region different from the device formation region on the SOI wafer. FIG. 1 is a schematic view of the NPN transistor 2, (a) is a top view,
(B) is an AA 'sectional view in (a).

In the SOI wafer 1, a buried N ⁺ layer 41 is arranged on the buried oxide film 3, and a region forming an NPN transistor is insulated and separated from other elements by a trench 51. In addition, the LOC on the SOI wafer 1
The OS oxide film 52 is formed.

A collector (N ⁻ ) region 42 is formed on the buried N ⁺ layer 41 in the region isolated by the trench 51.
And a base (P ⁻ ) region 43 is formed in the surface layer portion of the collector (N ⁻ ) region 42. Also,
A base (P ⁺ ) region 44 and an emitter (N ⁺ ) region 45 are formed in the surface layer portion in the base (P ⁻ ) region 43. Further, a collector (N ⁺ ) region 46 is formed at a position apart from the base (P ⁺ ) region 44 in the surface layer portion of the collector (N ⁻ ) region 42.

An insulating film 6 made of a BPSG film containing boron (B) or phosphorus (P) is deposited on the SOI wafer 1. The insulating film 6 has a collector (N ⁺ ) region 4
6, the base (P ⁺ ) region 44, and the emitter (N ⁺ ) region 45, corresponding to the collector contact hole 71 and the base contact hole 7 for taking the respective potentials on the corresponding portion.
2 and a contact hole 73 for the emitter are formed. Each contact hole 71 to 73 may be one or more, but in the illustrated example, five collector contact holes 71 and five base contact holes 72 and one emitter contact hole 73 are formed.

Here, the contact hole 7 for the emitter
No. 3 has the same shape, size, and arrangement as the contact hole formed in the device forming region, and has the same etching characteristic.

The collector (N ⁺ ) region 46 and the base (P ⁺ ) region 44 are provided to reduce the contact resistance. Further, although each of the regions 41 to 46 and the contact holes 71 to 73 has a rectangular shape in the illustrated example, it may have any shape. Wiring metal is embedded in each of the contact holes 71 to 73 to form a collector wiring 81, a base wiring 82, and an emitter wiring 83, respectively.

Next, S in the evaluation contact hole
A method of evaluating the abrasion amount of i will be described. In Figure 2,
The schematic diagram which expanded the emitter part in FIG.1 (b) is shown. As shown in FIG. 2, at the interface with the SOI wafer 1 in the emitter contact hole 73, the SOI wafer 1 is scraped and recessed, and the distance from the surface 1a of the SOI wafer 1 to the bottom of the recess is Si. Is the amount of abrasion (the amount of abrasion of the semiconductor substrate) L.

First, the contact hole 73 for the emitter
A plurality of NPN transistors 2 having different amounts of shaving of Si are prepared. At this time, as described above, the NPN transistor 2 in which the device is formed on the SOI wafer 1 may be used, or the one in which only the NPN transistor 2 having the same etching characteristics as the NPN transistor 2 is formed is used. Is also good.

Then, the current amplification factor (hereinafter referred to as hFE) of each NPN transistor 2 is measured. less than,
An example of the measuring method of this hFE is shown. The emitter is grounded, the collector potential is 3V, and the base potential is 0
It is changed in steps of 0.01V up to 1V. At this time, the collector current and base current are monitored, and the collector current is set to 1
Let hFE be the collector current / base current when changing to μA, 10 μA, 100 μA, 500 μA, 1 mA.

Also, the amount L of Si scraped in the contact hole 73 for the emitter of each NPN transistor 2
To measure. This measurement is, for example, S
It can be performed by cutting the OI wafer 1 in the thickness direction and using an electron microscope.

Then, the relationship between the amount of Si scraped L in the contact hole 73 for each emitter and hFE is obtained. Figure 3 shows hFE when the collector current is 100 μA.
And the amount L of Si scraping are shown. As shown in FIG.
The larger the scraped amount L of Si, the smaller the value of hFE.
This is because the emitter (N ⁺ ) region 45 has a higher impurity concentration in the upper layer and decreases in the lower layer. Therefore, the larger the amount L of Si scraped, the higher the impurity concentration at the interface between the emitter wiring 83 and the emitter (N ⁺ ) region 45. This is because the concentration is reduced, the electron injection efficiency is reduced, and the collector current is reduced. Note that hFE is an emitter (N ⁺ ) region 4
Although it depends on the depth of 5 itself, the depth is 0.16 μm in this embodiment.

After that, as in the above-mentioned configuration, the NPN transistor (hereinafter referred to as the inspection NPN transistor) 2 for which the relationship between the hFE and the scraped amount L of Si as shown in FIG. 3 has been obtained, and the evaluation contact. Holes are formed in the SOI wafer 1. And hF of NPN transistor 2
E is measured and, based on FIG. 3, first, the amount L of Si scraped in the contact hole 73 for the emitter is evaluated.

On the other hand, the contact hole 73 for the emitter
Has the same shape, size, and arrangement as the evaluation contact hole, the amount of Si scraped in the evaluation contact hole and the amount S of Si scraped in the emitter contact hole 73 are the same. .

Therefore, by measuring hFE, the amount of Si scraped in the evaluation contact hole can be evaluated. That is, if the relationship between hFE and the amount L of Si scraped in the contact hole 73 for the emitter is obtained in advance, the amount of Si scraped in the evaluation contact hole can be evaluated without destroying the SOI wafer 1 and the etching margin can be reduced. You can check.

Next, a manufacturing process of a semiconductor device to which the evaluation method of this embodiment is applied is shown in FIG. 4, and the manufacturing method will be described based on FIG.

[Preliminary Step] As described above, the inspection NPN is used.
The relation between the amount of Si scraped L in the contact hole 73 for the emitter of the transistor 2 and hFE is obtained.
The manufacturing method of the inspection NPN transistor is the same as the manufacturing method of the inspection NPN transistor in the following [device process].

[Device Forming Step] The SOI wafer 1 is prepared, and the trench 51 is formed in the device forming region and the region where the inspection NPN transistor 2 is formed to insulate and isolate from surrounding elements. Further, a LOCOS oxide film 52 is formed on the SOI wafer 1. Then, in the device formation region, the SOI wafer 1 is doped with impurities in order to form various desired devices. At this time, also in the region where the inspection NPN transistor 2 is formed, the regions 41 to 46 are formed and impurities are doped so as to have the above-described configuration.

Next, an oxide film 6 such as a BPSG film is formed on the SOI wafer 1 to form an evaluation contact hole in the device formation region, and a collector contact hole 71 and a base contact hole in the inspection NPN transistor 2. 72, a resist is formed on the oxide film 6 so that the portion where the contact hole 73 for the emitter is formed is opened. Then, by performing dry etching, the evaluation contact hole and the inspection NP are formed.
Each contact hole 71 to 7 in the N transistor 2
3 and 3 are formed at the same time.

After passing through various steps for forming a device, a metal such as Al (aluminum) is applied to the evaluation contact holes in the device formation region and the contact holes 71 to 73 in the inspection NPN transistor 2. Wiring (collector wiring 81, base wiring 82, emitter wiring 83) is formed by embedding. In this way, the device and the inspection NPN transistor 2 are formed.

[Device Inspection Step] When performing various inspections on the SOI wafer 1 on which a device is formed, an NP for inspection is used.
The hFE of the N-transistor 2 is measured. Then, the contact hole 7 for the emitter obtained in the preliminary step
The amount of Si scraped in the evaluation contact hole is evaluated based on the relationship between the amount of Si scraped L in FIG.

[Inspection Result Examination Step] The dry etching condition in the [device forming step] is changed based on the amount of Si scraped in the evaluation contact hole, and etching is performed under the optimum condition.

Hereinafter, the [device forming step], the [device inspecting step], and the [inspection result examining step] are repeated.

As described above, the etching margin can be confirmed by evaluating the amount of Si scraped in the evaluation contact hole only by measuring the hFE.
It is possible to easily evaluate the amount of shaving of Si in units or wafers to confirm the etching margin, and reflect it in the manufacturing process at any time to manufacture a semiconductor device under optimum conditions.

In the present embodiment, the inspection NPN transistor 2 is formed separately from the device used as the product, but the Si in the contact hole of the bipolar transistor itself formed in the device used as the product is formed.
The evaluation method of the present embodiment may be applied to evaluate the amount of abrasion. Further, instead of forming the inspection bipolar transistor, a bipolar transistor used as a product may be used to evaluate other contact holes formed in the device.

(Second Embodiment) In the first embodiment, an example in which the inspection NPN transistor 2 in which one emitter contact hole 73 is formed is used is shown, but the shape, size, and arrangement of the evaluation contact hole are shown. To form multiple contact holes for the emitter,
It is also possible to use an inspection NPN transistor having a different shape, size, arrangement, or the like.

FIG. 5 shows top views of various NPN transistors 2. It should be noted that the detailed configuration is denoted by the same reference numeral as in FIG. As shown in FIG.
The contact hole 73 for the emitter in each NPN transistor 2 is as small as 12 in (a).
In the case of (b), one large piece is formed, and in (c), two long thin pieces are formed.

In the contact etching, the etching rate changes depending on the shape, size and arrangement of the contact holes. Therefore, as in the present embodiment, by performing evaluation using the contact hole 73 for the emitter corresponding to the shape of the contact hole for evaluation and the like, it is possible to more accurately evaluate the scraped amount of Si in the contact hole for evaluation. it can.

Further, not only one type of inspection NPN transistor is used, but a plurality of types of inspection NPN transistors 2 having contact holes 73 for various emitters as shown in FIG. 5 may be simultaneously formed.

(Third Embodiment) In the first and second embodiments, the amount of Si scraped in the evaluation contact hole is evaluated at the product inspection stage of the device formed on the SOI wafer 1. However, the evaluation method using the bipolar transistor can be utilized at the development stage of the manufacturing process. Below is an example of how to utilize this.

As shown in FIG. 5, various inspection NPs having different shapes of the contact holes 73 for the emitter and the like.
Using the N-transistor 2, the relationship between the amount of shaving of Si and hFE is obtained in advance for the contact holes 73 for emitters having different shapes and dimensions. Then, these various inspection NPN transistors 2 are formed on the entire surface of the SOI wafer under a certain etching condition, or a required number of inspection NPN transistors 2 are formed. Then, in this SOI wafer, hFE is measured using the contact holes 73 for individual emitters to evaluate the amount of Si scraped in the contact holes 73 for each emitter.

As a result, under these etching conditions,
It is possible to confirm the dependence of the etching rate on the contact hole shape and the like. When the inspection NPN transistor 2 is formed on the entire surface of the SOI wafer, it is possible to confirm the deviation of the etching rate within the wafer surface. Further, when forming a plurality of wafers in the same process, it is possible to confirm the difference in etching rate between the wafers.

Therefore, the optimum etching condition can be selected by changing the etching condition variously and confirming the etching rate in the same manner.

(Other Embodiments) The first and second embodiments described above show the case where the amount L of Si scraped in the inspection NPN transistor 2 and the amount of Si scraped in the evaluation contact hole are the same. . However, even if the two Sis do not have the same amount of abrasion, hFE
It is possible to evaluate the amount of shaving of Si in the evaluation contact hole by measuring.

In general, the value of hFE is the emitter (N ⁺ )
Depends on area depth and concentration. In addition, even if a barrier metal is used for wiring or additional ion implantation is performed, hF
The value of E changes. Further, the amount of Si scraped may change depending on the concentration of the emitter (N ⁺ ) region. Further, the etching rate also depends on the shape, size, arrangement, etc. of the contact holes.

However, even if the above-mentioned conditions are changed, the relationship between the amount of Si scraped in the contact hole for the emitter of the bipolar transistor and the value of hFE becomes almost linear or 1: 1. Therefore, by obtaining the correlation between the amount of shaving of Si in the evaluation contact hole and the amount of shaving of Si in the contact hole for the emitter of the inspection bipolar transistor, it is possible to evaluate the evaluation contact hole in the manufacturing process. Can measure the amount of Si scraped in the evaluation contact hole without destroying the SOI wafer simply by measuring hFE.

Further, in each of the above embodiments, the NPN transistor 2 is used as the inspection bipolar transistor, but a PNP type bipolar transistor as shown in the top view of FIG. 6 may be used. In this PNP-type bipolar transistor, a base (N ⁺ ) region 44 is formed on the right side of the figure, and a square-shaped portion on the left side of the figure is a collector (P ⁺ ) region 46, and the center portion thereof is formed. An emitter (P ⁺ ) region 45 is formed. The other configurations are given the same reference numerals as those in FIG.

Further, an epitaxial transistor of the junction isolation type in which the periphery of the transistor is insulated can be used as the inspection bipolar transistor.

In addition, the emitter (N ⁺ ) region is not ion-implanted, but as shown in FIG.
Even when it is formed by diffusing from ySi9, it can be used in the evaluation method of each embodiment.

[Brief description of drawings]

FIG. 1 is a schematic diagram of an NPN bipolar transistor for inspection used in a first embodiment.

FIG. 2 is an enlarged view of an emitter contact in FIG.

FIG. 3 is a graph showing a relationship between hFE and a scraped amount L of Si in a contact hole for an emitter in a bipolar transistor.

FIG. 4 is a flowchart showing a manufacturing process of the first embodiment.

FIG. 5 is a top view of an NPN bipolar transistor used in the second embodiment.

FIG. 6 is a top view of a PNP type bipolar transistor.

FIG. 7 is a schematic view of an NPN bipolar transistor formed using PolySi for emitter diffusion.

[Explanation of symbols]

1 ... SOI wafer, 1a ... SOI wafer surface, 2 ... N
PN type bipolar transistor, 3 ... buried oxide film,
6 ... Insulating film, 9 ... PolySi for emitter diffusion, 41
... buried N ⁺ layer, 42 ... collector (N ^-) region, 43 ...
Base (P ^-) region, 44 ... base (P ⁺⁾ region, 45 ...
Emitter (N ⁺ ) region, 46 ... Collector (N ⁺ ) region, 5
1 ... Trench, 52 ... LOCOS oxide film, 71 ... Collector contact hole, 72 ... Base contact hole,
73 ... Contact holes for emitter, 81 ... Collector wiring, 82 ... Base wiring, 83 ... Emitter wiring.

─────────────────────────────────────────────────── ─── Continued Front Page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/66

Claims (5)

(57) [Claims] 1. A method for evaluating a semiconductor device, comprising forming an insulating film (6) on a semiconductor substrate (1) and forming a contact hole by etching the insulating film. A method for evaluating a semiconductor device, characterized in that the amount of abrasion of the semiconductor substrate due to the etching in the contact hole is evaluated by measuring the current amplification factor of 2). 2. The method for evaluating a semiconductor device according to claim 1, wherein a bipolar transistor formed for evaluation is used separately from the device formed on the semiconductor substrate. 3. The method for evaluating a semiconductor device according to claim 2, wherein the bipolar transistor having an emitter contact hole (73) having etching characteristics similar to those of the contact hole is used. 4. A plurality of the bipolar transistors are formed, and contact holes for the plurality of emitters in each of the bipolar transistors are formed by changing at least one of shape, size, and arrangement. The semiconductor device evaluation method according to claim 1. 5. To form a device on a semiconductor substrate (1), an insulating film (6) is formed on the semiconductor substrate, and the insulating film is partially etched to form a contact hole for the device. In the method of manufacturing a semiconductor device to be formed, a bipolar transistor (2) is formed on the semiconductor substrate, and a relationship between the amount of abrasion of the semiconductor substrate in the contact hole (73) for the emitter of the bipolar transistor and the current amplification factor is obtained. After performing a preliminary step, in order to form the device and the bipolar transistor on the semiconductor substrate, the insulating film formed on the semiconductor substrate is partially etched to form a contact hole for the device. A device forming step of forming a contact hole for the emitter is performed, and thereafter, the via hole is formed. The current amplification factor of the transistor is measured, and the abrasion amount of the semiconductor substrate in the contact hole for the device is evaluated based on the relationship between the abrasion amount of the semiconductor substrate and the current amplification factor obtained in the preliminary step. A method of manufacturing a semiconductor substrate, which comprises performing a device inspection step, and then performing a step of adjusting etching conditions in the device forming step based on a scraped amount of the semiconductor substrate in a contact hole for the device. .