JP3501769B2 - Differential voltage / current conversion circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential voltage / current conversion circuit used as a first-stage circuit of an amplifier, and more particularly to a first-stage circuit such as a total low NFB amplifier having a low negative feedback ratio. The present invention relates to a differential voltage / current conversion circuit which is suitable and suitable for an audio preamplifier.

[0002]

2. Description of the Related Art Conventionally, in audio amplifiers,
In the second stage, a complementary push-pull circuit is generally used as a circuit forming a voltage amplifier. The complementary push-pull circuit is advantageous in that positive and negative drive impedances are equal and even-order distortion is canceled.

As a circuit for driving the complementary push-pull circuit, that is, a first stage circuit of a conventional audio amplifier, a differential type voltage / current conversion circuit is generally used. The differential circuit is a circuit that outputs a value that is proportional to the difference between two input signals, and is less likely to be saturated, less drifted, less affected by temperature and power supply fluctuations, and capable of removing common-mode noise. There are features such as.

FIG. 8 is a circuit diagram showing an example of a conventional differential voltage / current conversion circuit. This conventional differential type voltage-current conversion circuit has two input terminals, an input A and an input B, and four output terminals of plus and minus two sets of output 1, output 2, output 3 and output 4. I have it. Then, the complementary push-pull circuit is directly driven by the output terminal.

[0005]

However, in the conventional differential circuit as shown in FIG. 8, the DC current output as the bias of the next stage is almost determined by the accuracy of the constant current circuits 71 and 72. Since the current circuits 71 and 72 are separate solid circuits, the drift amounts with respect to temperature changes are different from each other, and it is not easy to improve the accuracy of the constant current circuits 71 and 72 to make them uniform.

Regarding the differential gain, the gm of the plus side dual FET 10 and the minus side dual FET
If the gm of 20 is not aligned, it becomes difficult to highly adjust the symmetry and the similarity of the gain. That is, in the conventional differential voltage-current conversion circuit, the plus side output (output 1, output 2) and the minus side output (output 3,
It was difficult to adjust the gain deviation and the sameness with the output 4).

On the other hand, conventionally, the amplification characteristics must be comprehensively improved by a method of increasing the negative feedback ratio in the entire amplifier including the first and second stages and a method of using the DC servo. did not become. Therefore, in order to make a circuit that accurately amplifies an input signal in a high frequency range, a complicated circuit and a great deal of labor are required.

Therefore, in the conventional audio amplifier,
In order to improve the amplification characteristics comprehensively, the circuit configuration becomes complicated, and a great deal of labor is required for circuit adjustment to increase the symmetry and similarity of drift and gain with respect to temperature changes. There was a problem that it was expensive.

Here, the main objects to be solved by the present invention are as follows. That is, the first object of the present invention is to provide a differential voltage / current conversion circuit capable of directly driving a complementary push-pull circuit and capable of reducing distortion as compared with the conventional one. It is a thing.

A second object of the present invention is to provide a first-stage circuit of an amplifier, which is capable of reducing the distortion of the entire amplifier while suppressing the negative feedback ratio of the entire amplifier to a low level. It is intended to provide a current conversion circuit.

A third object of the present invention is to provide a differential voltage / current which makes it possible to reduce the time and effort of circuit adjustment for temperature drift and symmetry / similarity of gain with a relatively simple circuit configuration. It is intended to provide a conversion circuit.

Other objects of the present invention will be apparent from the specification, the drawings, and particularly the description of each claim in the claims.

[0013]

In order to solve the above-mentioned problems, the device of the present invention includes two transistors having uniform characteristics, a positive-side first transistor (QA1) and a positive-side second transistor (QA2). Plus-side dual transistor housed in one package and minus-side first transistor that is two transistors with the same characteristics
A minus side dual transistor in which a transistor (QB1) and a minus side second transistor (QB2) are accommodated in one package, and a plus side first transistor (QA1) and a minus side second transistor (QB2) Are connected in series via a first variable resistor (VR1), and the positive second transistor (QA2) and the negative first transistor (QB1) are connected to the second variable resistor (VR).
2) is connected in tandem via 2) to construct a differential circuit.

More specifically, in order to solve the problem, the present invention adopts a novel characteristic construction means ranging from a superordinate concept to a subordinate concept enumerated below.
It is made to achieve the above purpose.

That is, the first feature of the device of the present invention is that a positive side first transistor (QA1) and a positive side second transistor (QA2), which are two transistors having the same characteristics, are housed in one package. Positive side dual transistor and the negative side first transistor (QB which is two transistors with the same characteristics).
1) and the minus second transistor (QB2) to 1
A differential voltage / current conversion circuit having a minus side dual transistor housed in one package,
Substantially all of the current flowing through the plus-side first transistor (QA1) is the minus-side second transistor (QA1).
B2), the positive-side first transistor (QA1) and the negative-side second transistor (QB2) are connected in tandem, and the current flowing through the positive-side second transistor (QA2) is approximately The positive side second transistor (QA2) and the negative side first transistor (QB1) are connected in series so that the whole flows through the negative side first transistor (QB1),
The operation control terminal of the plus side first transistor (QA1) and the operation side of the minus side first transistor (QB1) are connected to form an input A terminal, and the operation control of the plus side second transistor (QA2) is performed. End and an operation control end of the minus side second transistor (QB2) are connected to form an input B terminal, and the plus side first transistor (QA2)
1) and the plus-side output terminals are connected to the current-inflow ends of the plus-side second transistors (QA2), respectively, and the minus-side first transistors (QB1) and the minus-side second transistors (QB2) are flow-in ends. To the negative side output terminal, and to connect the source terminal of the positive side first transistor (QA1) and the negative side second transistor.
A first variable resistor (VR1) is connected between the source ends of the transistors (QB2), and between the source end of the positive side second transistor (QA2) and the source end of the negative side first transistor (QB1). A second variable resistor (VR2) is connected to the first variable resistor (VR1).
Limits the amount of current flowing through the plus-side first transistor (QA1) and the minus-side second transistor (QB2), and the second variable resistor (VR2) is the plus-side second transistor (QA2). And the amount of current flowing through the minus-side first transistor (QB1) is limited, and the first variable resistor (VR1) and the second variable resistor (VR2) are connected to the plus-side first transistor (QA1).
1) and the negative side second transistor (QB2),
Configuration of a differential voltage / current conversion circuit for a first-stage circuit of an audio amplifier capable of adjusting the amount of idling current flowing between the positive-side second transistor (QA2) and the negative-side first transistor (QB1) to the same amount It is in adoption.

A second feature of the device of the present invention is that the plus-side first transistor (QA1) and the plus-side second transistor (QA1 in the first feature of the present invention device are the same.
2) are n-channel junction type FETs,
The minus side first transistor (QB1) and the minus side second transistor (QB2) are respectively p
This is in adopting the configuration of the differential voltage / current conversion circuit for the first stage circuit of the audio amplifier which is the junction type FET of the channel.

The third feature of the device of the present invention is that the drain end of the first transistor on the plus side (QA1) in the second feature of the device of the present invention has an n-channel junction type FET.
The third junction type FET (Q3) is connected in cascade, and the drain terminal of the third junction type FET (Q3) has an output 1 terminal which is one of the plus side output terminals,
One end of the first resistor (R1) is connected, a plus side power source is connected to the other end of the first resistor (R1), and the drain end of the plus side second transistor (QA2) is connected. , A fourth junction type FET (Q4), which is an n-channel junction type FET, is connected in cascade.
At the drain end of the junction type FET (Q4), the output 2 terminal forming one of the plus side output terminals and the second resistor (R2)
Is connected to one end of the second resistor (R2), the positive side power source is connected to the other end of the second resistor (R2), and the third junction type FET (Q3) and the fourth junction type FET (Q4) are connected.
A positive side bias circuit for supplying a positive constant voltage is connected to the gate end of the, and a drain side of the negative side first transistor (QB1) has a fifth junction type FET which is a p-channel junction type FET. The FETs (Q5) are cascade-connected, and the drain end of the fifth junction type FET (Q5) has three output terminals which are one of the negative output terminals and one end of the third resistor (R3). Connected,
A negative side power source is connected to the other end of the third resistor (R3), and the negative side second transistor (QB
A sixth junction FET (Q6), which is a p-channel junction FET, is cascade-connected to the drain end of 2), and the drain end of the sixth junction FET (Q6) is
The output 4 terminal forming one of the minus side output terminals is connected to one end of a fourth resistor (R4), and the minus side power source is connected to the other end of the fourth resistor (R4). Therefore, for the first stage circuit of the audio amplifier, the negative side bias circuit for supplying a constant negative voltage is connected to the gate ends of the fifth junction type FET (Q5) and the sixth junction type FET (Q6). This is in adopting the configuration of the differential voltage / current conversion circuit.

A fourth feature of the device of the present invention is that the differential voltage / current conversion circuit in the third feature of the device of the present invention functions as a circuit for driving a complementary push-pull circuit. The positive side input terminal of the complementary push-pull circuit is connected to either the output 1 terminal or the output 2 terminal, and the complementary push-pull circuit is connected to any of the output 3 terminal and the output 4 terminal. The differential voltage / current conversion circuit is used for the first-stage circuit of the audio amplifier in which the negative input terminal of is connected.

[0019]

DETAILED DESCRIPTION OF THE INVENTION Referring to the accompanying drawings,
An embodiment of the present invention will be described with respect to an apparatus example and an operation example.

According to the present invention, a differential circuit is constructed by using two dual type FETs each having two FETs built therein.
The DC output and the symmetry and similarity of the differential gain can be easily and accurately matched by adjusting the variable resistance, and is suitable for the first stage circuit of an audio amplifier.

In the present embodiment, description will be given by taking a mode in which it is applied to a circuit for driving a complementary push-pull circuit, but the present invention is not limited to these and amplification of a signal detected by a sensor is performed. It can be applied to various signal amplification circuits such as a circuit or a buffer circuit.

(Device Example) FIG. 1 is a circuit diagram showing a device example of the present invention, in which (a) is a differential voltage / current conversion circuit according to an embodiment of the present invention.
(B) is a complementary push-pull circuit driven by (a).

In the figure, 10 is a positive side dual FET, 2
0 is a minus side dual FET, VR1 is a variable resistor for adjustment (first variable resistor), VR2 is a variable resistor for adjustment (second variable resistor), and Q3 and Q4 are junction type n-channel FEs.
T, Q5 and Q6 are junction type p-channel FETs.
R1, R2, R3, R4, R5 and R6 are resistors,
D1 and D2 are Zener diodes, and C1 and C2 are capacitors.

Further, 1 is one output of the plus side output terminal, 2 is the other output of the plus side output terminal, 3 is one output of the minus side output terminal, and 4 is the other output of the minus side output terminal. . Further, A is an input of the input A terminal, and B is an input of the input B terminal.

The complementary push-pull circuit is a pnp type bipolar transistor TR1, n.
It is composed of a pn-type bipolar transistor TR2, a resistor R7 and a resistor R8.

The plus-side dual FET 10 is a plus-side dual transistor in which two FETs having the same characteristics and thermally coupled are housed in one package, and each is a junction type n-channel FET FET QA1 (plus-side first transistor). ) And FET QA2 (plus side second
Transistor).

The minus-side dual FET 20 is also a minus-side dual transistor in which two FETs having the same characteristics and thermally coupled are housed in one package, and there is a junction-type p-channel FET FET QB1 (minus-side first transistor). ) And FET QB2 (second transistor on the minus side).

Here, the positive side dual FET 10 and the negative side dual FET 20 do not have the same characteristics,
In other words, (FETQA1, FETQA2) and (FETQA1
QB1 and FET QB2) have different signal transfer characteristics.
The signal transfer characteristics refer to temperature drift such as gain, symmetry of gain, and similarity. This is due to the difficulty in manufacturing the transistor and the limitation from the viewpoint of manufacturing cost.

The source of the FET QA1 and the source of the FET QB2 are connected via the variable resistor VR1. Further, the source of the FET QA2 and the source of the FET QB1 are connected via the variable resistor VR2.

Further, the gate of the FET QA1 and the FET QB
One gate is connected to form an input A terminal. The gate of the FET QA2 and the gate of the FET QB2 are connected to form an input B terminal.

The source of the FET Q3 is connected to the drain of the FET QA1, and the FET QA1 and the FET Q3 form a cascade circuit. The drain of the FET Q3 is connected to the output 1 terminal which is one of the plus side output terminals, and the resistor R1 is further connected to the output 1 terminal. A positive power source is connected to the other end of the resistor R1.

The source of the FET Q4 is connected to the drain of the FET QA2, and the FET QA2 and the FET Q4 form a cascade circuit. The drain of the FET Q4 is connected to the output 2 terminal, which is one of the plus-side output terminals, and the resistor R2 is further connected to the end. A positive power source is connected to the other end of the resistor R2.

The source of the FET Q5 is connected to the drain of the FET QB1, and the FET QB1 and the FET Q5 form a cascade circuit. The drain of the FET Q5 is connected to the output 3 terminal, which is one of the negative output terminals, and the resistor R3 is further connected to the output. A negative power source is connected to the other end of the resistor R3.

The source of the FET Q6 is connected to the drain of the FET QB2, and the FET QB2 and the FET Q6 form a cascade circuit. The drain of the FET Q6 is connected to the output 4 terminal, which is one of the negative output terminals, and the resistor R4 is further connected to the end. A negative power source is connected to the other end of the resistor R4.

The gate of the FET Q3 and the gate of the FET Q4 are connected to each other, and a plus side bias circuit including a resistor R5, a Zener diode D1 and a capacitor C1 is further connected. FET Q5 gate and FET Q6
Of the resistor R6, the Zener diode D2, and the capacitor C2 are connected to the negative side bias circuit.

As a result, the plus side and the minus side are symmetrically connected in the circuit as a whole, and a current corresponding to the difference between the signal applied to the input A terminal and the signal applied to the input B terminal is output. , A differential voltage / current conversion circuit that can output from the output 2 terminal, the output 3 terminal, and the output 4 terminal.

Then, the variable resistor VR1 or the variable resistor VR
By adjusting 2, output 1 terminal, output 2 terminal, output 3
The DC output due to the idling current, the symmetry and the similarity of the differential gain can be matched with high accuracy and easily for the outputs of the terminal and the output 4 terminal, respectively. The DC output due to the idling current becomes the bias voltage of the next stage in the case of the direct connection amplifier.

The differential voltage / current conversion circuit shown in FIG. 1A and the complementary push-pull circuit shown in FIG. 1B are connected, for example, by connecting the output 2 terminal and the base of the bipolar transistor TR1. , The output 4 terminal and the base of the bipolar transistor TR2 are connected.

(Example of Operation) An example of operation of the above-described example of the apparatus will be described with reference to the drawings.
First, an outline of the operation will be described with reference to FIG.

Since this differential voltage / current conversion circuit uses self-bias, the idling current is set by the variable resistors VR1 and VR2. Here, the gate leakage current of the junction-type FET changes with temperature and the variation of the drain-source voltage, but the change value of the leakage current is sufficiently smaller than the value of the idling current, and FE
Since the difference between the leakage currents of T is even smaller, it is possible to eliminate such a leakage current.

From this fact, in FIG. Current I1 = Current I4 Current I2 = Current I3 Becomes

Then, the variable resistor VR1 or the variable resistor VR
By finely adjusting 2, the current I1 = current I2 = current I3 = current I4.

As a result, the bias voltage of each input of the next stage (complementary push-pull circuit) is a resistor R1 and a resistor R2 respectively connected to the output 1 terminal, the output 2 terminal, the output 3 terminal and the output 4 terminal. , The resistance values of the resistors R3 and R4 have the same value.

Further, the values of the currents flowing through the respective FETs are the same, and the FETQA1 and FETQA2, FETQB
Since 1 and the FET QB2 are thermally coupled to each other, the similarity with respect to the temperature drift of each output is also good. In this way, if the temperature drift of each output has a high similarity, the junction type FET will have a negative temperature range of 0.
Since the point / positive area is provided, this differential voltage / current conversion circuit can contribute to the temperature guarantee of the circuit at the next stage.

Furthermore, since the current I1 = current I4, the transfer characteristic of one of the differential circuits in this differential voltage / current conversion circuit is a combination of the transfer characteristics of FETQA1 and FETQB2. However, the drain cutoff current (IDSS) is limited by the lower FET, and the limiting pinch-off voltage is also limited by the lower absolute value FET.

Next, the details of the operation of the above-mentioned device example will be described. Now, assume that the input B terminal is grounded. The operation when a "plus" signal is input to the input A terminal is as follows.

First, since the gate potential of the FET QA1 becomes high and the current I1 and the current I4 increase,
The output 1 terminal is displaced to the minus side, and the output 4 terminal is displaced to the plus side. Here, since the current I1 = the current I4, the displacement at the output 1 terminal and the displacement at the output 4 terminal have the same value, and there is symmetry.

On the contrary, since the gate potentials of the FETQA2 and FETQB2 become lower than the gate potentials of the FETQA1 and FETQB1 and the currents I2 and I3 decrease, the output 2 terminal is displaced to the plus side, and the output 3 terminal is to the minus side. Is displaced to. Here, since the current I2 = current I3, the displacement at the output 2 terminal and the displacement at the output 3 terminal have the same value, and there is symmetry.

Even when a "minus" signal is input to the input A terminal, the operation is reversed for the output 1 terminal and the output 4 terminal and the output 2 terminal and the output 3 terminal, but the concept is the above-mentioned input A terminal. The same as when the "plus" signal was input to.

From these, the potentials of the output 1 terminal, the output 2 terminal, the output 3 terminal and the output 4 terminal are changed in accordance with the potential difference between the input A terminal and the input B terminal, and they operate as a differential circuit. You can see that

The plus side output (output 1 terminal, output 2 terminal) and the minus side output (output 3 terminal, output 4 terminal) in this differential voltage / current conversion circuit are the plus side dual junction type FET 10 (FETQA1, FETQA2)
And the negative side dual junction type FET20 (FETQB
1 and FET QB2) are formed by a composite circuit in which they are cascade-connected in cascade.

Therefore, when the same signal of the same phase is input to the input A terminal and the input B terminal, FETQA1 and FETQ
Since there is no potential difference between the gate potentials of A2, FETQB1 and FETQB2, output 1 terminal, output 2
The potentials of the terminals, output 3 terminals and output 4 terminals do not change.

Since the dual-junction type FET accommodates two FETs having the same characteristics in one package, the FETQA1 and the FETQA2 have very similar characteristics, and the FETQB1 and the FETQB2 also have very similar characteristics. There is. Further, since the plus side dual FET 10 and the minus side dual FET 20 are combined in a side-by-side cascade connection, the plus side output (output 1 terminal, output 2
The displacement characteristics of the negative side output (output 3 terminal, output 4 terminal) are also approximated.

Therefore, the variable resistor VR1 or the variable resistor VR
By finely adjusting either of the two, it is possible to easily adjust the current I1 = current I2 = current I3 = current I4 when the in-phase signal is input, and output 1 terminal, output 2 terminal, output It is possible to match the similarity and symmetry of the outputs of the three terminals and the output four terminals with high accuracy.

That is, the variable resistance VR1 or the variable resistance V
By finely adjusting either R2, FET QA1, F
The same circuit as the one in which the characteristics of ETQA2, FETQB1 and FETQB2 are matched with extremely high precision, and the values of the resistors R1, R2, R3 and R4 that directly affect the output voltage are matched with extremely high precision. Becomes

Therefore, when the in-phase signal enters the input terminals A and B, neither the AC component nor the DC component is output from the output terminals 1 to 4, and the operating point of the next stage circuit fluctuates. Therefore, it is possible to improve the amplification accuracy of the entire amplifier, reduce the manufacturing cost, and simplify the circuit design.

Next, the differential gain of the differential voltage / current conversion circuit will be described with reference to FIGS. Figure 2
FIG. 2 is a circuit diagram in which a differential circuit on one side is extracted from the differential voltage / current conversion circuit of FIG. The resistors VR1 ′ and VR1 ″ are obtained by virtually dividing the variable resistor VR1 in FIG. 1 into two. FIG. 3 shows an equivalent circuit which is a further simplification of the differential circuit shown in FIG. It is a circuit diagram.

In FIG. 2, in order to simplify the explanation, F
It is assumed that the transfer characteristics of ETQA1 and FETQB2 are the same. Then, it is assumed that a signal of +1 displacement is input to the input A terminal and a signal of -1 displacement is input to the input B terminal. Since this circuit is a differential circuit, a value corresponding to the displacement of (potential of input A terminal)-(potential of input B terminal) = 1-(-1) = 2 is generated at each output terminal.

At this time, the resistor R1, the FET Q3, the FET
The positive side circuit composed of QA1 and the resistor VR1 ′ and the negative side circuit composed of the resistor R4, FETQ6, FETQB2 and the resistor VR1 ″ are symmetrical, and the potentials of the output 1 terminal and the output 4 terminal are the same. The potential does not fluctuate when looking at the point C at 2. Therefore, the circuit shown in FIG.

Further, the point C can be regarded as virtual ground because the potential does not change. Therefore, since the FET QA1 in FIG. 3 is a grounded source circuit, its voltage amplification degree Av (output voltage / input voltage) is expressed by the following mathematical expression 1. Note that gm1 is the mutual conductance of the FET QA1.

[Formula 1]

The above expression 1 indicates the voltage amplification degree in the state where the displacement of “2” occurs between the input terminals as described above. That is, since the above Equation 1 indicates the voltage amplification degree for the circuit above the broken line (the circuit on the positive power supply side) in FIG. 2, the input displacement for the displacement of “2” in the entire differential circuit is the input displacement. Is also halved. In other words, point C
The gain for the input displacement from is shown. Since it is assumed that the circuit shown in FIG. 2 has an input signal of “input A−input B = 2”, the entire voltage amplification degree Av ′ of the differential circuit shown in FIG. It becomes half of the voltage amplification level Av. Therefore, the voltage amplification degree Av ′ of the entire differential circuit shown in FIG. 2 is expressed by the following mathematical expression 2.

[Formula 2]

The voltage amplification degree Av ′ shown in the above equation 2 has four outputs (output 1, output 2, output 3, and output 3 of the differential circuit shown in FIG.
Output 4) Each gain. In addition, FETQA1
When the mutual conductance gm1 of the FET is different from the mutual conductance gm2 of the FET QB2, as described above,
Since the characteristics of QA1 and FET QB2 are combined and the mutual conductance gm becomes the slope of the transfer characteristics of the junction FET, the mutual conductance gm of FET QA1 and FET QB2 is expressed by the following mathematical expression 3. [Equation 3] gm = (gm1 + gm2) / 2

Next, the result of actually making the differential voltage / current conversion circuit and the conventional differential voltage / current conversion circuit and measuring the operation thereof will be described. FIG. 4 is a circuit diagram showing a conventional differential voltage / current conversion circuit and measured values of respective parts thereof. FIG. 5 is a circuit diagram showing a differential voltage / current conversion circuit according to the present invention and measured values of respective parts thereof.

4 and 5, the model of each component of the circuit is also shown. Specifically, the resistors R1, R2,
As R3, R4, R5, and R6, those having a 1.6 [K ohm] error of 1% are used. Also, "2SK386" is used as the plus side dual FET 10, and "2SJ1" is used as the minus side dual FET 20.
09 ”is used. Further, the conventional differential voltage / current conversion circuit shown in FIG. 4 has a configuration slightly different from that of the conventional differential voltage / current conversion circuit shown in FIG.

In the circuit shown in FIG. 4 and the circuit shown in FIG. 5, parts having the same reference numerals are the same parts. This clarifies the difference in performance between this differential voltage / current conversion circuit and the conventional differential voltage / current conversion circuit.

Further, in the conventional differential voltage / current conversion circuit shown in FIG. 4, the source of the FET QA1 and the source of the FET QA2 are short-circuited, and the source of the FET QB1 and the FET QB2 are short-circuited.
Between the sources of FETQA1 and FETQA
2 source currents are all FETQB1 and FETQB2
It becomes the source current of. As a result, the idling current value for the entire conventional differential voltage / current conversion circuit shown in FIG. 4 becomes the same as the idling current value for the entire differential voltage / current conversion circuit shown in FIG.

Here, in the conventional differential voltage / current conversion circuit shown in FIG. 4 and the present differential voltage / current conversion circuit shown in FIG.
It should be noted that the gains are different. This differential voltage /
Since the gain is compressed in the current conversion circuit, each output terminal (output 1 terminal, output 2 terminal, output 3 terminal, output 4 terminal)
Errors between terminals) are also compressed. However, it is necessary to consider whether to compare the plus side output (output 1 terminal, output 2 terminal) or the minus side output (output 3 terminal, output 4 terminal).

On the other hand, the drain cutoff current (IDSS) of the FET QA1 is 10.77 mA, the drain cutoff current (IDSS) of the FET QA2 is 10.93 mA, and the FET QB.
1 drain cutoff current (IDSS) is 5.63mA, F
The drain cutoff current (IDSS) of ETQB2 is 5.44.
mA.

That is, FETQA1 and FETQB2
Comparing the pair of FETQA2 and FETQB1 with each other, the drain cutoff current (IDSS) of the pair of FETQA1 and FETQB2 is larger. Therefore, FIG.
For this differential voltage / current conversion circuit shown in
The combination of A1, FETQA2, FETQB1 and FETQB2 is the worst combination.

FIG. 6 is a diagram comparing output errors of the conventional circuit shown in FIG. 4 and the circuit according to the present invention shown in FIG. In this table, the column of “average value” shows the average value of output 1, output 2, output 3 and output 4. The column of "output error" shows a value obtained by subtracting each output value from the maximum value among the outputs 1 to 4.

The column of "correction value of output error of circuit of the present invention" shows the correction value obtained by multiplying the value of column of output error of circuit of the present invention by 3.63. Here, the multiplication by 3.63 is that the input value of the conventional circuit of FIG. 5 of the conventional circuit of FIG. .63) times.

In both the differential voltage / current conversion circuits of FIGS. 4 and 5, the error I1 + current I2 up to the error of the resistors (resistor 1, resistor 2, resistor 3, resistor 4) connected to the respective output terminals. = Current I3 + current I4 should be obtained.

However, as shown in the table of FIG. 6, the circuit according to the present invention has a smaller output error. In particular, regarding the differential gain, when the plus side gain (output 1 or output 2) and the minus side gain (output 3 or output 4) are compared, considering that the magnitude of the gain is smaller in the circuit of FIG. Even so, the circuit according to the present invention in FIG. 5 has a smaller error. That is, the circuit according to the present invention in FIG. 5 has a greatly improved symmetry with respect to the differential gain as compared with the conventional circuit in FIG.

Incidentally, as shown by the double underlined data in the table of FIG. 6, the correction value of the output error of the circuit of the present invention is
Compared with the output error of the conventional circuit, the DC component is about 1/10,
The AC component is about 1/5, and it can be seen that the symmetry of the differential gain of the circuit of the present invention is greatly improved.

As described above, the symmetry of the differential gain is improved because in the differential voltage / current conversion circuit according to the present invention shown in FIG. 5, FETQA1 and FETQB2 are connected in cascade and their characteristics are combined. Also FETQA2 and FET
This is because QB1s are connected in cascade and their characteristics are combined.

On the other hand, in the conventional differential voltage / current conversion circuit of FIG. 4, FETQA1 or FETQA2 and FE
The characteristics are not combined with TQB1 or FETQB2, and F
Differential combination of ETQA1 and FETQA2, and FETQB1
Since the FET QB2 operates only by the differential combination, the symmetry of the differential gain is inferior to that of the circuit of the present invention.

Therefore, in the next stage of the circuit according to the present invention,
When constructing a symmetrical circuit such as a complementary push-pull circuit, the error between the positive gain and the negative gain does not depend on the pairing characteristics of the junction type FET, and the positive gain and the negative gain can be matched by simple adjustment. This is a characteristic of the circuit according to the present invention.

FIG. 7 is a circuit diagram showing another conventional differential voltage / current conversion circuit and another measurement result of each part thereof. Figure 7
Also in the circuit shown in FIG. 5, the parts having the same reference numerals as those of the circuit according to the present invention shown in FIG. 5 use the same parts.

Further, the circuit shown in FIG. 7 has an overall smaller gain than the conventional circuit shown in FIG.
The output error of each output (output 1, output 2, output 3 and output 4) is substantially the same as that of the conventional circuit shown in FIG. That is, it is shown that the circuit according to the present invention in FIG. 5 has a greatly improved symmetry with respect to the differential gain, as compared with the conventional circuit shown in FIG.

Although the embodiments of the present invention have been described above, the present invention is not necessarily limited to the above-mentioned matters, and can be appropriately modified and implemented within the scope of achieving the objects of the present invention and the following effects. Is.

For example, in the above embodiment, the junction type FET is used as the amplifying element, but a MOS type FET, a bipolar transistor or a vacuum tube may be used instead of the junction type FET. In addition, the adjustment variable resistors VR1,
VR2 is FETQA1 and FETQB as shown in FIG.
It may be provided at another position, not between the two or between the FETQA2 and the FETQB1. In this case, the resistance R1,
The values of R2, R3, and R4 are also changed as appropriate.

[0082]

As described above, according to the present invention,
A plus-side dual FET composed of two FETs having the same characteristics and a minus dual-type FET consisting of two FETs having the same characteristics are combined so that the characteristics of the two dual FETs are combined. Since the differential voltage / current conversion circuit is configured by the cascade connection, the DC output due to the idling current, the symmetry and the similarity of the differential gain are controlled by simple circuit adjustment with high accuracy while suppressing the temperature drift. Can be matched to.

Further, the differential voltage / current conversion circuit according to the present invention has two input terminals, two plus side output terminals,
Since it has two minus side output terminals, it is possible to directly drive the complementary push-pull circuit, and it is possible to reduce distortion as compared with the conventional one.

Therefore, the circuit becomes the first stage circuit of the amplifier, and the distortion of the entire amplifier can be reduced while suppressing the negative feedback ratio of the entire amplifier to a low level.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, (a)
Is a differential voltage / current conversion circuit according to the present invention, and (b) is a complementary push-pull circuit driven by (a).

FIG. 2 is a circuit diagram showing a differential circuit on one side in the circuit of FIG.

FIG. 3 is a circuit diagram showing an equivalent circuit which is a further simplification of the differential circuit shown in FIG.

FIG. 4 is a circuit diagram showing a conventional differential voltage / current conversion circuit and measured values of respective parts thereof.

5 is a circuit diagram showing a differential voltage / current conversion circuit shown in FIG. 1A and measured values of respective portions thereof.

6 is a diagram comparing output errors of the conventional circuit shown in FIG. 4 and the circuit according to the present invention shown in FIG.

FIG. 7 is a circuit diagram showing another conventional differential voltage / current conversion circuit and another measurement result of each part thereof.

FIG. 8 is a circuit diagram showing an example of a conventional differential voltage / current conversion circuit.

[Explanation of symbols]

1, 2, 3, 4 ... Output 10 ... Plus side dual FET (plus side dual transistor) 20 ... Minus side dual FET (minus side dual transistor) 71, 72 ... Constant current circuit A, B ... Input C1, C2 ... Capacitor D1, D2 ... Zener diodes I1, I2, I3, I4 ... Current Q3, Q4 ... N-channel FET Q5, Q6 ... P-channel FET QA1 ... N-channel FET (plus side first transistor) QA2 ... N-channel FET (plus side first) 2 transistors) QB1 ... p-channel FET (minus-side first transistor) QB2 ... p-channel FET (minus-side second transistor) R1, R2, R3, R4, R5, R6, R7, R8 ... Resistance C ... Points TR1, TR2 ... Bipolar transistors VR1, VR2, VR3 ... Variable resistance

Claims (4)

(57) [Claims] 1. A plus-side dual transistor in which a plus-side first transistor (QA1) and a plus-side second transistor (QA2), which are two transistors having uniform characteristics, are accommodated in one package, A differential voltage / current conversion circuit having a minus-side dual transistor in which a minus-side first transistor (QB1) and a minus-side second transistor (QB2) which are two arranged transistors are accommodated in one package. And substantially all of the current flowing through the plus-side first transistor (QA1) is the minus-side second transistor (QA1).
B2), the positive-side first transistor (QA1) and the negative-side second transistor (QB2) are connected in series so that the current flowing through the positive-side second transistor (QA2) is substantially the same. All are the negative side first transistor (Q
The positive side second transistor (QA2) and the negative side first transistor (QB1) are connected in series so as to flow through B1), and the operation control end of the positive side first transistor (QA1) and the negative side are connected. The operation control terminal of the first side transistor (QB1) is connected to form the input A terminal, and the operation control terminal of the second transistor (QA2) on the plus side and the operation control terminal of the second transistor (QB2) on the negative side are connected. Connected to form an input B terminal, positive side output terminals are respectively connected to the current inflow end sides of the positive side first transistor (QA1) and the positive side second transistor (QA2), and the negative side first transistor (QB1) and the negative side output terminal of the negative side second transistor (QB2) are respectively connected to the negative side output terminals, The first variable resistor (VR1) is connected between the source end of the first side transistor (QA1) and the source end of the second transistor (QB2) on the negative side, and the source of the second transistor (QA2) on the positive side is connected. A second variable resistor (VR2) is connected between an end and a source end of the negative first transistor (QB1), and the first variable resistor (VR1) is connected to the positive first transistor (QA1) and The amount of current flowing through the minus side second transistor (QB2) is limited, and the second variable resistor (VR2) passes through the plus side second transistor (QA2) and the minus side first transistor (QB1). The amount of current flowing through the first variable resistor (VR1) and the second variable resistor (VR).
2) is between the plus side first transistor (QA1) and the minus side second transistor (QB2), and the plus side second transistor.
A differential voltage / current conversion circuit for a first-stage circuit of an audio amplifier, wherein an idling current amount flowing respectively between a transistor (QA2) and the minus-side first transistor (QB1) can be adjusted to the same amount. 2. The positive side first transistor (QA1)
And the plus-side second transistor (QA2) are n-channel junction type FETs, and the minus-side first transistor (QB1) and the minus-side second transistor (QB2) are p-channel junction transistors, respectively. A differential voltage / current conversion circuit for a first stage circuit of an audio amplifier according to claim 1, wherein the differential voltage / current conversion circuit is a FET. 3. The first positive side transistor (QA1)
At the drain end of the third junction type FET (Q
3) are cascade-connected, and a drain terminal of the third junction FET (Q3) has an output 1 terminal that forms one of the plus-side output terminals and a first output terminal
One end of the resistor (R1) is connected, the other end of the first resistor (R1) is connected to the plus side power source, and the drain end of the plus side second transistor (QA2) is A fourth junction type FET (Q
4) are cascade-connected, and at the drain end of the fourth junction FET (Q4), an output 2 terminal that forms one of the plus side output terminals and a second
One end of the resistor (R2) is connected, the other end of the second resistor (R2) is connected to the plus side power source, the third junction type FET (Q3) and the fourth junction type FE
A positive side bias circuit for supplying a positive constant voltage is connected to the gate end of T (Q4), and a p-channel junction type FET is connected to the drain end of the negative side first transistor (QB1). Fifth junction type FET (Q
5) are cascade-connected, and the drain terminal of the fifth junction FET (Q5) is connected to the output 3 terminal which is one of the negative output terminals and one end of the third resistor (R3). The minus side power source is connected to the other end of the third resistor (R3), and the drain end of the minus side second transistor (QB2) is a p-channel junction type FET. Junction type FET (Q
6) are cascade-connected, and the drain terminal of the sixth junction FET (Q6) is connected to the output 4 terminal which is one of the negative output terminals and one end of the fourth resistor (R4). The negative side power source is connected to the other end of the fourth resistor (R4), and the fifth junction type FET (Q5) and the sixth junction type FE are connected.
The differential voltage / current for the initial stage circuit of the audio amplifier according to claim 2, wherein a negative side bias circuit for supplying a constant negative voltage is connected to the gate terminal of T (Q6). Conversion circuit. 4. The differential voltage / current conversion circuit functions as a circuit for driving a complementary push-pull circuit, and any one of the output 1 terminal and the output 2 terminal is a complementary push circuit. The plus side input end of the pull circuit is connected, and the minus side input end of the complementary push-pull circuit is connected to either of the output 3 terminal and the output 4 terminal. 3. A differential voltage / current conversion circuit for the first-stage circuit of the audio amplifier according to 3.