JP3506009B2 - Silicon wafer etching method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for etching a silicon wafer, and more particularly, it is suitable for use as an etching method for forming a thin portion in a semiconductor pressure sensor or a semiconductor acceleration sensor, for example.

[0002]

2. Description of the Related Art As a method of forming a thin silicon diaphragm on a partial area of a silicon substrate, electrochemical etching in a wafer state is used (Japanese Patent Laid-Open No. 7-24).
9608 publication). This is a method in which a voltage is applied to an N layer in a silicon wafer having a PN junction in an alkaline etching solution and anodic oxidation is performed near the PN junction surface to stop the etching. More specifically, regarding this electrochemical etching, there is an effect of making the thickness of each diaphragm (thin portion) uniform within the wafer surface during anodization, that is, an effect of correcting the diaphragm thickness.

On the other hand, in electrochemical etching, when etching is performed at a high temperature in order to shorten the processing time,
There is a problem in that the effect of correcting the diaphragm thickness is not sufficiently obtained, and the diaphragm thickness varies within the wafer surface.

[0004]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for etching a silicon wafer which can achieve both shortening of the etching time and uniformization of a sufficient thin portion thickness within the wafer surface. Especially.

[0005]

According to a first aspect of the present invention, there is provided a method for etching a silicon wafer, wherein at least a temperature of the etching solution is lowered and a concentration of the etching solution is reduced before all the etched surfaces in the wafer surface reach the PN junction. It is characterized by doing either.

Therefore, the etching rate can be increased and the etching processing time can be shortened until at least one of lowering the temperature and lowering the concentration of the etching solution. Then, at least one of lowering the temperature and lowering the concentration of the etching solution can make uniform the thickness of the thin portion within the wafer surface.

Here, a more practical case where a KOH aqueous solution is used as an etching solution and the conditions for the desired processing are performed will be described below with reference to FIG. 12 as an example.

As shown in FIG. 12, when the liquid concentration is plotted on the horizontal axis and the liquid temperature is plotted on the vertical axis, it is below the line L1 at which the liquid starts boiling and the liquid reaches the saturated concentration. Reaching line L
On the left side of 2, the P layer etch rate is 3 μm / m
The P layer etch rate is 3 μm / m above the in line L3.
The first liquid temperature / concentration range Z1 is on the right side of the boundary line L4 in which the area is equal to or larger than “in” and the diaphragm surface / shape defect occurs due to the micropyramid. This is the first
The use range Z1 in the process of is. In FIG. 12, the PN interface layer / P is located below the line L1 at which boiling starts and on the left side of the line L2 at which the saturation concentration is reached.
PN is to the left of line L5 with a layer etch rate ratio of 0.01
The interface layer / P layer etch rate ratio is 0.01 or less in the second liquid temperature / concentration range Z2. This is set as a use range Z2 in the second step. Here, the etch rate of the PN interface layer refers to the etch rate when silicon is anodized near the PN interface.

Then, from the proper etching region Z1 capable of forming a proper surface / shape in a short time, to the proper anodizing region Z2 capable of effectively correcting the variation in the thickness of the thin portion within the wafer surface. Shift to. That is,
The proper etching region Z1 that can etch the P layer at an etching rate of 3 μm / min or more without roughening the etching surface is switched to the proper anodizing region Z2 that can reduce the variation of the etching amount to 0.01 or less. In this way, the first step (etching step) for forming an appropriate surface / shape in the electrochemical etching step in a short time
And the second step (anodizing step) for effectively correcting the thickness variation of the thin portion, and the first step is performed at high temperature.
The processing conditions are set to a high concentration, the second step is set to a lower temperature or a lower concentration than the first step, and switching is performed before all the etched surfaces in the wafer surface reach the PN junction.

According to a second aspect of the present invention, in the method for etching a silicon wafer, the temperature of the etching solution is lowered and the concentration thereof is lowered before the etching surface where the etching progresses fastest in the wafer surface reaches the PN junction. The feature is that at least one of the conversion is performed.

Therefore, the etching rate can be increased and the etching processing time can be shortened until at least one of lowering the temperature and lowering the concentration of the etching solution. Then, at least one of lowering the temperature and lowering the concentration of the etching solution can make uniform the thickness of the thin portion within the wafer surface.

Here, as described in claim 3, the treatment before and / or after lowering the temperature and / or lowering the concentration of the etching solution is continuously performed in the same bath, or As described in Item 4, by injecting a liquid having a temperature and / or a concentration lower than that of the etching liquid in the processing bath into the processing bath, and diluting and / or cooling the etching liquid, At least one of lowering the temperature and lowering the concentration of the etching solution is performed, or when the current flowing in the silicon wafer is detected and the current shows a desired behavior as described in claim 5, etching is performed. At least one of lowering the temperature and lowering the concentration of the liquid should be performed. By doing so, it is preferable for practical use.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. This embodiment is embodied in a semiconductor pressure sensor using a piezoresistive layer.

FIG. 1 shows a cross section of a semiconductor pressure sensor.
An N-type epitaxial layer 2 having a thickness of 6 μm is formed on one surface of a P-type silicon substrate 1 having a crystal orientation (100), and a semiconductor substrate 3 is constituted by this laminated body. The P-type silicon substrate 1 is formed with a concave portion 4 which is open on one surface, and the bottom surface 4 a of the concave portion 4 constitutes a thin portion 5. This thin portion 5 serves as a sensor diaphragm. Also,
The recess 4 is formed by electrochemical etching.

In FIG. 1, a P ⁺ -type impurity diffusion layer 6 is formed in the N-type epitaxial layer 2, and this P ⁺ -type impurity diffusion layer 6 serves as a piezoresistor for sensing strain. A silicon oxide film 7 is formed on the surface of the N-type epitaxial layer 2. The P ⁺ -type impurity diffusion layer 6 is electrically drawn out to the surface side of the silicon oxide film 7 by the aluminum wiring 8.

FIG. 2 is a schematic view of an etching apparatus for forming the thin portion (diaphragm) 5 on the semiconductor substrate 3 in a wafer state before dicing. The etching apparatus includes a base 14, a cylindrical frame body 15, and a lid body 16. These members are made of tetrafluoroethylene resin or the like, and have high insulation properties and excellent heat insulation properties and corrosion resistance. . The lower surface opening end of the frame 15 is arranged on the base 14 in a state where it can be held in a liquid-tight state by the O-ring 17, and the upper opening end of the frame body 15 is covered by the lid 16 by the O-ring 18. It is installed in a dense state. This base 14, frame 15 and lid 1
A processing tank (closed vessel) 55 is constituted by 6 and KO as an alkali anisotropic etching liquid is contained in the processing tank 55.
The H aqueous solution 19 can be arranged.

Here, in the present embodiment, the KOH aqueous solution 19 contains the high temperature and high concentration liquid for the first step and the second solution.
Two types are used, a low temperature and low concentration liquid for the process.
Specifically, as a high temperature and high concentration KOH aqueous solution,
A KOH aqueous solution of 25 to 40 wt% at a temperature of 0 to 120 ° C., and a low temperature / low concentration liquid at 80 to 90 ° C.
A 20 wt% KOH aqueous solution is used.

The upper surface 14a of the base 14 is a smooth wafer mounting surface, and the semiconductor substrate 3 in a wafer state to be etched is placed on the upper surface 14a. At this time, the P-type silicon substrate 1 of the silicon wafer (semiconductor substrate 3) faces upward, and the surface of the P-type silicon substrate 1 is in contact with the KOH aqueous solution 19. In addition, the power supply electrode 9 (see FIG. 1) of the silicon wafer (semiconductor substrate 3) is in close contact with the upper surface 14 a of the base 14.

The upper surface (wafer mounting surface) 1 of the base 14
A negative pressure chamber forming recess 20 is annularly provided on the outer peripheral portion of 4a. A ring-shaped packing 21 is provided on the lower surface of the frame body 15.
The packing 21 is fixed to the negative pressure chamber forming recess 2 with the outer peripheral edge of the silicon wafer (semiconductor substrate 3) sandwiched therebetween.
It blocks the 0 opening. Then, the inside of the negative pressure chamber forming recess 20 is evacuated by a vacuum pump (not shown) or the like, whereby the packing 21 is sucked and the silicon wafer 3 is immovably fixed. in this way,
Masking for the etching surface at the outer peripheral edge of the silicon wafer 3 is performed by the packing 21. Moreover, the base 14 and the frame 15 are suction-fixed by this vacuuming.

As shown in FIG. 3, the base 14 is formed with a passage 23 that connects the upper surface (wafer mounting surface) 14 a and the negative pressure chamber forming recess 20. The passage 23 has an anode electrode 24. Are arranged. One end of the anode electrode 24 is connected to the pin 26 by the nut 25 in the negative pressure chamber forming recess 20. The pin 26 is exposed to the outside of the base 14 by the communication hole 27 and is kept airtight by the O-ring 28. The tip of the anode electrode 24 has an upper surface 14a of the base 14 in the absence of the silicon wafer (semiconductor substrate 3).
When the silicon wafer 3 is projected on the upper surface 14a of the base 14 by a distance L from the anode electrode 24, the anode electrode 24 bends as shown by a chain double-dashed line in FIG. In this way, the anode electrode 24 contacts the power supply electrode 9 (see FIG. 1) of the silicon wafer 3 with a constant contact pressure, and the voltage can be applied to the silicon wafer (semiconductor substrate 3).

In FIG. 2, the lid 16 is provided with a supply passage 29 reaching the inside of the frame 15. In this supply passage 29, KOH aqueous solution is passed through the valve 30, pure water is passed through the valve 31, and nitrogen gas is passed through the valve 32. However, they can be supplied separately. A discharge passage 33 that communicates the inside and the outside is provided in the lid body 16.
One end of 3 is opened at the bottom of the frame 15 by a pipe 34. Then, the KOH aqueous solution 19 and pure water in the frame 15 can be discharged through the pipe 34 and the discharge passage 33.

Further, a rod-shaped cathode electrode 35 is arranged so as to penetrate through the lid body 16 and is kept airtight by an O-ring 36. This cathode electrode 35 is the K in the processing tank 55.
It extends to a predetermined depth with respect to the OH aqueous solution 19. A DC power supply 37, an ammeter 38, and a contact 39 are connected in series between the cathode electrode 35 and the anode electrode 24. Then, by closing the contact 39, a voltage is applied to the cathode electrode 35 and the anode electrode 24 by the DC power supply 37. At this time, the cathode electrode 35 is removed from the silicon wafer (semiconductor substrate 3) by the ammeter 38.
The current flowing to is detected.

Further, the heater 40 is arranged in a state of penetrating the lid body 16 and is kept airtight by an O-ring 41. By energizing this heater 40, the heater 4
0 can generate heat to raise the temperature of the KOH aqueous solution 19. Further, the temperature sensor 42 is arranged so as to penetrate the lid 16, and the O-ring 43 keeps airtightness. The temperature of the KOH aqueous solution 19 is detected by the temperature sensor 42. The temperature controller 44 is the temperature sensor 4
Heater 4 while monitoring the temperature of KOH aqueous solution 19
0 is energized to maintain the temperature of the KOH aqueous solution 19 at a desired value.

A stirring blade 45 is arranged in the processing tank 55,
The motor 46 attached to the lid 16 rotates the stirring blade 45 through the coupling 47 to rotate the KOH aqueous solution 19
Stir. The stirring blade 45 is kept airtight by an O-ring 48.

Further, as shown in FIG. 4, a tank 62 for storing the treatment liquid 60 for the first step, a tank 63 for storing the treatment liquid 61 for dilution for the second step, and a preliminary tank. 64 is provided, and the processing liquid 60 in the tank 62 and the processing liquid 61 in the tank 63 are pumped up by a fixed amount by the pumps 65 and 66 and sent to the preliminary tank 64. Spare tank 6
4 is equipped with a stirrer 67 and a heater 68 so that the liquid pumped into the preliminary tank 64 can be adjusted to a desired temperature. In this spare tank 64, the high temperature for the first step
High concentration liquid (100-120 ° C, 25-40wt% KO
H aqueous solution) is prepared and placed in the processing bath 55 by opening the valve 30 of FIG. Further, the liquid for the second step is put into the processing bath 55 by opening the valve 30, and the low temperature / low concentration liquid for the second step (80 to 90 ° C.,
10 to 20 wt% KOH aqueous solution). In other words, when the valve 30 is opened and put into the processing bath 55 at the time when the first step is completed, the liquid amount, concentration, and temperature are adjusted so that the mixed liquid is in the second etching liquid condition in a short time. It

The main controller 49 of FIG. 2 detects the start of etching by the signal from the start switch 50, and also detects the energizing current by the signal from the ammeter 38. Further, the main controller 49 includes a contact 39, a motor 46, a temperature controller 44, valves 30, 31,
32 is driven and controlled. The main controller 49 is mainly composed of a microcomputer.

Next, a method of manufacturing this semiconductor pressure sensor will be described. First, a P-type silicon substrate (silicon wafer) 1 having a (100) plane in FIG. 1 is prepared. An N-type epitaxial layer 2 is grown on one surface of the P-type silicon substrate (silicon wafer) 1, and the N-type epitaxial layer 2 is further grown.
A power supply electrode (metal film) 9 is formed on the outer peripheral portion of the surface of the.
Further, the mask material 10 (see FIG. 1) is arranged in a predetermined region on the surface of the P-type silicon substrate 1. A silicon nitride film (SiN) is used as the mask material 10. In this way, a silicon wafer (semiconductor substrate 3) before etching is prepared. A large number of recesses 4 are formed in each chip formation region in the silicon wafer 3 by the subsequent processing.

Then, the silicon wafer 3 is set in the etching apparatus shown in FIG. At this time, the back surface of the wafer (the surface to be etched) faces upward, and the silicon wafer 3 is placed on the base 1.
4, and the inside of the negative pressure chamber forming recess 20 is evacuated to fix the silicon wafer 3 with packing 21.

The main controller 49 is shown in FIG.
The process of is executed. This processing will be described based on the time chart of FIG. The vertical axis in FIG. 6 represents the current value. Here, the curve shown by the solid line in FIG. 6 shows the case where the first process condition is switched to the second process condition. In FIG. 6, the case where etching is performed under the first process conditions is also indicated by a broken line.

First, when the main controller 49 receives an etching start signal from the start switch 50, the main controller 49 of FIG.
The process of is started. The main controller 49 opens the valve 30 and puts a predetermined amount of the high temperature / high concentration KOH aqueous solution 19 (100 to 120 ° C., 25 to 40 wt% KOH aqueous solution) for the first step. Furthermore, the stirring blade 45 allows KO
While the H aqueous solution 19 is being stirred, the temperature controller 44 energizes the heater 40 to maintain the temperature of the KOH aqueous solution 19 at a predetermined value. From this state, the main controller 49 closes the power contact 39 in step 101 of FIG.
A voltage from the DC power supply 37 is applied to the N-type epitaxial layer 2 of the wafer 3 (timing t0 in FIG. 6).

[0031] Then, the main controller 49 (70 minutes specifically) a predetermined time in step 102 elapses, determines whether it is t ₁ in FIG. When a predetermined time (70 minutes) elapses and t ₁ is reached, the main controller 49 proceeds to step 103 and reads the current value (current flowing during etching) by the ammeter 38 every predetermined time, and at step 104. It is determined whether or not the difference ΔI (= I _i −I _i−1 ) between the current value I _i and the previous value I _i−1 every 2 seconds is larger than the predetermined value ΔI ′ for three consecutive times. When the difference ΔI between the current values every 2 seconds is larger than the predetermined value ΔI ′ three times consecutively (timing of t _ch in FIG. 6), the main controller 49 moves to step 105 and reserves the tank in FIG. The liquid (the liquid for the second step) whose liquid amount, concentration and temperature are adjusted in 64 is transferred to the processing bath 55 of FIG. 2 to dilute and cool the etching liquid to lower the temperature and lower the concentration of the etching liquid. To convert. As a result, the etching solution becomes 80 to 9
It becomes an aqueous solution of 0 to 10 wt% KOH at 0 ° C.

More specifically, during the first step, the diluent 61 for the second step shown in FIG. 4 is pumped from the tank 63 to the preliminary tank 64 by the metering pump 66 to adjust the temperature and concentration. When the condition switching signal is output from the main controller 49, the amount of the liquid in the processing bath 55 is fixed (about 6% of the processing liquid).
(Sorting) About suction and discharge, immediately open the valve 30 of the preliminary tank 64, and transfer the sucked portion to the processing tank 55. For example, when the first process condition is 110 ° C. and 38 wt%, and the second process condition is 80 ° C. and 15 wt%, the diluent for the second process is pure water and the liquid temperature is set to 50 ° C. Keep it. Then, when the liquid is mixed by the stirring blade 45 in the processing tank 55,
The liquid temperature reaches 80 ° C. in about 2 to 3 minutes. Regarding the etching condition in the processing bath 55 in more detail, the voltage is applied to the wafer 3 during this time, the etching progresses, and when the liquid temperature stabilizes and the liquid temperature stabilizes for a few minutes, the current sharply increases and eventually reaches the peak.

The main controller 49 reads the current value from the ammeter 38 in step 106 of FIG. 5, and determines in step 107 whether or not the current peak is reached. That is,
It is determined whether or not the energizing current value reaches a peak (timing of t _{3 in} FIG. 6). More specifically, this current value I
Difference between _i and the previous current value I _i-1 ΔI _i (= I _i −I _i-1 )
Is calculated to determine whether or not the rate of change ΔI _i of the energizing current is inverted from positive to negative.

When the current value reaches a peak (t _{3 in} FIG. 6)
Timing), the main controller 49 waits for a predetermined time T1 (for example, 10 minutes) in step 108 (timing t ₄ in FIG. 6), and then in step 109, injects pure water by valve operation to dilute the processing liquid.・ Cool and 3
After a lapse of minutes, the valve 31 is closed, the contact 39 is opened, and the etching is completed. In this way, the recess 4 shown in FIG.
A silicon wafer 3 having a large number of is obtained.

Further, in FIG. 6, the timing of t ₂ is the diaphragm (etching process) in which the fastest etching progresses in each diaphragm in the wafer when etching is performed under the first process conditions (broken line). Surface) reaches the PN interface layer, and t ₃ , t
_At the timing of ₃ ', all the etched surfaces in the wafer surface reach the PN interface layer. The initial current value I ₀ at the start of the etching is 2.0 mA, the current value I ₂ at the timing of t ₂ is in the case (broken line) which were kept etching of the first process condition, I ₀ It is +10 mA.

In the silicon wafer thus obtained, the thickness of each diaphragm in the wafer surface has a desired value. That is, as shown in FIG. 8, t _{1 in} FIG.
In comparison with 70 minutes after the start of etching in FIG. 6, the thickness of a part of the diaphragm in the wafer surface starts to be made uniform from the time t ₂ in FIG. 6, and the current peak point at t ₃ in FIG. Then, the uniformization of the thicknesses of all the diaphragms within the wafer surface is started, and finally the thicknesses of all the diaphragms within the wafer surface are uniformized. In this way
It is possible to form a diaphragm having an appropriate etching surface / shape and having a small thickness variation in the wafer surface in a relatively short time. Details of FIG. 8 will be described later.

Next, a method of setting a switching point of etching conditions will be described with reference to FIG. FIG. 7 shows a case where the etching is performed under the first process conditions shown by the broken line in FIG. 6, and more specifically, the anode is formed only under the first process conditions (for example, 110 ° C., 38 wt%). Oxidation (applied voltage 1.5 V, time 6 minutes) was performed.

At the point p1 (time t ₁ , current value I ₁ ), the current starts to slightly increase, and it is 5 from the current peak point p3.
It is about a minute before. In addition, point p2 (time t ₂ , current value I
₂ ) The current is starting to surge. The period between points p1 and p2 is the time for switching the etching conditions. This point p
A method of setting 1 and the point p2 will be described. The current value at the start of etching is I ₀ .

First, the minimum time t to reach the current peak point p3 (time t ₃ ', current value I ₃ ) which is a standard for detecting the end point of normal etching when electrochemical etching is repeatedly performed only under the first process condition. _Ask for _{3 min} . Then, the time t ₁ at which the current gradient starts to be detected is set by the following equation. However, the unit of t _3min and t ₁ is
It is min.

T ₁ = t _3min −t _3min / 15 Next, the current value I ₂ at the point p2 is calculated by the following equation using the current value I ₀ at the start of etching and the current value I ₃ at t _3min . Set. However, the unit of I ₃ , I ₂ and I ₀ is mA.
(Milliamperes).

I ₂ = I ₀ + (I ₃ −I ₀ ) /8.5 Furthermore, the current gradients ΔI ₁ and ΔI ₂ at the points p1 and p2 during actual etching are measured, and the conditions are switched according to the following equation. To set the trigger current gradient ΔI ^′ for The unit of ΔI is mA (milliampere) / 2 sec.
(Seconds).

ΔI ^' = ΔI ₁ + (ΔI ₂ −ΔI ₁ ) / 6 In FIG. 7, the ΔI ₁ value at p1 is 0.015 mA / 2.
sec, and the ΔI ₂ value at p2 is 0.32 mA / 2s
ec and the trigger current gradient ΔI ^′ is 0.066 mA /
2 seconds.

These values are stored in the main controller 49 of FIG.
To enter. Then, as described above, in step 103 of FIG. 5, when the time t ₁ is reached, the main controller 49 calculates the difference in current value every 2 seconds, and in step 104 of FIG. 5, this difference is repeated three times. Then, when ΔI ^' or more, the processing condition is changed to step 105.

Next, the experiments conducted by the present inventors will be described. When forming a diaphragm by electrochemical etching, it is necessary to form an appropriate surface / shape in a short time and to effectively correct variations in diaphragm thickness. The effect of correcting the diaphragm thickness is determined by the etching rate ratio of the PN interface layer and the P layer, and the smaller the etching rate ratio, the greater the effect. For example, when etching silicon having a crystal orientation (100) with KOH, as shown in FIG. 11, processing conditions of lower temperature and lower concentration (for example, 80 to 90 ° C., 10 to 20 wt%) are desirable. That is, in FIG. 11, the horizontal axis represents the liquid concentration and the vertical axis represents the ratio of the etching rates of the PN interface layer and the P layer, and liquids having liquid temperatures of 80, 90, 100, 110, and 120 ° C. were used. It is a plot of the ratio of the etching rate to the liquid concentration in the case. From FIG. 11, the smaller the concentration of the liquid and the lower the temperature of the liquid, the smaller the ratio of the etching rates of the PN interface layer and the P layer, and the better the uniformity of the diaphragm thickness within the wafer surface. I understand.

However, when etching is performed under conditions of low temperature and low concentration, the surface is roughened due to generation of micropyramids on the etched surface, and an appropriate diaphragm cannot be formed. Therefore, in order to form a proper etching surface in a relatively short time,
High-concentration processing conditions (for example, 100 to 120 ° C., 25 to 4
0 wt%) must be applied.

Therefore, as described with reference to FIG.
The electrochemical etching process is divided into a first process (etching process) for forming an appropriate surface / shape in a short time and a second process (anodizing process) for effectively correcting variations in diaphragm thickness. The first step is set to a high temperature / high concentration processing condition, the second step is set to a lower temperature or a lower concentration than the first step, and these are continuously performed in a series of devices. Here, regarding the timing of switching the conditions, if the etching processed surface is switched 30 μm or more before the PN interface layer, there is a possibility that surface roughness and shape defects due to pyramids that occur at low temperatures and low concentrations may occur. Switching after the surface reaches the PN interface layer diminishes the effect of diaphragm thickness correction. In consideration of these points, the timing of switching the etching solution to a low temperature and a low concentration is optimized by utilizing the current monitor used for detecting the etching end point.

As previously shown, FIG. 8 shows the result of investigation of the change in diaphragm thickness corresponding to the change over time in current in FIG. Here, the etching solution (KOH) has a concentration of 38
wt%, liquid temperature is 110 ° C.

As a result, 5 from the current peak point p3 in FIG.
At a point p1 (time t ₁ , current value I ₁ ) at which the current slightly before the minute increases slightly, not all the diaphragms in the wafer surface reach the PN interface layer, and 1
It was thicker than 0 μm. Also, the point p2 at which the current begins to increase sharply
At (time t ₂ and current value I ₂ ), the diaphragm with the fastest etching progressed within the wafer surface reached the PN interface layer. Then, begins diaphragm thickness correction from the point p2 in the wafer surface, the current peak point is a measure of end-point detection of the normal etching p3 (time t ₃ ', the current value I
_{In 3} ), it was found that most of the diaphragm reached the PN interface layer and the thickness was being corrected.

From this, it is effective to switch the processing conditions between the points p1 and p2. In this case, at low temperature
Even if the maximum etching amount at low concentration is 30μ
Since it can be set to m or less and the etching amount is small, surface roughness and defective shape due to micropyramids can be avoided. Also,
Even the diaphragm with the fastest etching has not yet reached the PN interface layer, and the thickness can be effectively corrected at low temperature and low concentration. That is, as shown in FIG. 5, a predetermined time (for example, 70 minutes) has elapsed from the start of etching, and the current difference between two points (every 2 seconds) has reached a predetermined value (for example, 0.05 m) continuously three times.
A) When the above is reached, the condition is switched.

An experiment was carried out to confirm the effect, which will be described below. FIG. 9 shows the measurement results of the thickness of the diaphragm within the wafer when the liquid temperature is 110 ° C., the liquid concentration is 38 wt%, the anodizing time is 6 minutes, and the applied voltage is 3 volts. In FIG. 10, the first process condition is 11
0 ° C., 38 wt%, second process condition is 80 ° C., 15 wt
%, And the distribution of the diaphragm thickness when the anodic oxidation time is 10 minutes and the applied voltage is 1.5 V for etching.

In the comparative example shown in FIG. 9, the diaphragm thickness on the outer peripheral portion of the wafer is about 0.4 μm thicker than the central portion. In the present embodiment of FIG. 10, the difference between the diaphragm thickness at the outer peripheral portion of the wafer and that at the central portion is 0.2 μm or less. This is the PN interface layer and P
This is because the etching rate ratio of the layer was 0.03 under the condition of FIG. 9, but was 0.01 or less in the present embodiment (see FIG. 11). Further, in the present embodiment of FIG. 10, the etching surface was not roughened, and a good diaphragm could be formed. It should be noted that the etching time becomes longer due to the lowering of the anodic oxidation, but this is also 10%.
It's enough. In this way, a sufficient diaphragm thickness correction effect can be obtained without significantly increasing the total etching time as compared with the conventional case.

As described above, the present embodiment has the following features. (A) Since the etching solution is lowered in temperature and the concentration thereof before the etching surface where the etching progresses fastest in the wafer surface reaches the PN junction, Until the temperature is lowered and the concentration is lowered, the etching rate is increased to shorten the etching process time.By lowering the temperature and concentration of the etching solution, the thin wall thickness in the wafer surface can be reduced. Can be achieved, and both the shortening of the etching time and the uniformization of the sufficient thickness of the thin portion in the wafer surface can be achieved at the same time.

As a more specific etching method, when the current flowing in the silicon wafer is detected and the current exhibits a desired behavior, that is, when the slope increase point of the current value flowing in the wafer is detected, the same bath is used. In 55, the processing before and after lowering the temperature and the concentration of the etching solution is continuously performed, that is, a solution having a temperature and a concentration lower than that of the etching solution in the processing tank 55 is injected into the processing tank 55. Since the etching liquid is diluted and cooled to lower the temperature and the concentration of the etching liquid, it is more preferable.

In the present embodiment, in order to further enhance the effect of correcting the diaphragm thickness, the temperature is lowered and the concentration is decreased in the second step. However, when the correction degree may be slightly small, Either the low temperature or the low concentration may be used. That is, in FIG. 12, only the lowering of temperature may be performed as indicated by shift (I), or only the lowering of concentration may be performed as indicated by shift (II). However, for example, the variation in the final thickness of the diaphragm within the wafer surface is ± 0.
When the thickness is 3 μm or less (the thickness variation of the N layer is ± 0.1
5 μm), and considering the diaphragm thickness variation before anodic oxidation up to 20 μm (usually about 10 μm),
As in the present embodiment, the first process condition (liquid temperature 110 ° C.,
The second process condition is a liquid temperature of 90 wt%).
It is necessary to keep the liquid temperature below 20 ° C. and the liquid concentration below 20 wt%.

In the above description, the case where the diaphragm of the semiconductor pressure sensor is formed has been described.
It can be used, for example, when forming a thin portion (beam portion) of a semiconductor acceleration sensor.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor pressure sensor according to an embodiment.

FIG. 2 is a schematic view of an etching apparatus.

FIG. 3 is a partially enlarged view of an etching apparatus.

FIG. 4 is a schematic view of an etching apparatus.

FIG. 5 is a flowchart for explaining an etching operation.

FIG. 6 is a time chart for explaining an etching operation.

FIG. 7 is a time chart for explaining an etching operation.

FIG. 8 is a distribution chart of the etching amount in the wafer surface.

FIG. 9 is a distribution diagram of the etching amount in the wafer surface.

FIG. 10 is a distribution chart of the etching amount on the wafer surface.

FIG. 11 is a diagram showing the relationship between the etching solution concentration and the etch rate ratio.

FIG. 12 is a diagram for explaining etching conditions.

[Explanation of symbols]

1 ... P-type silicon substrate, 2 ... N-type epitaxial layer, 3
... Semiconductor substrate (silicon wafer), 4 ... Recess, 19 ... K
OH aqueous solution

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Mitsuru Hoshino 1-1, Showa-cho, Kariya city, Aichi, Denso Co., Ltd. (72) Inventor Toshinao Taniguchi 1-1-chome, Showa-cho, Aichi prefecture, Denso, Inc. ( 56) References JP-A-10-335305 (JP, A) JP-A-9-27469 (JP, A) JP-A-8-264504 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/306 H01L 21/3063 H01L 21/308

Claims (5)

(57) [Claims] 1. A silicon wafer having a PN junction is dipped in an alkaline etching solution to perform etching from one surface of the silicon wafer to etch a partial region of the silicon wafer by a predetermined amount and near the PN junction surface. Stop the etching by anodic oxidation of silicon with
An etching method for forming a recess having a PN junction as a bottom surface, in which at least one of lowering the temperature and lowering the concentration of the etching solution is performed before all the etched surfaces in the wafer surface reach the PN junction. A method for etching a silicon wafer, which is characterized by being performed. 2. A silicon wafer having a PN junction is immersed in an alkaline etching solution, and etching is performed from one surface of the silicon wafer to etch a partial area of the silicon wafer by a predetermined amount and near the PN junction surface. Stop the etching by anodic oxidation of silicon with
An etching method for forming a recess having a PN junction as a bottom surface, which is performed to reduce the temperature of the etching solution and to reduce the concentration of the etching solution before the etching-processed surface, which has the fastest etching progress in the wafer surface, reaches the PN junction. A method for etching a silicon wafer, characterized in that at least one of them is performed. 3. The etching of a silicon wafer according to claim 1 or 2, wherein the treatment before and after the low temperature and / or the low concentration of the etching solution is continuously performed in the same bath. Method. 4. An etching solution is prepared by injecting into the processing tank a solution having a temperature and / or a concentration lower than that of the etching solution in the processing tank, and diluting and / or cooling the etching solution. The method for etching a silicon wafer according to claim 3, wherein at least one of lowering the temperature and lowering the concentration is performed. 5. The method according to claim 1, wherein the current flowing through the silicon wafer is detected, and when the current exhibits a desired behavior, at least one of lowering the temperature of the etching solution and lowering the concentration of the etching solution is performed. A method for etching a silicon wafer according to claim 1.