JP3510766B2 - Deflection device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a deflection device having a vertical output function used in a TV receiver, a monitor, a display, etc., which uses a CRT, and particularly drives a vertical deflection coil by class D amplification. The present invention relates to a deflection device.

[0002]

2. Description of the Related Art A conventional vertical output circuit has a problem that it consumes a large amount of power and generates a large amount of heat. If the amount of heat generated is large, a heat sink is required, which increases the cost of the device. Therefore,
It is conceivable to drive the vertical deflection coil by class D amplification to reduce power consumption. PWM for class D amplification
A modulator is required, and a horizontal sawtooth wave (clock) is required for PWM modulation.

On the other hand, the existing vertical deflection device in the form of an IC is usually separated into two ICs, and the IC of the preceding stage is used.
Includes blocks up to the vertical sawtooth wave generation circuit. The latter IC is a high voltage process IC and has an operational amplifier function and an output amplifying function. When it is attempted to perform class D amplification using the conventional vertical deflection device having such an IC arrangement, the configuration shown in FIG. 2 can be considered.

The composite video signal from the input pin (2) of the first IC (1) is applied to the sync separation circuit (3). The sync separation circuit (3) generates a horizontal sync signal and a vertical sync signal. The vertical synchronizing signal is applied to the vertical sawtooth wave creating circuit (4) and converted into a sawtooth wave having a vertical synchronizing signal period. The horizontal sync signal is applied to an AFC loop (8) including a phase comparator (5), an oscillator (6) and a frequency divider (7). The AFC loop (8) oscillates in synchronization with the horizontal sync signal.

The output signal of the frequency divider (7) is supplied to the horizontal deflection coil (9) as a drive signal for horizontal deflection. The FBP (flyback pulse) generated from the horizontal deflection coil (9) is fed back to the phase comparator (5). The sawtooth wave of the vertical synchronizing signal period from the vertical sawtooth wave creating circuit (4) is applied to the second IC (10). The sawtooth wave is applied to the operational amplifier (11) and amplified. The amplified sawtooth wave is PWM-modulated by the PWM modulator (12). A sawtooth wave having a horizontal synchronizing signal period is applied as a clock signal to the PWM modulator (12) from the horizontal sawtooth wave creating circuit (13B). The horizontal sawtooth wave generating circuit (13B) is supplied with the clock signal locked to the horizontal synchronizing signal from the AFC loop (13A). The AFC loop (13A) locks to the horizontal sync signal using the FBP.

As a result, a PWM signal having vertical deflection information is generated from the PWM modulator (12) and the class D amplifier (1
3) is applied. P amplified by class D amplifier (13)
The WM signal has its high-frequency component removed by the coil (14), returns to the original vertical period, and is supplied to the vertical deflection coil (15). Part of the current flowing through the vertical deflection coil (15) is applied to the operational amplifier (11) as a negative feedback signal (NFB).

Therefore, according to the apparatus of FIG. 2, the vertical deflection coil can be driven by class D amplification to reduce the power consumption.

[0008]

However, the device of FIG. 2 has a problem that the number of elements increases. In particular, the AFC loop (13A) of the second IC (10) requires not only the number of elements but also the crystal oscillator (16) external to the IC.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned points, and a sync separation circuit for synchronously separating a horizontal sync signal and a vertical sync signal from an input video signal and a horizontal separation circuit from the sync separation circuit. A first integrated circuit including an AFC loop that operates in synchronization with a synchronization signal and a vertical sawtooth wave generation circuit that generates a vertical sawtooth wave in response to a vertical synchronization signal from the synchronization separation circuit, and the first integrated circuit. A second integrated circuit including a PWM modulation circuit that PWM-modulates the output signal of the AFC loop according to the vertical sawtooth wave of
A vertical deflection coil is driven by class D amplifying a PWM signal from the PWM modulation circuit.

[0010]

FIG. 1 is a circuit diagram showing a deflecting device of the present invention, in which (20) is a first IC (where a clock signal of a horizontal synchronizing signal period from a frequency divider (7) is applied. 1) pin, (21) pin of the second IC (10) to which the clock signal from the pin (20) of the first IC (1) is applied,
(22) is P in response to the clock signal from pin (21)
It is a horizontal sawtooth wave creation circuit that creates a sawtooth wave for WM modulation.

In FIG. 1, the same circuit blocks as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. First
The composite video signal from the input pin (2) of the IC (1) is applied to the sync separation circuit (3). The sync separation circuit (3) generates a horizontal sync signal and a vertical sync signal. The vertical synchronizing signal is applied to the vertical sawtooth wave creating circuit (4) and converted into a sawtooth wave having a vertical synchronizing signal period.
The horizontal sync signal is applied to an AFC loop (8) including a phase comparator (5), an oscillator (6) and a frequency divider (7). A
The FC loop (8) oscillates in synchronization with the horizontal sync signal.

The output signal of the frequency divider (7) is supplied to the horizontal deflection coil (9) as a drive signal for horizontal deflection. The FBP (flyback pulse) generated from the horizontal deflection coil (9) is fed back to the phase comparator (5). The sawtooth wave of the vertical synchronizing signal period from the vertical sawtooth wave creating circuit (4) is applied to the second IC (10). The sawtooth wave is applied to the operational amplifier (11) and amplified. The amplified sawtooth wave is PWM-modulated by the PWM modulator (12). A sawtooth wave having a horizontal synchronizing signal period is applied to the PWM modulator (12) as a clock signal from the horizontal sawtooth wave creating circuit (22). The horizontal sawtooth wave generating circuit (22) is supplied with the clock signal locked to the horizontal synchronizing signal from the AFC loop (8). Therefore, the second I
No need for AFC loop in C (10)
External parts can be reduced.

As a result, a PWM signal having vertical deflection information is generated from the PWM modulator (12) and the class D amplifier (1
3) is applied. P amplified by class D amplifier (13)
The WM signal has its high-frequency component removed by the coil (14), returns to the original vertical period, and is supplied to the vertical deflection coil (15). Part of the current flowing through the vertical deflection coil (15) is applied to the operational amplifier (11) as a negative feedback signal (NFB).

Therefore, according to the apparatus of FIG. 1, the vertical deflection coil can be driven by the class D amplification to reduce the power consumption, the AFC loop is not required, and the number of elements and the external parts of the IC can be reduced. .

[0015]

As described above, according to the present invention, the vertical deflection coil can be driven by class D amplification to reduce the power consumption. The use of class D amplification also has the effect of eliminating the need for a heat sink. Further, according to the present invention, one AFC loop can be reduced, so that there is an effect that the number of elements does not increase even if class D amplification is performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a deflection device of the present invention.

FIG. 2 is a circuit diagram showing a conventional deflection device.

[Explanation of symbols]

(1) First IC (3) Sync separation circuit (4) Vertical sawtooth wave generation circuit (8) AFC loop (10) Second IC (12) PWM modulator (13) Class D amplifier (22) Horizontal sawtooth wave generation circuit

Claims (2)

(57) [Claims] 1. A sync separator circuit for synchronously separating a horizontal sync signal and a vertical sync signal from an input video signal, an AFC loop which operates in synchronization with a horizontal sync signal from the sync separator circuit, and a vertical sync from the sync separator circuit. A first integrated circuit including a vertical sawtooth wave generation circuit for generating a vertical sawtooth wave in response to a signal; and the A according to the vertical sawtooth wave of the first integrated circuit.
A second integrated circuit including a PWM modulation circuit that PWM-modulates an output signal of the FC loop, wherein the PWM signal from the PWM modulation circuit is class-D amplified to drive a vertical deflection coil. . 2. A sync separator circuit for synchronously separating a horizontal sync signal and a vertical sync signal from an input video signal, an AFC loop which operates in synchronization with a horizontal sync signal from the sync separator circuit, and a vertical sync from the sync separator circuit. A first integrated circuit including a vertical sawtooth wave generation circuit that generates a vertical sawtooth wave according to a signal, a negative feedback amplifier that negatively amplifies the vertical sawtooth wave from the first integrated circuit, and the negative feedback amplifier PWM for modulating the output signal of the AFC loop according to the output signal of
And a second integrated circuit including a modulation circuit, wherein the PWM signal from the PWM modulation circuit is class D amplified to drive a vertical deflection coil.