JP3511908B2 - NMOS network logic - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device such as a CPU (Central Processing Unit), a peripheral control LSI, an ASIC, and a memory, which are components of a computer.

[0002]

2. Description of the Related Art In a conventional CMOS logic circuit, C
MOS VLSI Design Principles, translated by Takashi Tomizawa and Yasuo Matsuyama,
As discussed on pages 37 to 44, published by Maruzen Co., Ltd., in order to secure a sufficient DC noise margin or obtain a sufficient circuit delay time characteristic, the channel of the PMOS transistor and the NMOS transistor is used. Determine the width. Further, the number of NMOS transistors connected to the output terminal is determined by a logic function to be realized. That is, in the case of an inverter logic circuit, the number of NMOS transistors connected to the output terminal is one, and in the case of a two-input NOR logic circuit, the number of NMOS transistors connected to the output terminal is two.

As described above, the conventional CMOS logic circuit has
NMOS by DC transfer characteristic, delay time and logic function
NMO connected to transistor channel width and output terminal
The number of S transistors was determined.

[0004]

As the miniaturization progresses, MO
The junction capacitance C _d of the S transistor has decreased, and the power supply voltage V has decreased. As a result, the problem of noise due to α particles, which is conventionally called a soft error, has become apparent. In particular, in the dynamic CMOS logic circuit shown in FIG. 2, the problem of noise due to the α particles is remarkable.

The dynamic circuit shown in FIG. 2 is an example of a two-input OR circuit. The circuit of this conventional example includes a precharge PMOS transistor 101, a discharge NMO
S transistor 102, output inversion buffer 103, logic
It consists of NMOS108. The precharge PMOS transistor 101 is connected between the first power supply terminal 109 and the input terminal 103 of the output inversion buffer. The logic NMOS 108 and the discharge NMOS transistor 102 are connected between the input terminal 107 of the output inversion buffer and the second power supply. It is connected in series between the terminals.

[0006] The input terminal 107 of the output inversion buffer is
The clock signal is precharged to the first power supply potential during the low period, and the output terminal 105 is set to the second power supply potential. Next, during the high period of the clock, the charge at the input terminal 107 of the output inversion buffer is discharged via the discharge NMOS 102 in accordance with the value of the input signal, the output terminal rises to the first power supply potential, and the signal is supplied to the next circuit. Propagating to

Here, if all the input signals are low during the high period of the clock, all the logic NMOSs are turned off, and the input terminal 107 of the output inversion buffer dynamically holds the charge. Assuming that the sum of the junction capacitances of the NMOSs connected to the input terminal 107 of the output inversion buffer is ΔC _d = C _D , the amount of charge held in the input terminal 107 of the output inversion buffer is: Q _C = V · C _D It becomes. Actually, the diffusion capacitance of the precharge PMOS, the input capacitance of the output inversion buffer, the wiring capacitance in the circuit, and the like are further added. However, here, for simplicity, only the diffusion capacitance of the NMOS is considered.

On the other hand, alpha particles and Q _alpha noise amount of charge generated by incident on the diffusion region of the NMOS transistor. When the Q _C ≦ 2Q _alpha, by noise generated by alpha particles, drops below the potential of the input terminal portion 107 is half of the output inverting buffer, causes circuit malfunction.

[0009] The charge amount Q _C held in the input terminal portion 107 of the output inverting buffer, when lowering the power supply voltage becomes whereas small, noise charge amount Q _alpha by alpha particles, does not depend on the supply voltage. Therefore, when the power supply voltage is reduced, α
The effect of noise due to particles tends to be even greater. This problem is conventionally called soft error, and in particular, DR error
It is a problem in AM. However, when the MOS transistor is miniaturized and the power supply voltage is further lowered, CM
Even in OS logic circuits, noise due to α particles cannot be ignored.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to prevent a CMOS logic circuit from malfunctioning even when noise is generated by α particles. For this purpose, the charge amount Q _C held in the input terminal portion 107 of the output inverting buffers of CMOS logic circuits, it is necessary that sufficiently larger than the charge amount Q _alpha generated by noise.

Therefore, the maximum noise charge generated when α particles _enter a transistor constituting a logic circuit is defined as Q _αMAX , the sum of the junction capacitances of the NMOS transistors connected to the output terminal is C _D , the first power supply _Assuming that the potential difference between the first power supply and the second power supply is V, C _D > ( _2QαMAX / V) (1) may be set.

There are several possible ways to achieve this. For example, as shown in FIG. 3, (1) input terminal of the output inverting buffer the C _a extra junction capacitance so as to satisfy the formula 1
07. That is, C _a is added so that C _D = ΣC _d + C _a > ( _2QαMAX / V). C _a can be added by a method such to widen the NMOS diffusion regions. However, in this method, although the noise resistance is increased, an extra capacitance is added inside the circuit, so that there is a problem that the circuit speed is reduced.

In view of the above, a method is conceivable in which the entire logic block is constituted by a logic circuit having a scale satisfying the expression (1).
A circuit having a scale that satisfies the expression (1) means that if the number of NMOS transistors connected to the input terminal unit 107 of the output inversion buffer is n, n or more NMOS transistors that satisfy the expression (1) are output. It is a logic circuit connected in parallel to the input terminal 107 of the inversion buffer.

According to the usual method, when a logic block of a certain scale is realized by a logic circuit, the logic function is constituted by a combination of circuits of a small scale. That is, it is configured by a logic circuit including a two-input OR circuit, a two-input AND circuit, a two-input exclusive logic circuit, and the like. However, such a small-sized circuit has a small value of the number n of the NMOS transistors connected to the input terminal unit 107 of the output inversion buffer, and does not satisfy the expression (1).

Accordingly, the logical expression expressing the function of the logical block is converted into a logical expression of a unit such that the number n of the NMOS transistors connected to the input terminal 107 of the output inversion buffer becomes equal to or more than a value satisfying the expression (1). By expanding, it becomes possible to configure the entire logic block by a combination of logic circuits in which all circuits satisfy the expression (1).

[0016]

FIG. 1 shows a first embodiment of the present invention. The embodiment 100 shown in FIG. 1A is a dynamic circuit having noise resistance to α-ray particles. Precharge PMOS transistor 101, discharge NM
It comprises an OS transistor 102, an output inversion buffer 103, and n logic NMOSs 108 connected in parallel. The precharge PMOS transistor 101 is connected between the first power supply terminal 109 and the input terminal 107 of the output inversion buffer. The logic NMOS 108 and the discharge NMOS transistor 102 are connected to the input terminal 107 of the output inversion buffer.
And a second power supply terminal.

The input terminal 107 of the output inversion buffer is
The clock signal is precharged to the first power supply potential during the low period, and the output terminal 105 is set to the second power supply potential. Next, during the high period of the clock, the charge at the input terminal 107 of the output inversion buffer is discharged via the discharge NMOS 102 in accordance with the value of the input signal, the output terminal rises to the first power supply potential, and the signal is supplied to the next circuit. Propagating to

If the input signals are all low during the high period of the clock, all the logic NMOSs are turned off, and the input terminal 107 of the output inversion buffer dynamically holds the charge. Assuming that the sum of the junction capacitances of the NMOSs connected to the input terminal 107 of the output inversion buffer is ΔC _d = n · C _d = C _D , the amount of charge held in the input terminal 107 of the output inversion buffer is Q _C = V
It becomes C _D. Actually, the diffusion capacitance of the precharge PMOS, the input capacitance of the output inversion buffer, the wiring capacitance in the circuit, and the like are further added.
Consider only the diffusion capacity of This _CD is
The value of n is determined so as to satisfy the expression (1).

From the equation (1), the value of n depends on the noise _QαMAX generated by the α-particles and the power supply voltage V. The amount of noise generated by the α-particle is proportional to the range over which the α-particle runs in the NMOS transistor. Therefore, α
The amount of noise generated by the particles is approximately proportional to the channel width W of the NMOS transistor. That is, assuming that the number of NMOS transistors satisfying the expression (1) is m,
The value of m can be expressed as m = F1 (W) F2 (V) (2) as a function of the channel width W of the NMOS transistor and the power supply voltage V.

The number n of the logic NMOSs 108 connected in parallel is     n ≧ m (3) Is set to satisfy.

FIG. 1 (b) 106 is a symbol diagram showing the circuit diagram 100 of FIG. 1 (a). Indicates that the circuit is an n-input dynamic circuit.

FIG. 4 shows a layout diagram of the circuit diagram 100 shown in FIG. The numbers indicating the parts are the same as those in FIG. As can be seen from the example of this layout diagram, n NMOs
Even if the S transistors are connected in parallel, in practice, n diffusion capacitors of the NMOS transistors may not be connected to the input terminal 107 of the output inversion buffer. Although it depends on the layout method, when n NMOS transistors are connected in parallel, approximately n / 2 diffusion capacitors are often connected. The conditions required in the present invention are:
(1) Total volume C _D satisfying the equation is that it is connected to the input terminal portion 107 of the output inverting buffers. Therefore, assuming that the number of diffusion regions of the NMOS transistor that satisfies the expression (1) is k, n = A · k (4) where A is the layout pattern. Depends on the constant.
Usually, the value of A is smaller than 1, but the value of A can be set to 1 or more depending on the layout.

In the following description, for the sake of simplicity, it is assumed that, when n pieces are connected in parallel on a circuit, n pieces of diffusion regions are connected.

FIG. 5 shows a state of noise generated when α-particles are incident on the NMOS network logic section 104 constituted by connecting the NMOS transistors of FIG. 1 in parallel.

First, in the circuit diagram of FIG. 1, suppose that all input signals are low while the clock is high.
All the logic NMOSs are turned off, and the input terminal portion 107 of the output inversion buffer dynamically holds charges.
NM connected to input terminal 107 of output inversion buffer
Assuming that the total sum of the junction capacitances of the OS is ΔC _d = n · C _d = C _D , the charge amount held in the input terminal 107 of the output inversion buffer is Q _C = V · C _D. Actually, the diffusion capacitance of the precharge PMOS, the input capacitance of the output inversion buffer, the wiring capacitance in the circuit, and the like are further added. However, here, for simplicity, only the diffusion capacitance of the NMOS is considered. Also, a noise current 111 generated when α particles enter the NMOS transistor is shown. The noise current has a peak current I1 and a pulse width of several ps to several tens ps.
Can be assumed.

During the period when the charge is dynamically held, the input terminal 1 of the output inversion buffer shown in the circuit diagram of FIG.
07 when the noise current is generated is 11
It is shown in FIG. Here, n1 to n6 indicate differences depending on the number n of the logic NMOSs connected in parallel. In n1, the number n of the logic NMOSs connected in parallel is small. Therefore, the output sum C _D junction capacitance of the NMOS is connected to the input terminal portion 107 of the inverting buffer is small, the holding amount of charge Q _C is also small. In other words, between the noise charge amount Q _alpha is related to Q _C <Q _α. Therefore, the voltage of the input terminal unit 107 of the output inversion buffer falls to near 0 V due to the noise current, and the circuit malfunctions.

On the other hand, n6 is a logic NM connected in parallel.
The number n of OSs is large. Therefore, large sum C _D of the NMOS of the junction capacitance connected to the input terminal portion 107 of the output inverting buffer, the holding amount of charge Q _C is also large. That is,
Between the noise charge amount Q _alpha, a relationship of Q _C> Q _α. Therefore, the voltage of the input terminal unit 107 of the output inversion buffer slightly drops due to the noise current, and does not cause a malfunction of the circuit. in this way,
The effect on the circuit when noise occurs differs depending on the value of the number n of the logic NMOSs connected in parallel.

In this embodiment, at least the value of n is increased to n3 or more so that even if noise occurs, the circuit does not malfunction. Further, the logic to be designed is developed into logical units in which the value of n is set to be larger than n3.

FIG. 6 shows an application example of the circuit shown in FIG. A plurality of circuits shown in FIG. 1 are connected in series or in parallel to form a certain logic. At this time, the first logic circuit connected to the input terminal of the logic block is an NMOS network logic circuit 11 having a discharge NMOS 102.
3 and the second and subsequent NMOS network logic circuits 115 and 116 connected in series to 113
Does not have MOS. The above is the logic executed within one clock cycle, and the first NMOS network logic circuit 114 of the logic executed in the next clock cycle has the discharge NMOS 102. Thus, only the first logic circuit executed in a certain clock cycle has the discharge NMOS 102,
The other second and subsequent logic circuits include a discharge NMOS 102
The speedup is achieved by adopting a configuration having no.

That is, the first logic circuit in a certain clock cycle is required to start the precharge operation at high speed. If there is no discharge NMOS 102, and if the input signals are all high and the NMOS logic is on, then even if the precharge PMOS is on, current will flow from the NMOS logic to the second power supply. , The output cannot be set low. Therefore, the first logic circuit includes the discharge NMOS 102
is necessary. When the output of the first logic circuit is set low, the input signals of the second logic circuit all go low. Therefore, when precharging the second logic circuit, there is no leakage of current to the second power supply, and a precharge operation can be performed.

The discharge NMOS 102 is necessary for the precharge operation. Conversely, when the discharge operation is performed, one extra NMOS is interposed and the circuit speed is deteriorated. Therefore, in the second and subsequent logic circuits that can perform the precharge operation without the discharge NMOS 102, the configuration without the discharge NMOS 102 is faster.

However, if the logic has too many stages,
It takes time for the input row to be determined. That is, since the precharge time is long, it is conceivable to insert one logic circuit with the discharge NMOS 102 for every certain number of circuit stages.

FIG. 7 shows an application of the circuit shown in FIG. The circuit shown in FIG. 1 is a one-wire logic type NMOS network logic circuit according to the present invention, but is shown in FIG.
The NMOS network logic circuit is a two-wire logic type NMOS network logic circuit. The NMOS logic unit 121
This is a two-wire logic in which the NMOS logic unit 104 in FIG. 1 is configured by both positive and negative logics. Similarly to the NMOS logic unit 104, the NMOS logic unit 121 configured by two-wire logic configures logic so as to satisfy the conditional expression (1). That is, n or more NMOSs are connected in parallel to the input portions of the output inversion buffers of the positive and negative logics. With this configuration, α
A two-wire NMOS network logic circuit that does not malfunction even when line noise occurs can be realized.

The 2-wire NMOS network logic circuit generates a self-synchronizing signal 123 indicating that signal output has been completed. This self-synchronizing signal is used as a precharge PMOS for the second and subsequent NMOS network logic circuits 119 and 120.
, A self-synchronous operation becomes possible.

The details of the circuit operation will be described below. First,
When the logic block starts operating, the reset signal 13
3 goes high. As a result, the self-synchronization signal becomes low, and the second and subsequent NMOS network logic circuits 11
9, 120 are precharged. The outputs of the two-wire NMOS network logic circuits 119 and 120 are all low. After that, the reset signal 133 switches to low,
Keep the row. Next, when the clock signal goes low, the first two-wire NMOS network logic is precharged. Thus, all circuits are in the precharged initial state.

Next, the clock signal goes high, and the input signal propagates. When the outputs 131 and 132 of the two-wire NMOS network logic circuit 120 are determined, one of the outputs 131 and 132, which were both low until now, always changes to high. 131 and 132 are input to a three-input NOR circuit, and the output signal of the self-sync signal 1
23 changes to low. By this series of operations, when the output signal of the two-wire NMOS network logic circuit 120 is determined, the self-synchronization signal 123 becomes low,
The precharge operation of the linear NMOS network logic circuits 119 and 120 is started.

As described above, the operation of the two-wire NMOS network logic circuit in one clock cycle period of one-phase clock can be performed by forming the two-wire NMOS network logic circuit and performing the precharge operation by the self-synchronization signal. It becomes possible. In the case of a one-wire type NMOS network logic circuit, one clock cycle cannot be operated unless a two-phase clock is used.

FIG. 8 shows an NMOS network logic circuit 1.
This is an example in which a fully complementary CMOS logic circuit 124 is connected in series at a stage subsequent to 16. As described above, it is possible to connect a fully complementary CMOS logic circuit in series at the subsequent stage of the NMOS network logic circuit.
The NMOS network logic circuit 116 cannot be connected in series at the subsequent stage of the MOS logic circuit 124. Because, during the precharge period when the outputs of all the other NMOS network logic circuits are low, the output of the fully complementary CMOS logic circuit may be high depending on the logic. In that case, the input signal of the NMOS network logic circuit connected to the next stage is high,
The precharged charge is discharged, and the signal does not propagate. However, when a completely complementary CMOS logic circuit is connected to the subsequent stage of the NMOS network logic circuit, such a problem does not occur, so that the configuration of FIG. 8 is possible. FIG. 9 is an embodiment of the present invention showing a method of logic synthesis. Reference numeral 125 denotes a circuit library having information necessary for logic synthesis constituted by the NMOS network logic circuit according to the present invention. Reference numeral 126 denotes a higher-level description describing a logic to be realized, for example, RTL (Register Transfer Lev.).
This is a logical net file described in el). 127 is a synthesizing program for automatically synthesizing logic using 126 and 125 as input information. An output result 128 of the logic synthesis is a gate-level logic file. At this time, the gate-level netlist 128 is a logic file of the gate description constituted by the NMOS network logic circuit defined by 125 according to the present invention. Therefore, 1
Each of the gate circuits used in the 28 logic files is composed of an NMOS network logic circuit that satisfies the noise conditional expression (1). When a conventional dynamic logic circuit is used, there is no guarantee against noise in the NMOS logic portion, and therefore, if logic is automatically synthesized, a circuit malfunction may occur. If a guarantee circuit for noise is added to the conventional dynamic circuit, there is a problem that circuit characteristics deteriorate. Also, when the NMOS logic of a small unit is used as in the related art, the ratio of the delay time of the output buffer to the total delay time in which the signal propagates through the logic NMOS is large, and the effect of increasing the speed of the dynamic circuit with respect to the completely complementary CMOS circuit is reduced. small. In the present invention, logic synthesis is performed using a circuit library based on an NMOS network logic circuit that does not cause such a problem, and the output result is a logic file of a gate description that does not cause the above-described noise and delay problems.

NMOS defined in circuit library
Since the network logic circuit is a circuit designed to satisfy the noise conditional expression (1), n or more NMOSs are connected in parallel to the input of the output buffer. Therefore, the logic synthesis is optimized to a logic in which many NMOSs are connected in parallel. Whereas conventional logic synthesis uses only the area and the delay time as conditions for optimization, in the present invention, it is a necessary condition for optimization that n or more NMOSs are connected in parallel.

FIG. 10 is an embodiment of the logic synthesis similar to FIG. Reference numeral 129 denotes a circuit library having information necessary for logic synthesis constituted by the NMOS network logic circuit and the completely complementary CMOS logic circuit according to the present invention. Here, the completely complementary CMOS logic circuit is not restricted by the noise conditional expression (1) of the present invention. The logic is synthesized using both the NMOS network logic circuit and the fully complementary CMOS logic circuit. However, as described in the embodiment shown in FIG. 8, it is possible to connect the fully complementary CMOS logic circuit to the subsequent stage of the NMOS network logic circuit. No circuits can be connected. Therefore, it is necessary to add the connection relation by the circuit type to the constraint condition of the logic synthesis.

FIG. 11 shows an embodiment of the logic synthesis similar to FIG. Reference numeral 130 denotes a circuit library having information necessary for logic synthesis constituted by a two-wire logic type NMOS network logic circuit according to the present invention. 2-wire logic type NMOS
Since the synthesis is made into a circuit description using a network logic circuit, either a higher-level description or a logic synthesis program needs a description or logic conversion suitable for the synthesis of two-wire logic.

FIG. 12 shows an embodiment in which a 12-input OR logic and a 6-input select logic are constituted by a conventional dynamic circuit and an NMOS network logic circuit according to the present invention. 134 is a logic circuit based on a conventional dynamic circuit,
135 is an NMOS network logic circuit;
And 135 are equivalent logic.

The logic circuit of the conventional circuit of 134 has 13
6, a two-input NOR circuit using a conventional dynamic circuit,
137 two-input NOR circuit using a conventional dynamic circuit, 138 three-input NOR circuit using a conventional dynamic circuit
The R circuit constitutes a 12-input OR circuit, and 139
3 input selector circuit by the conventional dynamic circuit of
A 6-input select logic is constituted by a 3-input selector circuit of 140 conventional dynamic circuits and a 2-input selector circuit of 141 conventional dynamic circuits.

The logic circuit composed of 135 NMOS network circuits is composed of a 12-input OR circuit composed of 142 NMOS network logic circuits and a 6-input selector circuit composed of 143 NMOS network logic circuits.

As shown in this embodiment, in the conventional dynamic circuit, the logic is configured by combining small-scale NMOS logics in multiple stages.
The network logic circuit forms a logic by connecting a large number of NMOS transistors in parallel.

The conventional dynamic circuit 134 constitutes a logic in units of a gate circuit usually used for a completely complementary CMOS circuit, and has a problem of NMO due to noise.
No consideration is given to connecting a large number of S in parallel. on the other hand,
The NMOS network circuit 135 of the present invention has a circuit configuration in which a large number of NMOSs are connected in parallel in consideration of satisfying the above-mentioned noise conditional expression (1), and the circuit does not malfunction due to noise due to α particles. I have.

[0047]

According to the present invention, it is possible to construct a dynamic circuit that does not cause a circuit malfunction even when α particles enter the circuit. Since noise can be guaranteed without adding a noise assurance circuit, there is no reduction in circuit delay time characteristics due to the noise assurance circuit. That is, the speed is higher than that of a conventional dynamic circuit to which noise assurance is added.

Further, since a circuit in which n or more NMOSs are connected in parallel is used as a basic unit, the effect of speeding up is higher than when a small dynamic circuit is used as a basic unit. That is, in the case of a conventional small circuit unit, NM
The ratio of the delay time of the output buffer to the delay time of the OS logic unit is high, and the effect of increasing the speed on the completely complementary CMOS logic circuit may be small. On the contrary,
In the case of the NMOS network logic circuit according to the present invention, since one output buffer is provided for n or more NMOS logics, the ratio of the delay time of the output buffer unit to the delay time of the NMOS logic is as follows. small.
Therefore, the speed of the NMOS dynamic circuit of the present invention is higher than that of a conventional small-scale dynamic circuit.

[Brief description of the drawings]

FIG. 1 is an NMOS network logic circuit of the present invention.

FIG. 2 shows a conventional dynamic logic circuit.

FIG. 3 is a dynamic logic circuit of the present invention.

FIG. 4 is a layout diagram of an NMOS network logic circuit of the present invention.

FIG. 5 shows noise characteristics of the NMOS network logic circuit of the present invention.

FIG. 6 shows an embodiment of the present invention.

FIG. 7 shows an embodiment of the present invention.

FIG. 8 shows an embodiment of the present invention.

FIG. 9 shows an embodiment of the present invention.

FIG. 10 shows an embodiment of the present invention.

FIG. 11 shows an embodiment of the present invention.

FIG. 12 is a diagram showing a conventional logic circuit and a logic circuit of the present invention.

[Explanation of symbols]

100 ... NMOS network logic circuit of the present invention, 10
1: Precharge PMOS, 102: Discharge NMO
S, 103: output buffer, 104: NMOS network logic unit, 105: output terminal, 106: symbol diagram of NMOS network logic circuit, 107: input terminal of output inversion buffer circuit, 108: logic NMOS, 109: first
Power terminal 110, a second power terminal 111, a noise current due to α particles, a voltage 112
14 ... NMOS network logic circuit with discharge NMOS, 115, 116 ... Discharge NMO
NMOS network logic without S, 117, 11
8 ... 2-wire NMOS network logic circuit with discharge NMOS, 119, 120 ... 2-wire NMOS network logic circuit without discharge NMOS, 121 ... 2-wire N
MOS network logic section, 122... 3-input NOR circuit, 123... Self-synchronization signal indicating completion of signal processing, 12.
4 ... Complementary CMOS circuit, 125 ... Circuit library consisting of NMOS network logic unit, 126 ... RT
L netlist 127 ... automatic logic synthesis program, 1
28: Gate level netlist, 129: NMOS
A circuit library consisting of a network logic circuit and a fully complementary CMOS circuit; a circuit library consisting of a two-line NMOS network logic circuit; an output signal of a positive logic; an output signal of a negative logic; a reset signal; 134: a logic circuit based on a conventional dynamic circuit; 135: an NMOS network logic circuit of the present invention; 136, 137: 2 based on a conventional dynamic circuit
Input NOR circuit, 138: 3-input NOR circuit using conventional dynamic circuit, 139, 140: 3-input selector circuit using conventional dynamic circuit, 141: 2-input selector circuit using conventional dynamic circuit, 142: NMOS network logic circuit of the present invention 12-input OR circuit, 143... 6-input selector circuit using the NMOS network logic circuit of the present invention.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-56374 (JP, A) JP-A-11-68549 (JP, A) JP-A-11-261406 (JP, A) JP-A 9-96 232523 (JP, A) JP-A-2-168724 (JP, A) JP-A-10-93411 (JP, A) JP-A-7-288465 (JP, A) JP-A-62-224118 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 19/096

Claims (7)

(57) [Claims] 1. A semiconductor integrated circuit in which a plurality of field effect transistors are formed on the same semiconductor substrate, a first power terminal, a second power terminal, an output inversion buffer, and the first power terminal. And a PMOS transistor connected between the second power supply terminal and the input of the output inversion buffer, and a plurality of parallel-connected NMOS transistors connected between the second power supply terminal and the input of the output inversion buffer. A logic circuit, wherein the sum of the junction capacitances of the NMOS transistors is 2Q _α
MAX / V (Q _{α MAX} is the drain area of the NMOS transistor
The maximum noise charge generated when α particles enter the region
V is larger than the potential difference between the first power supply and the second power supply)
A semiconductor integrated circuit characterized by: 2. The device according to claim 1, wherein a unit junction capacitance corresponding to the drain of one of the NMOS transistors is C _d , the number of the NMOS transistors is n ,
The sum of junction capacitance of the NMOS transistor when the C _D, a semiconductor integrated circuit satisfying n · C _d ≧ C _D. 3. A semiconductor integrated circuit having a plurality of logic circuit blocks constituted by a plurality of field effect transistors, wherein at least one of the logic circuit blocks has a first power supply terminal, a second power supply terminal, and an output. An inversion buffer, a PMOS transistor connected between the first power supply terminal and the input of the output inversion buffer, and a PMOS transistor connected between the second power supply terminal and the input of the output inversion buffer ;
A plurality of NMOS transistors connected in parallel ,
The total sum of the junction capacitances of the NMOS transistor is C _D , the maximum noise charge generated when α particles enter the drain region of the NMOS transistor is Q _{α MAX} , and the potential difference between the first power supply and the second power supply is If V, C
_{D> (2Q α MAX / V} ) in a semiconductor integrated circuit. 4. The logic circuit according to claim 3, wherein at least one of the logic circuit blocks is a logic circuit block that operates in synchronization with a clock signal, and at least one of the logic circuit blocks is a logic circuit block that is not synchronized with a clock signal. A semiconductor integrated circuit. 5. The semiconductor integrated circuit according to claim 4 , wherein the logic circuit block not synchronized with the clock signal operates by a signal indicating completion of signal processing. 6. The semiconductor integrated circuit according to claim 3, wherein a completely complementary static CMOS logic circuit is connected to an output terminal of said logic circuit block. 7. A method for producing a semiconductor integrated circuit in which a plurality of field-effect transistors are formed on the same semiconductor substrate, comprising: a second power supply terminal constituting a CMOS circuit and an input of an output inversion buffer. And a plurality of N connected in parallel.
The sum of the junction capacitances of the MOS transistor and the NMOS transistor is C _D , the maximum noise charge generated when α particles enter the drain region of the NMOS transistor is Q _{α MAX} , and the potential difference between the first power supply and the second power supply. If the set to V, C _D> generation method of a semiconductor integrated circuit which connects the NMOS transistor to satisfy the condition of _(2Q α _MA / V) in parallel.