JP3512715B2 - Bus termination adjusting device and bus termination adjusting method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus termination adjusting device and a bus termination adjusting method.

[0002]

2. Description of the Related Art Conventionally, there is a bus termination automatic adjustment circuit which automatically adjusts a bus termination condition in a transmission circuit. The bus termination automatic adjustment circuit is suitable for reducing power consumption, preventing device destruction, and reducing leak current, particularly in a bus using a burst data signal.

As a conventional example of the above-mentioned bus termination automatic adjusting circuit, for example, a technique disclosed in Japanese Patent Laid-Open No. 11-308251 has been proposed. This publication discloses a data transmission circuit having pull-up and pull-down resistors and a differential line receiver in a data reception 2 input terminal section from a balanced 2-line bus line, each of the data reception 2 input terminal sections being described. Disclosed is a data transmission circuit characterized by including detection means for detecting a voltage and its potential difference, and control means for variably controlling the resistance values of the pull-up and pull-down resistors according to the detection outputs. .

[0004]

However, the above-mentioned conventional example has the following problems.

In the above-mentioned conventional example, in a bus using a burst data signal, the bus and the ground are connected via a pull-down resistor having a high resistance value and power consumption generally generated when operating the bus. In this case, the discharge of the electric charge does not proceed, and the confirmation to the L level is delayed. For this reason,
Load on the device due to continuous uncertain state (CMO that does not allow input of signals whose H level and L level are uncertain)
If a device such as an S logic LSI is connected to the bus, this phenomenon may destroy the device.) And after using high impedance, a small resistance is used to quickly determine the level. There has been concern that the power consumption may increase and that a leak current may occur in the high impedance state.

An object of the present invention is to reduce power consumption by using a clock and a state detection signal to operate the bus only at the timing of changing the bus in the signal transmission state.
Immediately after the transition to the standby state, by connecting a pull-down or pull-up resistor with a small resistance, the high impedance is quickly set to the L level or the H level to reduce the load on the device, and in the standby state, A bus termination adjusting device and a bus termination adjusting method capable of reducing a leak current by connecting a high resistance pull-down or pull-up resistor.

[0007]

[0008]

According to the present invention, there is provided a bus termination adjustment device for adjusting a bus termination circuit in a transmission circuit, when all devices connected to the bus are in a standby state immediately after a standby transition. A control means for disconnecting the terminating resistor from the DC power source and switching to a pull-down resistor or a pull-up resistor having a low resistance value is provided.

[0009]

Further, according to the present invention, in a bus termination adjusting device for adjusting a bus terminating circuit in a transmission circuit, a terminating resistor and a DC power source are connected and connected to the bus only during a waveform transition in a signal transmission state. In the state immediately after the transition to the standby state where all the devices that have been switched to the reception waiting state are disconnected, the terminating resistor is disconnected from the DC power supply and switched to a pull-down resistor or a pull-up resistor with a low resistance value, and all the devices connected to the bus receive It is characterized by comprising control means for switching the pull-down resistor or the pull-up resistor from a low resistance to a high resistance in the standby state after shifting to the waiting state and after the level is fixed.

The bus termination adjusting device of the present invention is shown in FIG.
The bus (10) in the transmission circuit will be described with reference to FIG.
9) Bus termination adjusting device (10) for adjusting the termination circuit
In 8), the terminal resistor (102) and the DC power supply (103) are connected only during the waveform transition in the signal transmission state, and the devices connected to the bus are all in the standby state immediately after the transition to the standby state. , The terminating resistor is disconnected from the DC power source, and the pull-down resistor (10
4) or switching to a pull-up resistor, and when all devices connected to the bus shift to a reception waiting state and are in a standby state after the level is fixed, the pull-down resistor or the pull-up resistor is changed from low resistance to high resistance (106). The control means (101, 105, 107) for switching is provided.

[Operation] In the bus termination adjusting device of the present invention, the termination resistor is installed on the bus, and the termination resistor and the DC power source are connected only at the time of waveform transition. Therefore, the reflection noise can be reduced and the power consumed by the terminating resistor can be reduced. Further, when all the devices on the bus are in the high impedance state, the level is quickly determined to prevent the trouble of the circuit connected to the bus. Further, after the level determination is completed, a pull-down resistor or a pull-up resistor having a high resistance value is electrically and automatically connected. for that reason,
It is possible to reduce the leak current flowing into the input / output device connected to the bus and the leak current flowing out from the input / output device.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION First, before describing the first and second embodiments of the present invention, the features and basic configuration of the present invention will be described.

According to the present invention, when a signal is transmitted through a bus, a signal capable of recognizing a transition state of a transmission waveform, such as a clock, is used as a trigger to connect a terminating resistor only at the time of waveform transition, thereby reducing reflection noise and power consumption. The first feature is to reduce the above. In addition, the present invention disconnects the terminating resistor and pulls down (or pulls) a low resistance value when all the devices connected to the bus immediately shift to the reception waiting state (standby state) and then electrically shift to the high impedance state. The second feature is to quickly settle to L level (or H level) by switching to (up) resistance and prevent device breakdown.

Further, according to the present invention, after the state is shifted to the standby state and the level is determined, the pull-down (or pull-up resistance) is switched from low resistance to high resistance, so that leakage into or out of the device is caused. The third feature is that the current is reduced.

The bus termination automatic adjusting circuit according to the present invention, as shown in FIG.
7, a terminating resistor 102, a DC power supply 103, pull-down resistors 104 and 106, a control signal generation circuit 108, a bus 109, and a data input / output device 110. Reference numerals 111, 112 and 113 in the figure denote control signals.

By the control signal generation circuit 108,
The control circuit 1 uses the control signal 111 generated by using a clock or a state signal that can record the transition state of the waveform as a trigger.
01, and by connecting the terminating resistor 102 only at the time of the waveform transition in the signal transmission state, the reflection of the waveform is prevented,
At the same time, reduce power consumption. At that time, the control signal 112 and the control signal 113 from the control signal generation circuit 108
And the pull-down resistor 104 and the pull-down resistor 106 are electrically separated by the operation of the control circuit 105 and the control circuit 107 (first characteristic).

Immediately after shifting to the standby state,
The control signal 112 and the control signal 113 output from the control signal generation circuit 108 are transmitted, and the pull-down resistor 104 having a low resistance value and the pull-down resistor 106 having a high resistance value are electrically operated by the operations of the control circuit 105 and the control circuit 107. By connecting, the L level can be quickly fixed and the device is prevented from being destroyed (second feature).

After shifting to the standby state and the level being fixed, the control signal 112 is transmitted from the control signal generation circuit 108, and the pull-down resistor 104 is electrically disconnected by the operation of the control circuit 105 and connected to the bus. By setting only the high resistance pull-down resistor 106 as the resistance, the leak current flowing into or out of the device is reduced (third feature).

According to the first to third features of the present invention, an optimal terminating circuit is configured for each of the signal transmission state, the state immediately after transition to standby and the standby state.

[First Embodiment] Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

(1) Description of Configuration The bus termination automatic adjustment circuit of the first embodiment of the present invention is shown in FIG.
As shown in FIG.
7, a terminating resistor 202, a DC power source 203, pull-down resistors 204 and 206, a control signal generating circuit 208, a bus 209, and a data input / output device 210. Further, the control signal generating circuit 208 includes a differentiating circuit 215, a low pass filter 217, an AND gate 218, an inverter gate 219, and a transistor 22.
It has 0 and 221. 211, 212, 21 in the figure
3 is a control signal, 214 is a clock input, and 216 is a state detection input.

In the first embodiment of the present invention, in a bus configuration in which a plurality of data input / output devices 210 are connected to the bus 209, the states of the bus 209 are a signal transmission state, a state immediately after transition to standby, and a standby state. Divided into states,
The terminal circuit configuration is automatically adjusted to suit each condition.

The above configuration will be described in detail. In the differentiating circuit 215 of the control signal generating circuit 208, the clock input 21
The clock input from 4 is differentiated. Next, the AND gate 218 of the control signal generation circuit 208 controls the output of the differential signal output from the differentiating circuit 215 with the state signal input from the state detection input 216. As a result, the control signal 21 is output from the control signal generation circuit 208.
1 is output. The control circuit 201 uses the control signal 211 to control electrical connection between the terminating resistor 202 and the DC power source 203.

The low-pass filter 217 of the control signal generation circuit 208 blunts the state signal waveform input from the state detection input 216. The transistor 220 controls the output of the blunted signal output by the low pass filter 217 by using the signal obtained by inverting the state signal input from the state detection input 216 by the inverter gate 219. In the transistor 221, the state signal input from the state detection input 216 is used to change the output of the transistor 220 to a value other than the state immediately after the transition to the standby state.
By fixing it to the L level, the state of the control signal 212 is controlled. As a result, the control signal generation circuit 20
8, the control signal 212 is output. The control circuit 205 uses the control signal 212 to control the electrical connection between the pull-down resistor 204 and the ground.

The inverter gate 219 of the control signal generation circuit 208 inverts the state signal input from the state detection input 216 and outputs it as the control signal 213. The control circuit 207 uses the control signal 213 to control electrical connection between the pull-down resistor 206 and the ground.

As the pull-down resistor 204, a resistor having a lower resistance value than that of the pull-down resistor 206 is used.

(2) Description of Operation Next, the operation of the first embodiment of the present invention will be described with reference to FIGS.
Will be described in detail with reference to.

The automatic adjustment of the termination circuit configuration according to the bus state, which is a feature of the present invention, is performed by the control signal generation circuit 20.
8 control signal 211, control signal 212, control signal 2
This is realized by controlling the electrical connection between the terminating resistor 202, the pull-down resistor 204, the pull-down resistor 206 and the DC power source 203 or the ground at 13.

First, in the signal transmission state, by controlling the control circuit 201 by the control signal 211 output from the control signal generation circuit 208, the terminating resistor 202 and the DC power source 203 are electrically connected and disconnected. Further, the pull-down resistor 204 and the pull-down resistor 206 are
With the control signal 212 and the control signal 213 output from the control signal generation circuit 208, the control circuit 205
By controlling the control circuit 207, it is electrically disconnected from the ground.

The operation is shown in the time chart of FIG.
As shown in FIG. 3, the clock input from the clock input 214 is differentiated by the differentiation circuit 215 of the control signal generation circuit 208. The differential signal output from the differentiating circuit 215 is output-controlled by the AND gate 218 of the control signal generating circuit 208 using the state detection signal input from the state detecting input 216.

As shown in FIG. 3, in the signal transmission state, the state detection signal input from the state detection input 216 becomes H level, so that the differential signal is output as the control signal 211 to the control circuit 201. Control circuit 201
Turns ON for the time when the control signal 211 is at the H level, and electrically connects and disconnects the terminating resistor 202 and the DC power supply 203.

Further, as shown in FIG. 3, in the signal transmission state, the state detection signal input from the state detection input 216 is supplied to the inverter gate 21 of the control signal generation circuit 208.
When the control signal 213 generated by inverting at 9 becomes L level, the control circuit 207 is turned off and the pull-down resistor 206 is electrically disconnected from the ground.

Further, the transistor 221 is turned on by the state detection signal input from the state detection input 216, and the control signal 212 is set to L level. Control signal 212
Becomes L level, the control circuit 205 becomes O
The FF state is set, and the pull-up resistor 205 is also electrically disconnected from the ground.

Since the control signal 211 is generated by differentiating the clock input from the clock input 214, it has a pulse width of 1/2 or less of the clock cycle. Bus 209
Assuming that the transition of the signal waveform transmitted between the data input / output devices 210 connected to each other is performed in synchronization with the clock, the terminating resistor 202 is connected to the DC power source 203 only when the signal waveform transitions by the control signal 211. Will be done.

When a signal is transmitted between the data input / output devices 210, signal reflection occurs at the time of transition of the signal waveform, and therefore, this configuration can sufficiently prevent the signal reflection. Further, since the time for which the terminating resistor 202 is connected to the DC power source 203 is 1/2 or less of the clock cycle, the power consumption is reduced in the configuration of the present invention as compared with the power consumption when the terminating resistor 202 is constantly connected to the DC power source. It is possible to reduce it to 1/2 or less.

Next, immediately after the transition to the standby state, the control signal 21 output from the control signal generation circuit 208 is output.
By controlling the control circuit 201 with 1,
The terminating resistor 202 and the DC power source 203 are electrically disconnected. The pull-down resistor 204 having a low resistance value is provided in the control signal generation circuit 208 in the state immediately after shifting to the standby state.
The control signal 212 output from the control circuit 2
By controlling 05, it is electrically connected to ground.

By connecting the pull-down resistor 204 to the ground, the level of the bus 209 is quickly fixed at the L level. The pull-down resistor 206 receives the control signal 213 output from the control signal generation circuit 208,
By controlling the control circuit 207, it is electrically connected to the ground.

The operation is shown in the time chart of FIG.
As shown in FIG. 3, when the state detection signal input from the state detection input 216 becomes L level, the control signal 21
1 is fixed to L level. When the control signal 211 becomes L level, the control circuit 201 is turned off, and the terminating resistor 202 and the DC power source 203 are electrically disconnected.

The low-pass filter 217 of the control signal generation circuit 208 slows down the state detection signal input from the state detection input 216. This is shown in the low pass filter output (217) in FIG. At the same time, the transistor 221 is turned off when the state detection signal input from the state detection input 216 becomes L level, and is electrically disconnected from the ground.

On the other hand, the transistor 220 is turned on by inputting a signal obtained by inverting the state detection signal input from the state detection input 216 by the inverter gate 219, and outputs the signal input from the low pass filter 217 as the control signal 212. To do. This is shown in control signal 2 in FIG.
12 shows. In the control circuit 205, the control signal 2
According to the waveform of 12, the pull-down resistor 204 and the ground are electrically connected.

The inverter gate 219 of the control signal generation circuit 208 inverts the state detection signal input from the state detection input 216 and outputs it as the control signal 213. As shown in FIG. 3, the control circuit 207 is turned on when the control signal 213 becomes H level, and electrically connects the pull-down resistor 206 and the ground.

When the data input / output device 210 shifts to a standby state in which all of the data input / output devices 210 are in a high impedance state (immediately after the shift to standby), the bus 209 and the ground are temporarily connected via the pull-down resistor 204 having a low resistance value. By accelerating the discharge effect of the electric charge accumulated in the bus, and by confirming to L level quickly,
The load on the device can be reduced.

Finally, in the standby state, only the pull-up resistor 206 having a high resistance value is connected to the ground. In the standby state, as shown in FIG. 3, the control signal 213 output from the control signal generation circuit 208 is fixed to the H level to turn on the control circuit 207. As a result, the pull-down resistor 206 is
It is electrically connected to ground.

As shown in FIG. 3, when the control signal 211 output from the control signal generation circuit 208 becomes L level, the terminating resistor 202 is controlled.
1 is turned off, and the terminating resistor 202 and the DC power source 20
3 is electrically disconnected.

The pull-down resistor 204 having a low resistance value is
As shown in FIG. 3, when the control signal 212 output from the control signal generation circuit 208 settles to the L level, the control circuit 205 is turned off and electrically disconnected from the ground.

When all the data input / output devices 210 connected to the bus 209 are in the high impedance state, only the pull-down resistor 206 having a high resistance value becomes effective, so that the data input / output device 210 outputs the data. Leakage current can be minimized.

[Second Embodiment] Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

(1) Description of Configuration The bus termination automatic adjustment circuit of the second embodiment of the present invention is shown in FIG.
As shown in, the control circuits 301, 305, 30
7, a terminating resistor 302, a DC power source 303, pull-down resistors 304 and 306, a control signal generation circuit 308, a bus 309, and a data input / output device 310. Further, the control signal generation circuit 308
LL (Delay Locked Loop) 15, counter 317, A
It has ND gates 318, 320, 323, inverter gates 319, 325, and a decoder 324. In the figure, 311, 312, 313 are control signals, 316 is a state detection input, 321 is a basic tone clock, and 322 is a 90 degree clock.

In the second embodiment of the present invention, in the bus configuration in which a plurality of data input / output devices 310 are connected to the bus 309, the states of the bus 309 are the signal transmission state, the state immediately after transition to standby, and the standby state. Divided into states,
The terminal circuit configuration is automatically adjusted to suit each condition.

The above configuration will be described in detail. The DLL 315 of the control signal generation circuit 308 controls the clock input 314.
A basic tone clock 321 and a 90-degree clock 322 are generated and output based on the input clock.

Next, the AND gate 323 of the control signal generation circuit 308 takes an AND logic with the basic tone clock 321 and the signal obtained by inverting the 90-degree clock 322 by the inverter gate 325 to control the output of the AND gate 323. The state signal input from the state detection input 316 is used. As a result, the control signal generation circuit 308
The control signal 311 is output. Control circuit 3
In 01, the control signal 311 is used to control the electrical connection between the terminating resistor 302 and the DC power source 303.

In the counter 317 of the control signal generation circuit 308, only when the state signal input from the state detection input 316 is L level, the clock input 314 performs the count-up operation, and the value is input to the decoder 324, When the count value is "0" to "2", a signal that becomes H level is output.

The output of the signal output from the decoder 324 is controlled by using the signal obtained by inverting the state signal input from the state detection input 316 by the inverter gate 319. As a result, the control signal generation circuit 308
Accordingly, the control signal 312 is output. The control circuit 305 uses the control signal 312 to pull down the pull-down resistor 3
The electrical connection between 04 and the ground is controlled.

The inverter gate 319 of the control signal generation circuit 308 inverts the state signal input from the state detection input 316 and outputs it as the control signal 313. The control circuit 307 uses the control signal 313 to control the electrical connection between the pull-down resistor 306 and the ground.

As the pull-down resistor 304, a resistor having a lower resistance value than that of the pull-down resistor 306 is used.

(2) Description of Operation Next, the operation of the second embodiment of the present invention will be described with reference to FIGS.
Will be described in detail with reference to.

The automatic adjustment of the termination circuit configuration according to the bus state, which is a feature of the present invention, is performed by the control signal generation circuit 30.
Control signal 311 from 8, control signal 312, control signal 3
This is realized by controlling the electrical connection between the terminating resistor 302, the pull-down resistor 304, the pull-down resistor 306 and the DC power source 303 or the ground at 13.

First, in the signal transmission state, by controlling the control circuit 301 with the control signal 311 output from the control signal generation circuit 308, the terminating resistor 302 and the DC power source 303 are electrically intermittently connected. Further, the pull-down resistor 304 and the pull-down resistor 306 are
With the control signal 312 and the control signal 313 output from the control signal generation circuit 308, the control circuit 305
By controlling the control circuit 307, it is electrically disconnected from the ground.

The operation is shown in the time chart of FIG.
As shown in FIG. 5, the DL of the control signal generation circuit 308 is based on the clock input from the clock input 314.
Keynote clock 321 and 90-degree clock 32 from L315
Output as 2. The 90-degree clock 322 output from the DLL 315 is inverted by the inverter gate 325, AND logic is taken in the basic tone clock 321 and the AND gate 323, and Du is input to the clock input 314.
The AND gate 318 outputs a control signal 311 in FIG. 5 using the state detection signal input from the state detection input 316.

As shown in FIG. 5, in the signal transmission state, the state detection signal input from the state detection input 316 becomes H level, so that the AND gate 318 outputs the control signal 311 to the control circuit 301. The control circuit 301 is in the ON state for the time when the control signal 311 is at the H level, and electrically connects and disconnects the terminating resistor 302 and the DC power source 303.

Further, as shown in FIG. 5, in the signal transmission state, the state detection signal input from the state detection input 316 is supplied to the inverter gate 31 of the control signal generation circuit 308.
The control signal 313 generated by inverting at 9
When the level becomes high, the control circuit 307 becomes O
In the FF state, the pull-down resistor 306 is electrically disconnected from the ground.

The control signal 311 is obtained by ANDing the clock input from the clock input 314 with the basic tone clock 321 and the 90-degree clock 322 by the AND gate 323, so that the pulse width is 1/4 or less of the clock period. Become. Data input / output device 31 connected to bus 309
If the transition of the signal waveform transmitted between 0s is performed in synchronization with the clock, the terminating resistor 302 is connected to the DC power supply 303 only when the signal waveform transitions by the control signal 311.

When signals are transmitted between the data input / output devices 310, since signal reflection occurs at the time of transition of the signal waveform, this configuration can provide sufficient signal reflection countermeasures. Further, since the time for which the terminating resistor 302 is connected to the DC power source 303 is 1/4 or less of the clock cycle, compared with the power consumption when the terminating resistor 302 is always connected to the DC power source, the power consumption of the configuration of the present invention is 1 It is possible to reduce it to / 8 or less.

Next, in the state immediately after shifting to the standby mode, the control signal 31 output from the control signal generation circuit 308 is output.
By controlling the control circuit 301 with 1, the terminating resistor 302 and the DC power source 303 are electrically disconnected. In the state immediately after shifting to the standby state, the pull-down resistor 304 having a low resistance value is controlled by the control signal generation circuit 308.
The control signal 312 output from the control circuit 3
By controlling 05, it is electrically connected to ground.

By connecting the pull-down resistor 304 to the ground, the level of the bus 309 is quickly fixed at the L level. The pull-down resistor 306 receives the control signal 313 output from the control signal generation circuit 308,
By controlling the control circuit 307, it is electrically connected to the ground.

The operation is shown in the time chart of FIG.
As shown in FIG. 5, when the state detection signal input from the state detection input 316 becomes L level, the control signal 31
1 is fixed to L level. When the control signal 311 becomes L level, the control circuit 301 is turned off, and the terminating resistor 302 and the DC power source 303 are electrically disconnected.

In the counter 317 of the control signal generation circuit 308, the count-up operation is started by the clock input 314 only when the state detection signal input from the state detection input 316 is at L level, and the count value is "0" to "2". '
The decoder 324 outputs a signal which becomes the H level only in the case of. This is shown in the decoder (324) waveform of FIG.

On the other hand, the AND gate 320 controls the output by inputting the signal obtained by inverting the state detection signal input from the state detection input 316 by the inverter gate 319, and outputs the signal output from the decoder 324 to the control signal 31.
Output as 2. This is shown as the control signal 312 in FIG. The control circuit 305 electrically connects the pull-down resistor 304 and the ground according to the waveform of the control signal 312.

Further, the inverter gate 319 of the control signal generation circuit 308 inverts the state detection signal input from the state detection input 316 and outputs it as the control signal 313. As shown in FIG. 5, the control circuit 307 is turned on when the control signal 313 becomes H level, and electrically connects the pull-down resistor 306 and the ground.

When all the data input / output devices 310 shift to the standby state where they are all in the high impedance state (immediately after the shift to the standby state), the bus 309 is temporarily connected to the ground via the pull-down resistor 304 having a low resistance value. By accelerating the discharge effect of the electric charge accumulated in the bus, and by confirming to L level quickly,
The load on the device can be reduced.

Finally, in the standby state, only the pull-up resistor 306 having a high resistance value is connected to the ground. In the standby state, as shown in FIG. 5, the control signal 313 output from the control signal generation circuit 308 is fixed to the H level, so that the control circuit 307
Turns on. As a result, the pull-down resistor 306
Is electrically connected to ground.

As shown in FIG. 5, when the control signal 311 output from the control signal generation circuit 308 becomes L level, the terminating resistor 302 is controlled by the terminating resistor 302.
1 is turned off, and the terminating resistor 302 and the DC power source 30
3 is electrically disconnected.

The pull-down resistor 304 having a low resistance value is
As shown in FIG. 5, by fixing the control signal 312 output from the control signal generation circuit 308 to the L level, the control circuit 305 is turned off and electrically disconnected from the ground.

When all the data input / output devices 310 connected to the bus 309 are in the high impedance state, only the pull-down resistor 306 having a high resistance value becomes valid, so that the data input / output device 310 outputs. Leakage current can be minimized.

[0076]

As described above, according to the present invention,
By installing the terminating resistor on the bus and connecting the terminating resistor and the DC power source only at the time of waveform transition, it is possible to reduce the reflection noise and the power consumed by the terminating resistor. Further, when all the devices on the bus are in the high impedance state, the level is quickly determined to prevent the trouble of the circuit connected to the bus. Furthermore, after the level is fixed, the pull-down resistor or pull-up resistor with a high resistance value is automatically and automatically connected so that the leak current flowing into the I / O device connected to the bus and the I / O device may The leak current flowing out can be reduced.

According to the present invention, it is possible to connect an optimal termination circuit during signal transmission by automatically adjusting the termination circuit configuration in the signal transmission state and other states.
In the signal transmission state, it is optimal to connect the terminating resistor with a DC power source having a signal amplitude of 1/2. With this termination circuit configuration, the signal amplitude is not biased to either the H level or the L level, and a noise margin for the H level and the L level can be secured. On the other hand, in the standby state where the input / output device does not perform signal transmission on the bus, it is necessary to determine the level to H level or L level in order to prevent device destruction. Therefore, the termination circuit configuration in the signal transmission state cannot be applied in the standby state. In the present invention,
This problem can be solved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a bus termination automatic adjustment circuit of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a bus termination automatic adjustment circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing various signal waveforms in the bus termination automatic adjustment circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a bus termination automatic adjustment circuit according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing various signal waveforms in the bus termination automatic adjustment circuit according to the second embodiment of the present invention.

[Explanation of symbols]

101, 105, 107, 201, 205, 207, 3
01, 305, 307 Control circuit 102, 202, 302 Termination resistor 103, 203, 303 DC power supply 104, 106, 204, 206, 304, 306 Pull-down resistor 108, 208, 308 Control signal generation circuit 109, 209, 309 Bus

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenji Shito, Kenji Shido, 1-403, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa NEC Telecom Systems Stock Company In-house (72) Masaki Sato, 1-chome, Kosugi-cho, Nakahara-ku, Kawasaki, Kanagawa 403 Nippon Electric Telecom System Stock Company In-house (72) Inventor Kazuhiko Niitsuma 1-chome Kosugi-cho, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 403 In-house Electric Telecom System Stock Company (72) Inventor Asai Saoh Kosugi, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 403, Machi 1-chome, Nippon Telecom System Stock Association (56) Reference JP 10-268992 (JP, A) JP 7-273780 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 25/02 G06F 1/32 G06F 3/00 H03K 19/0175 H04B 3/50

Claims (4)

(57) [Claims] 1. A bus termination adjusting device for adjusting a bus terminating circuit in a transmission circuit, wherein a terminating resistor is disconnected from a DC power source immediately after a transition to a standby state in which all devices connected to the bus have transitioned to a reception waiting state. A bus termination adjusting device comprising a control means for switching to a pull-down resistor or a pull-up resistor having a low resistance value. 2. A bus termination adjusting device for adjusting a bus terminating circuit in a transmission circuit, wherein a terminating resistor and a DC power supply are connected only when a waveform transitions in a signal transmission state, and a device connected to the bus is provided. Immediately after the transition to the standby state where all of the devices are connected to the standby state, the terminating resistor is disconnected from the DC power supply and switched to a pull-down resistor or a pull-up resistor with a low resistance value, and all devices connected to the bus transition to the standby state. In the standby state after the level is established, the bus termination adjusting device is provided with a control means for switching the pull-down resistor or the pull-up resistor from low resistance to high resistance. 3. A control signal generating means for generating a control signal such as a clock or a status signal capable of recognizing a transition state of the transmission waveform, wherein the control means is provided only when the waveform transitions during the signal transmission state. The bus termination adjusting device according to claim 1 or 2 , wherein the termination resistance and the DC power supply are connected by using the control signal transmitted from the control signal generation means as a trigger. 4. A bus termination adjusting method for adjusting a bus termination circuit in a transmission circuit, wherein a terminating resistor and a DC power source are connected only when a waveform transitions in a signal transmission state, and a device connected to the bus is provided. Immediately after the transition to the standby state where all of the devices are connected to the standby state, the terminating resistor is disconnected from the DC power supply and switched to a pull-down resistor or a pull-up resistor with a low resistance value, and all devices connected to the bus transition to the standby state. Then, in the standby state after the level is established, the pull-down resistor or the pull-up resistor is switched from low resistance to high resistance.