JP3513802B2 - Direct digital frequency synthesizer device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct digital frequency synthesizer for generating a sin or cos signal of an arbitrary frequency digitally.
nthesizer (DDS) device. [0002] DDS technology is well known and is disclosed in various documents. Examples of patents or utility model publications relating to DDS are as follows. JP-A-3-117115 "Direct digital frequency synthesizer" JP-A-10-31529 "Spread spectrum method and spread spectrum clock generator of clock generator" Japanese Utility Model Laid-Open Publication No. 4-36318 "Sweep frequency oscillator" JP-A-11-31924 "Direct digital frequency synthesizer, phase-locked frequency synthesizer and transmitter / receiver" JP-A-6-252645 "Direct digital frequency synthesizer" JP-A-5-145342 "Variable frequency signal generation method" JP-A-10-126158 "Frequency synthesizer" JP-A-7-131343 "Frequency synthesizer" JP-A-10-41817 "Synchronous generation circuit" JP-A-8-256058 "Signal generation device" JP-A-3-105020 "Sine wave generation circuit using DDS" No. 9-506490, "Narrow band, arbitrary high frequency modulation and noise generator" [0003] Next, DDS will be briefly described. D
The DS includes an accumulator and a sin / cos ROM (read only memory). At an externally input clock (CLK) timing, a predetermined set value is added by a cumulative adder. Then, addressing is performed based on the output value, a value of sin / cos is output, and a desired sin (sine) wave and cos (cosine) wave are generated. The frequency of the output signal is determined by the clock and the number of bits of the accumulator. That is, the set value and resolution of the DDS are obtained by the following equations (1) and (2), respectively. Setting value = output frequency × 2 ^{(number of bits of cumulative adder)} / input clock (2) resolution = input clock / 2 ^{(number of bits of cumulative adder)} (2) As apparent from the above equations (1) and (2), it is necessary to lower the input clock or increase the number of bits of the accumulator in order to improve the resolution. On the other hand, when the input clock is reduced, the maximum output frequency is reduced. Further, when the number of bits of the accumulator is increased, the operable frequency is reduced to reduce the input clock. [0006] In the case of a currently used DDS, a typical low-cost IC (semiconductor integrated circuit) has a maximum of 32 bits. Although there are some having more bits than this, they are not practical because they are extremely expensive and increase the number of peripheral circuits. Accordingly, an object of the present invention is to provide a DDS device which improves the resolution of an output frequency without increasing the number of bits of an input clock and an accumulator. [0008] In order to solve the above-mentioned problems and to achieve the above-mentioned object, the DDS device of the present invention has the following features. That is, DDS for inputting a DDS set value to DDS
By inputting two integer DDS setting values closest to the desired output frequency to the DS setting unit, and alternately switching these two DDS setting values at a ratio based on the deviation between the two DDS setting values and the desired output frequency, An output frequency corresponding to an intermediate value between the two DDS setting values is obtained. As a result, the resolution can be improved without increasing the number of DDS bits. Ingredient
Specifically, an integer DDS input by the DDS setting unit
Generates a signal of a predetermined frequency according to the set value and input lock.
In the DDS equipment including the generated DDS,
Register and B register that output the number of DDS setting values
And a counter for counting up in response to the input clock.
Counter and the count value of the counter and the A register.
DDS setting values are compared, and when they match, the DDS setting unit
A first comparator for switching a DDS set value;
Counter value and DDS setting of the A and B registers
Compare the total count of the fixed value, and when the
And a second comparator that clears
Prepare . DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of a DDS device according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram of a preferred embodiment of a DDS device according to the present invention. This DDS device is a DD
S1, DDS setting unit 2, comparator (comparator) 3,
5, counter 4, A register 6, B register 7, A count 8, (A + B) count 9, DSP (Digital Signal Processor) or CPU (Central Processing Unit)
It consists of ten. The DSP / CPU 10 has an A register 6,
The signal S12 is inputted to the register 7, the A count number 8 and the (A + B) count number 9. And these A
Register 6, B register 7, A count number 8 and (A
+ B) For the count number 9, the setting values S8 and S9 and the section numbers S10 and S11 are set, respectively. Set value S8, S
9 is input to the DDS setting unit 2. In addition, the number of sections S1
0 and S11 are input to the comparators 3 and 5, respectively. The counter 4 counts up upon receiving the input clock S2, and outputs the output values S5 and S6 to the comparators 3 and 5, respectively. Output value S6 from counter 4
Is compared by the comparator 5 with the section number S11 held in the (A + B) counter number 9, and when they match, a counter clear signal S7 is input to the counter 4 to clear the counter 4. On the other hand, the output value S5 of the counter 4
Is the same as the output value S6 described above, and the A count number 8
Is compared with the number of sections S10 held in. S5 and S
When 10 matches, the comparator 3 outputs a selection signal S4 to the DDS setting unit 2. Therefore, the DDS setting section 2 sets the selection signal S4
In response to the above, the set value S8 from the A register 6 and the set value S9 from the B register 7 are switched, the DDS set value S3 is selected and input to the DDS1, and the frequency of the output signal S1 of the DDS1 is set. As described above, the setting resolution of the DDS1 is improved by switching and setting the set values S8 and S9 from the registers 6 and 7 for each set section. Here, DDS1 and DSP / CPU1
Since 0 itself is well known and does not directly relate to the gist of the present invention, a detailed description thereof will be omitted. Also, counter 4
Since the comparators 3 and 5 also have the conventional configuration, detailed description is omitted. Since the counter 4 counts up from 0, the set values of the counts 8 and 9 are set to (the actual count minus 1). Next, the operation of the DDS device of FIG. 1 will be described based on a specific example. Here, DDS1 is 32 bits,
The input clock S2 is 40 MHz, and the frequency of the output signal S1 is 10.7 MHz. In addition, the system required deviation is set to 1
It is assumed that the frequency is less than mHz. The setting formula in DDS1 is shown in the above formulas (1) and (2). The resolution is 9.313 mHz. The set value is 10.7MHz × 232 / 40MHz = 1148903
751.68. In order to set an integer in DDS1, 1148903752 is set in DDS1. In the case of this set value, the possible output frequency is 10700000.2988
023 Hz, giving a deviation of about 3 mHz. Also,
In the case of 1148903751, the outputtable frequency is 1
069999.9999366 MHz, about 6 mHz
Produces a deviation of As is apparent from this, when the two set values are independently set, it is impossible to satisfy the required deviation of 1 mHz or less. Accordingly, 1 clock of the input clock S2 is set as a minimum unit and 1148903
The output frequency when the set value of 751 is switched every 8 clocks and the set value of 1148903752 every 17 clocks is 107000000000000000Hz.
The reason is as follows: (1148903751 × 1148903752 × 17) / (8 + 17) = 1 148903751.68 (3), and it is possible to set an integer other than an integer which cannot be set conventionally, that is, a decimal place. When the above principle is applied to the DDS apparatus of FIG. 1, the following is obtained. That is, 1148 is stored in the A register 6.
903751 is set. 114890 in B register 7
3752 is set. In addition, A count number 8 becomes (8-
1) = 7 is set, and (8 + 1) is added to (A + B) count number 9
7-1) = 24 is set. Then, the above-described two frequencies are alternately switched and output, whereby the output signal S
The frequency of 1 can be a frequency that satisfies the required deviation. As described above, according to the DDS apparatus of the present invention, two integers which are closest to the desired frequency and are higher and lower than the desired frequency are used as the set values, and the two frequencies based on these set values are determined based on the input clock. By alternately switching the ratio, the DDS setting resolution can be improved. If the set value for generating the desired frequency is not divisible, the A count number 8 and (A
+ B) It can be easily understood by those skilled in the art that the required deviation can be satisfied by setting the optimum value for the count number 9. The preferred embodiment of the DDS apparatus of the present invention has been described above in detail. However, the present invention should not be limited to only such specific examples, and various modifications can be made in accordance with specific applications. For example, in Embodiment 2 of FIG. 1, two set values are switched by a counter and two comparators.
The set value may be switched by counting the number of sections with two counters. In the embodiment of FIG. 1, the circuit blocks 2 to 9 are configured by hardware,
When the / CPU operates faster than the input clock,
The processing may be performed by software. Consider a case where the number of the counter 4, the A count number 8 and the B count number 9 are increased. For example, A count 8 is 1000 clocks, (A + B)
When the count number 9 becomes 2999 clocks, the frequency of the B register 7 is output for a maximum of 1999 clocks. Here, α is a set value of the A register 6,
If β is the set value of the B register 7, (α × 10 clocks + β × 20 clocks) + (α × 10 clocks + β × 19
The same result can be obtained even when output as a clock. In this case, looking at the frequency on the time axis, the A count number 8 is 1000 clocks, and the (A + B) count number 9 is 2999.
Better results can be obtained than when outputting as a clock. As is clear from the above description, according to the DDS apparatus of the present invention, the set values of the integers corresponding to the upper and lower frequencies of the desired frequency are alternately switched at a predetermined ratio.
Without using an expensive DDS having a large number of bits, it is possible to equivalently obtain a high-resolution output frequency corresponding to a decimal number between both integer values. The configuration added for that purpose is a counter, a register, a comparator, and the like, and is relatively simple.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a preferred embodiment of a DDS device of the present invention. [Description of Signs] 1 DDS (Direct Digital Frequency Synthesizer) 2 DDS setting unit 3, 5 Comparator 4 Counter 6, 7 A and B register 8 A count 9 (A + B) count 10 DSP / CPU

Claims (1)

(57) [Claims] 1. An integer DD input by a DDS setting unit
A signal of a predetermined frequency is set according to the S set value and input lock.
In the DDS device including the generated DDS, the A register and the A register which output different integer DDS setting values respectively.
And B register, and a counter that counts up upon receiving the input clock
And the count value of the counter and the DDS setting of the A register
Compare the values, and when they match, set the DDS of the DDS setting unit
A first comparator for switching a value, a count value of the counter, and a value of the A and B registers.
Compare the total count number of DDS set value,
A direct digital frequency synthesizer comprising: a second comparator for clearing a counter .