JP3513809B2 - Pulse encoding type A / D converter - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an A / D (analog
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital encoder, and more particularly to a pulse-encoded A / D converter of a type in which conversion data is sequentially input to a pulse encoder while switching reference voltage trains for comparing voltage levels with analog signal inputs.

[0002]

Digital technology has various advantages over analog technology. Therefore, many conventional analog signal processes are digitized. As an indispensable technique for such digitization, there is an A / D converter that converts an analog signal into a digital signal or data having a predetermined bit. As the frequency of the analog signal to be digitized becomes higher, the A / D converter is becoming faster and more accurate. A conventional A / D converter is disclosed in, for example, JP-A-61-810.
It is disclosed in the "A / D converter" of Japanese Patent No. 30. This conventional A / D converter includes a sample-hold circuit for sampling and holding an input signal, a variable gain subtracting amplifier for inputting the output of the sample-hold circuit, and an nth power of 2 for dividing a positive / negative reference voltage. Quantized the output voltage of the subtraction amplifier, including (2 n + 1) comparators (voltage comparators) for comparing the output voltage of the subtraction amplifier and the reference voltage divided by the resistors Parallel quantizing means, D / A converting means for switching the reference voltage according to the output of the parallel quantizing means, and obtaining an analog voltage corresponding to the quantized value of the parallel quantizing means, and the D / A conversion. Circuit means for applying the output of the means to the input side of the subtraction amplifier to perform the quantized subtraction, then for switching the gain of the subtraction amplifier, and repeating the operation for a predetermined number of times. .

[0003]

However, such a conventional A / D converter has various problems to be solved as follows. First, the A / D converter including the conventional subtraction amplifier has a low operation speed. The reason is that it takes time to switch the gain of the subtraction amplifier using a gain changeover switch, a reference voltage changeover switch, and the like, and the comparison operation is required to be repeated for these quantizations. Secondly, the power consumption increases. The reason is that an n-bit A / D converter requires (2 n + 1) comparators, flip-flops and complicated control logic circuits. Third, the structure becomes complicated. The reason is that, in addition to the above-mentioned comparator and flip-flop, several times as many switches are required.

[0004]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to enable a high speed operation as compared with a conventional A / D converter with a built-in subtraction amplifier without interposing a switch operation in the process of comparing an analog input voltage and a reference voltage. And to provide a pulse-encoding A / D converter with a relatively simple circuit configuration and low power consumption.

[0005]

A pulse-encoded A / D converter according to the present invention has a quantization bit number N of an AD converter.
On the other hand, a reference voltage generator that generates M reference voltage strings defined by 1 <M ≦ 2N, an analog multiplexer that sequentially outputs the reference voltage from the reference voltage generator, and an output of the analog multiplexer. analog input signal voltage from the sample hold circuit is input, pre
When the analog input signal voltage exceeds the reference voltage
A pulse encoder that inverts and outputs a 1-bit signal each time it exceeds, a shift register that performs serial / parallel conversion of the output of the pulse encoder, and a table conversion of the output from the shift register into digital data corresponding to an input value And a code conversion table.

The pulse encode type A / D of the present invention
According to a preferred embodiment of the converter, the reference voltage generator is
It is a reference voltage generation resistance network including N reference voltage trains each including a plurality of series resistors and connected between a reference voltage upper limit value and a reference voltage lower limit value. The pulse encoder is composed of a plurality of transistor pairs each connected to a current source. Also, the output terminals of the plurality of transistor pairs are
The pair of load resistors are alternately connected and inverted. An analog signal input from a sample hold circuit is commonly input to one input terminal of a plurality of transistor pairs forming a pulse encoder, and a plurality of different reference voltages from N reference voltage strings are input to the other input terminal. To be done. The analog multiplexer and shift register are controlled by the control signal from the timing controller.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of a pulse-encoded A / D converter according to the present invention will be described in detail below with reference to the accompanying drawings.

First, FIG. 1 is a block diagram showing the overall configuration of a preferred embodiment of a pulse encode type A / D converter according to the present invention. This pulse-encoded A / D converter includes a reference voltage generating resistor network (reference voltage generator) 1, a timing controller 2, an analog multiplexer 3, a sample hold circuit 4, a pulse encoder 5, a comparator (voltage comparator) 6, and a shift. Register (serial / parallel) conversion 7 and N-bit code conversion table 8
It is composed of

FIG. 2 shows a pulse encoder type A shown in FIG.
1 shows a detailed configuration of a reference voltage generating resistor network 1 which is one element of the / D converter. The reference voltage generating resistor network 1 constitutes N reference voltage trains of M (M ≧ N) voltage dividing resistors connected in parallel between the reference voltage upper limit value and the reference voltage lower limit value.

Further, FIG. 3 shows a detailed configuration of the pulse encoder 5 which is one element constituting the pulse encoder type A / D converter of FIG. The pulse encoder 5 is composed of M transistor pairs whose emitters are connected to the constant current source Ic and load resistors RL1 and RL2 (resistance value RL). The analog input signal level sampled and held by the sample and hold circuit 4 and the N reference voltage sequences that are applied while being switched are input, and a pulse encode signal is output from the load resistors RL1 and RL2.

Next, FIG. 4 is a timing chart showing the switching of the reference voltage sequence, the output of the pulse encode signal, and the output timing of the N-bit code signal with respect to the sample hold timing of the analog input signal. 4, (a) is an analog input signal, (b) is a clock signal, (c) is a sample hold signal, (d) is held data, (e) is a reference voltage train, and (f) is a pulse. The encode signal and (g) are N-bit code signals.

FIG. 5 is a pulse encode type A shown in FIG.
Comparator 6 which is one element that constitutes the / D converter
6 is a waveform diagram showing a state in which the level of the pulse encode signal output from the pulse encoder 5 is converted into a digital code signal. FIG. 5A shows a pulse encode signal waveform, and FIG. 5B shows a converted digital code signal.

Next, the operation of the pulse encode type A / D converter according to the present invention will be described with reference to FIGS. 1 to 5. As shown in FIG. 2, the reference voltage generating resistor network 1 of FIG. 1 divides the upper limit value and the lower limit value of the reference voltage by NM (M ≧ N) resistors, and includes the upper limit value and the lower limit value (2 Nth power + 1) reference voltage values are generated. The voltage dividing resistors are divided into N resistor groups, and each resistor group has M reference voltages N (1) to N (M).
Generate a reference voltage train having. The reference voltage of each of these voltage trains is set in advance so that when input together with the analog input voltage value to the pulse encoder 5 described later, a pulse encode signal unique to the analog input value is output. The N reference voltage trains are input to the analog multiplexer 3, and the voltage trains to be output are sequentially selected by the switching signal from the timing controller 2. The reference voltage sequence selected by the analog multiplexer 3 is input to the pulse encoder 5.

The pulse encoder 5 is an M encoder as shown in FIG.
The collector side of each transistor pair is alternately connected to two load resistors RL1 and RL2 connected to the power supply Vcc. The M reference voltages forming each reference voltage string are the left side transistors (Tr1, Tr3, T) of each transistor pair.
It is input to the base of r5, ..., Tr2M-1). The analog input signal is sampled and held by the sample and hold circuit 4 by the sample and hold signal output from the timing controller 2 of FIG.
Is sampled and held by. The sampled analog input signal level is the right side transistor (Tr
2, Tr4, Tr6, ..., Tr2M) and all the reference voltage strings are input to the transistor pair,
The value is held until the comparison operation is completed.

As shown in the timing chart of FIG. 4, the pulse encoder 5 outputs a pulse encode signal every time the reference voltage sequence is switched. A pair of load resistors RL having the same resistance value as the pulse encode signal level.
1 becomes the difference between the voltage values input to RL2 and that value causes the transistor to turn on the constant current Ic as shown in FIG.
If it is the current of time, it becomes either RLIc or -RLIc. This signal level is converted into a digital signal by the comparator 6 of FIG. 1 using the "0" level as a threshold value, RLIc becomes a code signal having an "H" level, and -RLIc becomes a code signal having an "L" level, and a reference voltage string. Are continuously output for N switching times. These N-bit code signal outputs are output by the shift register 7
Parallel conversion is performed in synchronization with the clock signal output from the timing controller 2. The obtained N-bit parallel signal is converted into data corresponding to the input level by the N-bit → N-bit code conversion table 8 and becomes output data.

Next, a specific example of the pulse encoder type A / D converter of the present invention will be described with reference to FIGS. FIG. 6 is a block diagram showing the overall configuration of the pulse encoder type A / D converter according to the present invention when N = 4. The constituent elements in the specific example of the pulse encode type A / D converter are a reference voltage generating resistor network 61, a timing controller 62, an analog multiplexer 63,
Sample hold circuit 64, pulse encoder 65, comparator 66, shift register 67 and 4 bits →
It is a 4-bit code conversion table 68.

FIG. 7 is a pulse encode type A shown in FIG.
A specific configuration of the reference voltage generating resistor network 61 in the / D converter is shown. The reference voltage generating resistor network 61 constitutes four reference voltage trains each including five (and four) reference resistors connected in series. These four reference voltage strings are connected between the reference voltage upper limit value and the reference voltage lower limit value.

Next, FIG. 8 shows a specific structure of the pulse encoder 65 in the pulse-encoded A / D converter shown in FIG. The pulse encoder 65 includes four transistor pairs each having an emitter connected to the constant current source Ic, and a pair of load resistors RL41 and RL42 (resistance value = R
L). The analog input signal level sampled and held by the sample and hold circuit 64 and the four reference voltage sequences that can be switched are input, and pulse encode signals are output from the load resistors RL1 and RL2.

FIG. 9 is a timing chart showing the switching of the reference voltage sequence, the output of the pulse encode signal, and the output timing of the 4-bit digital signal with respect to the sample hold timing of the analog input signal. Figure 9
, (A) is an analog input signal, (b) is a clock signal, (c) is a sample hold signal, (d) is hold data, (e) is a reference voltage sequence, (f) is a pulse encode signal and (g). ) Is a 4-bit code signal (parallel signal).

FIG. 10 shows the analog input signal level (hold level) of each of the pulse encode signals 1 to 4 when the reference voltage trains 1 to 4 are applied to the pulse encoder 65.
3 is a timing chart showing a state of change with respect to and output data after code conversion. In FIG.
(A) is the pulse encode signal 1, (b) is the pulse encode signal 2, (c) is the pulse encode signal 3,
(D) is a pulse encode signal 4, (e) is a 4-bit code signal, and (f) is output data.

FIG. 11 is a pulse decoding type A shown in FIG.
The block diagram of an example of the 4-bit-> 4-bit code conversion table 68 which is a component of a / D converter is shown. The code conversion table 68 includes four EX-OR (exclusive OR) gates 70a to 70 to which a 4-bit signal is input.
d, three OR (logical sum) gates 71a to 71c and two EX-OR gates 72 connected to the output side thereof.
a, 72b, an EX-OR gate 73 and a 3-input AND (logical product) gate 74 connected to the output side thereof, and two EX-OR gates 75a connected to their output sides to output output data, It is composed of 75b.

The reference voltage generating resistor network 61 shown in FIG.
As shown in FIG. 7, the upper and lower limit values of the reference voltage are divided by 20 resistors to generate 16 reference voltage values including the upper and lower limit values. These voltage dividing resistors are divided into four resistor groups to generate four reference voltage trains. These are input to the analog multiplexer 63 in FIG. 6, and the voltage train to be output is sequentially selected by the switching signal output from the timing controller 62 in FIG. The selected reference voltage train is the pulse encoder 6 shown in FIG.
Input to 5. This pulse encoder 65 is connected between the collector of five transistor pairs and the power supply Vcc.
The pair of load resistors RL41 and RL42 are alternately connected.

The transistors connected to one load resistor RL41 are Tr1, Tr4, Tr5, Tr8 and T.
r9 and the transistors connected to the other load resistor RL42 are Tr2, Tr3, Tr6, Tr7 and T.
r10. The three to five reference voltages forming the four reference voltage trains are on the left side (Tr1, Tr) of each transistor pair.
3, Tr5, Tr7 and Tr9). The analog input signal is sampled by the sample hold 64 by the sample hold signal output from the timing controller 62 of FIG. The sampled analog input signal level is the right side (Tr2, Tr4, Tr6, Tr8) of each transistor pair of the pulse encoder 65.
And Tr10) and all the reference voltage strings are input to the transistor pair, and the value is held until the comparison operation is completed.

The pulse encoder 65 outputs a pulse encode signal (f) every time four reference voltage trains are switched, as shown in (e) of the timing chart of FIG.
FIG. 10 shows the relationship between the analog signal input level held when each reference voltage is input and the pulse encode signal. The reference voltage sequence 1 (voltages 11 to 15) is composed of reference voltages of V, 5V, 11V, and 15V, where V is a voltage value that divides the difference between the upper limit value and the lower limit value of the reference voltage into 16 equal parts. When this reference voltage sequence is input to the pulse encoder 65 of FIG. 8, the relationship between the analog input level (Ain) and the pulse encode signal extracted from the transistor (or collector) side of the load resistors RL41 and RL42 is as follows.

(When Ain <V) O is applied to the load resistance RL41.
Transistors for passing N current are Tr1, Tr5, Tr9.
Therefore, the transistors that pass the ON current through the load resistor RL42 are Tr3 and Tr7. In this case, the pulse encode signal level is -RLIc (“L” after conversion).
Level).

(When V ≦ Ain <5V) Load resistance RL4
The transistors that pass the ON current to 1 are Tr5 and Tr.
The transistors for which the ON current flows through the load resistor RL42 are Tr2, Tr3, and Tr7. In this case, the pulse encode signal level is RLIc (“H” level after conversion).

(When 5V ≦ Ain <11V) Load resistance R
Transistors that pass ON current to L41 are Tr4 and Tr.
Transistors 5 and Tr9, and transistors that pass an ON current to the load resistance RL42 are Tr2 and Tr7. In this case, the pulse encode signal level is -RLIc.
(“L” level after conversion).

(In the case of 11V≤Ain <15V) Transistors for supplying ON current to the load resistor RL41 are Tr4 and Tr9, and transistors for supplying ON current to the load resistor RL42 are Tr2, Tr6 and Tr7. In this case, the pulse encode signal level is RLIc.
(“H” level after conversion).

(In the case of 15V ≦ Ain <16V) Transistors for flowing an ON current to the load resistor RL41 are Tr4, T
The transistors that are r8 and Tr9 and flow an ON current through the load resistor RL42 are Tr2 and Tr6. In this case, the pulse encode signal level is -RLI.
c (“L” level after conversion).

As described above, the pulse encode type A according to the present invention
The configurations and operations of the preferred embodiments and specific examples of the / D converter have been described in detail. However, such an embodiment is merely an example of the present invention and does not limit the present invention in any way. Those skilled in the art can easily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention.

[0031]

As can be understood from the above description, the pulse decoding A / D converter of the present invention has various practically remarkable effects as follows. First, the A / D conversion operation can be speeded up. The reason is that in the conventional A / D converter with a built-in subtraction amplifier, when the analog input signal is quantized, the comparison operation is performed at each stage of the quantization by the gain changeover switch and the reference voltage changeover switch.
This is because the pulse encode type A / D converter of the present invention can obtain information (encoded signal sequence) regarding digital conversion data of the analog input voltage value by switching the reference voltage sequence N times.

Secondly, the power consumption can be greatly reduced. The reason is that in the case of the conventional N-bit A / D converter,
(2 N + 1) comparators, flip-flops and complex control logic circuits were required. However, the pulse encode type A / D converter of the present invention has the following configuration. The power consumption reduction amount is roughly as follows. As a reference for comparison, if the power consumption of the subtraction amplifier which is conventionally incorporated is set to 50 and each component is represented by a relative value, it is possible to reduce the power consumption by about 40%. Components Conventional A / D converter A / D converter of the present invention-Reference voltage generator 10 10-Subtraction amplifier 50-Analog multiplexer-20-Sample hold 50 50-Comparator 80 or higher 10-Flip-flop 160 or higher- -Pulse encoder-90-Timing controller-120-Shift register-40 or more-Control logic circuit 300-Code conversion table-50 Total 650 or more 390 or more

Third, the circuit structure becomes simple. The reason is that a plurality of comparators, flip-flops, and switches, which are the constituent elements of the conventional A / D converter, are not necessary and can be replaced with one pulse encoder and one comparator.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a pulse encode type A / D converter according to the present invention.

FIG. 2 is a detailed configuration diagram of a reference voltage generating resistor network which constitutes the A / D converter shown in FIG.

FIG. 3 is a circuit diagram of a specific example of a pulse encoder that constitutes the A / D converter of FIG.

4 is a timing chart showing sample hold of an analog input signal, a pulse encode signal, and an output timing of an N-bit code signal in the A / D converter shown in FIG.

5 is an explanatory diagram of level conversion of a pulse encode signal into a digital code signal in the A / D converter shown in FIG.

FIG. 6 is a specific configuration diagram of a pulse-encoded A / D converter according to the present invention when N = 4.

7 is a specific configuration diagram of the reference voltage generating resistor network shown in FIG.

8 is a specific configuration diagram of the pulse encoder in FIG.

9 is an output timing chart of a sample hold of an analog input signal of the A / D converter shown in FIG. 6, a pulse encode signal, and a 4-bit code signal.

10 is a diagram illustrating a relationship between a pulse encode signal, a 4-bit code signal, and output data of the A / D converter shown in FIG.

11 is a specific configuration example of a 4-bit → 4-bit code conversion table of the A / D converter shown in FIG.

[Explanation of symbols]

1, 61 Reference voltage generator (reference voltage generating resistor network) 2, 62 Timing controller 3, 63 Analog multiplexer 4, 64 Sample and hold circuit 5, 65 Pulse encoder 6, 66 Comparator 7, 67 Shift register 8, 68 Code conversion table

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Claims (6)

(57) [Claims] 1. A 1 for a quantization bit number N of an AD converter.
A reference voltage generator that generates M reference voltage strings defined by <M ≦ 2N and a reference voltage from the reference voltage generator are sequentially arranged.
An analog multiplexer that following switching output, analog input signal voltage from the output and the sample hold circuit of the analog multiplexer is input, the analog
1-bit signal when the input signal voltage exceeds the reference voltage
Pulse encoder that inverts and outputs every time the number of signals exceeds, a shift register that performs serial / parallel conversion of the output of the pulse encoder, and code conversion that performs table conversion of the output from the shift register into digital data corresponding to the input value. A pulse-encoded A / D converter comprising a table. 2. The reference voltage generator is a reference voltage generation resistor network including N reference voltage trains each including a plurality of series resistors and connected between an upper limit reference voltage and a lower limit reference voltage. The pulse encode type A according to claim 1.
/ D converter. 3. The pulse encode type A / D converter according to claim 1, wherein the pulse encoder is composed of a plurality of transistor pairs each connected to a current source. 4. The output terminal of the plurality of transistor pairs is 1
The pulse encoding A / D converter according to claim 3, wherein the pair of load resistors are alternately inverted and connected. 5. An analog signal input from the sample-hold circuit is commonly input to one input terminal of the transistor pair forming the pulse encoder, and the other input terminal receives the analog signal input from the N reference voltage trains. The pulse encode type A / D converter according to claim 3 or 4, wherein a plurality of different reference voltages are input. 6. The pulse encode type A / D converter according to claim 1, wherein the analog multiplexer and the shift register are controlled by a control signal from a timing controller.