JP3514686B2 - Digital satellite receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital satellite broadcast receiver, and more particularly to a digital satellite broadcast receiver that receives site diversity based broadcasts.

[0002]

2. Description of the Related Art In digital satellite broadcasting, when it is predicted that one of the operating uplink broadcasting stations will not be able to secure a line due to rainfall or the like, site diversity is switched to operation by another uplink broadcasting station. Is adopted. In this site diversity, it is desirable to minimize the effect of interruptions in video and audio due to switching of uplink broadcasting stations.

In this specification, switching from one uplink broadcasting station in operation to operation by another uplink broadcasting station is referred to as switching of a site.

Therefore, the site diversity method proposed in the digital satellite broadcasting has a problem that a freeze occurs in the digital satellite broadcasting receiver at the time of switching the site so that the video and the audio by the switching are not interrupted as much as possible. In order to make the mute as inconspicuous as possible, it has been proposed to switch sites within the superframe.

Specifically, the extension area (1 to 4 bits) shown in FIG. 5 (a) in the transmission / reception control information in the TMCC information is used, and a bit for site diversity execution superframe instruction is set in bit 4 thereof. (Bit 4 =
1), after the bit is raised, as shown in FIG.
(N = 16) Performs site diversity in the superframe after the superframe, and after performing site diversity, bit 4 in the M (M = 0) superframe
Is set to the lower bit (bit 4 = 0).

In order to cope with the above-mentioned site diversity, the demodulation section of the digital satellite broadcast receiver, as shown in FIG. 6, corresponds to the modulation system based on the modulation system identification signal (A1, A0) and the carrier reproduction phase. According to the carrier reproduction phase error table selected from the error table 8,
The phase error voltage based on the received phase error with respect to the detected baseband signal is obtained, the phase error voltage is supplied to the carrier filter 9A composed of a digital filter, and the output from the carrier filter 9A is supplied to the AFC circuit 10 for cumulative addition. , The oscillating frequency of the numerically controlled oscillator 11 is controlled by the cumulative addition value, the output from the numerically controlled oscillator 11 is supplied to the arithmetic circuit 1 as a reproduction carrier, and the reproduction carrier and the quasi-synchronous detected signal input to the arithmetic circuit 1 are supplied. The quasi-coherent detection output is demodulated by multiplying the baseband signals I and Q which are

The detection output output from the arithmetic circuit 1 is band-limited by the roll-off filter 2, the frame synchronization pattern W1 is detected in the frame synchronization circuit 31 from the band-limited detection output, and TMCC information is extracted and extracted. T
The MCC information is supplied to the TMCC decoder 32 for decoding, the extracted TMCC information is supplied to the site diversity control circuit 33, and the site diversity control circuit 33 gives an instruction to execute site diversity based on bit 4 in the extension area. It detects whether or not it is done.

When it is detected that an instruction to execute the site diversity is issued, the site diversity control circuit 33
In each case, the N value is counted down every time the superframe is detected, and when the N value reaches 0, that is, when the superframe reaches N = 0, the execution instruction signal is supplied to the frame synchronization circuit 31, and the execution instruction signal is output. The received frame synchronization circuit 31 performs detection until the frame synchronization pattern W1 is detected in accordance with the execution instruction signal, and if detected, resynchronizes with the frame synchronization pattern W1.

[0009]

However, according to the above-mentioned proposed site diversity method, the site is switched somewhere in the superframe, and the site is switched somewhere in the superframe. There is a problem that it is unclear whether or not will be performed.

Further, when the sites are switched, a carrier frequency shift and a clock phase shift between the main station and the sub station are assumed, and further a frame cycle shift, for example, a shift of about 5 msec before and after switching. Therefore, there is a problem that the image is disturbed and the sound is interrupted due to this shift.

Further, according to this method, the site switching is switched somewhere within the superframe, and at the instant of this switching, the carrier frequency, clock phase,
Due to the shift of the frame period and the like, the system lock is once released in the digital satellite broadcasting receiver, and resynchronization must be performed. Since it is indefinite in one superframe where to switch to in the superframe, resynchronization causes system lock at least in the next superframe, which is the shortest period.

Therefore, the data in the super frame at the moment the site is switched cannot be reproduced, and for example, an error occurs in the image data in the digital satellite broadcast receiver, the image is disturbed, and the voice is interrupted. Dots occur.

An object of the present invention is to provide a digital satellite broadcast receiver which can resynchronize quickly when switching sites.

[0014]

A digital satellite broadcasting receiver according to claim 1 of the present invention detects a predetermined number of superframes after a site diversity execution instruction, and detects a final slot in the detected superframes. Detects dummy data in a frame that is dummy data, uses an 8PSK modulated signal reception method for carrier reproduction in a frame synchronization pattern section in a frame immediately after the detected dummy data, and performs absolute phase conversion in the frame synchronization pattern section. And performing the carrier reproduction by setting the loop gain of the carrier reproduction loop to the gain for high-speed acquisition, and then setting the loop gain of the carrier reproduction loop to the gain at the time of normal reception.

According to the digital satellite broadcast receiver of the first aspect of the present invention, the 8PSK modulation system is used for the carrier reproduction in the frame synchronization pattern section following the dummy data whose sites are switched, and the carrier reproduction loop is used. Since the loop gain of is set to the gain for high-speed acquisition, carrier regeneration is performed quickly, and synchronization is achieved by the frame synchronization pattern following the dummy data where site switching is performed, and resynchronization is performed at the shortest time. Therefore, no error occurs in the image data, the image is not disturbed, and sound interruption does not occur.

A digital satellite broadcast receiver according to a second aspect of the present invention is the digital satellite broadcast receiver according to the first aspect, in which the TMCC information is changed from when the gain of the carrier reproduction loop is set to the gain at the normal reception. It is characterized in that the modulated signal is received according to the reception method.

According to the digital satellite broadcast receiver of the second aspect of the present invention, the reception of the modulated signal based on the TMCC information for each reception system from the time when the gain of the carrier reproduction loop is set to the gain at the time of normal reception, That is, the normal reception state is restored.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION A digital satellite broadcast receiver according to the present invention will be described below with reference to embodiments.

FIG. 1 is a block diagram showing a configuration of a demodulation section of a digital satellite broadcast receiver according to an embodiment of the present invention.

Prior to the description of the digital satellite broadcast receiver according to the embodiment of the present invention, the site switching proposed by the applicant will be described.

FIG. 3A is a schematic diagram showing the structure of one superframe in digital satellite broadcasting.

In the layered broadcasting system, one superframe is composed of eight frames as shown in FIG. 3 (a), and each frame has a frame synchronization pattern W1, TMCC (transmission multiplex) as illustrated in FIG. 3 (b). (Configuration control) information, frame identification synchronization pattern W2 or W3 for identifying whether or not it is the first frame in the superframe, main signal,
The reference burst signal, the main signal, the burst signal, ..., The main signal and the burst signal. The first frame in the super frame has a frame identification synchronization pattern W.
2, the frame identification synchronization pattern W3 is used for 2 to 8 frames. It should be noted that FIG. 3B shows the second frame.

The main signal is a modulation type trellis code 8PS
K, QPSK or BPSK, frame synchronization pattern W1, frame identification synchronization patterns W2, W3, T
The MCC information and the reference burst signal are BPSK,
The frame synchronization pattern W1 and the frame identification synchronization patterns W2 and W3 each have 32 symbols (including 20 symbols of fixed bits), TMCC information has 128 symbols, main signal has 203 symbols, and burst has 4 symbols. One frame is composed of 39936 symbols.

According to the embodiment of the present invention, when it is desired to switch the uplink broadcasting station, a bit is set in bit 4 of the extension area shown in FIG. 5 in the transmission / reception control information in the TMCC information and set in bit 4 of the extension area. The site switching is performed from the time when the bit is set, that is, from the time when the site switching execution instruction signal is received, during the superframe when the superframe is counted 16 times.

The site switching in the superframe is performed by detecting a frame in which the final slot is dummy data from the superframe in which the site is switched, and determining the final slot of the frame detected as dummy data. In the transmission / reception control information in the TMCC information, bit 3 of the extension area indicated by (xxx) in FIG.
By designating the frame whose site has been switched by using 3 bits from 1 to 3, the frame information whose site has been switched is included in the TMCC information.

In this case, the information of the frame whose site has been switched is changed from the bit 3 to the bit 1 of the extension area shown in FIG. 3 in the transmission / reception control information in the TMCC information to the extension information in the TMCC information. It is also possible to use 3 bits in the extension area of the above and include it in the TMCC information.

On the other hand, the transmission method (coding rate) and the number of effective slots / the number of transmission slots in the hierarchical transmission are shown in FIG.
It is as shown in (a). Here, the transmission slot is the minimum number of slots for transmission, and the effective slot is the number of slots in the transmission slot in which information can be transmitted.

As is clear from FIG. 4A, for example,
Slot number 1 to slot number 46 is TC8PS
Slot number 4 for transmission of K modulated signal
4 is for transmission of QPSK (1/2) modulated signal, slot number 1 to slot number 44 are for transmission of TC8PSK modulated signal and slot number When slot numbers 45 to 48 are for transmission of BPSK (1/2) modulated signal, it is as shown in FIG. 4C, and slot numbers 1 to 44 are for transmission of TC8PSK modulated signal. When the slot number 45 to the slot number 46 and the slot number 47 to the slot number 48 are for the transmission of the QPSK (1/2) modulated signal, it is as shown in FIG. 4 (d).

When the slot number 1 to the slot number 48 are TC8PSK modulated signals, the final slot is the slot number 48, and FIGS. 4 (b), 4 (c), 4
In FIG. 4D, the last slot is slot number 47 in FIG. 4B, slot number 45 in FIG. 4C, and slot number 47 in FIG. 4D. . When the last slot is dummy data, that is, when all are TC8PSK modulated signals, a frame including the slot number 48, which is dummy data, is detected, and the site is switched in the last slot of the frame. 4), a frame including this slot number 47 is detected, the site is switched in the last slot of the frame, and in the case of FIG. 4C, a frame including this slot number 45 is detected and the frame of this frame is detected. Site switching is performed in the last slot, and Fig. 4
In the case of (d), the frame including this slot number 47 is detected, and the site is switched in the last slot of the frame.

Returning to the demodulation section of the digital satellite broadcast receiver shown in FIG.

In the demodulation section of the digital satellite broadcast receiver shown in FIG. 1, the orthogonal reproduction carrier output from the numerically controlled oscillator 11 to the baseband signals I and Q is the arithmetic circuit 1.
And the baseband signals I and Q are demodulated. The demodulated baseband signals I and Q are supplied to the roll-off filter 2 and band-limited.

The baseband signals I and Q band-limited by the roll-off filter 2 are supplied to the absolute phase calculation circuit 6 and the remapper circuit 7. The absolute phase calculation circuit 6 obtains a phase difference signal based on the difference between the signal point arrangement of the baseband signals I and Q based on the reception phase of the frame synchronization pattern W1 and that on the transmission side, and the remapper circuit 7 determines the absolute phase calculation circuit 6 The signal point arrangement of the baseband signals I and Q is rotated by the remapper circuit 7 according to the phase difference signal in response to the phase difference signal obtained by Made to be identical to that of. The baseband signals I and Q passed through the remapper circuit 7 are supplied to the carrier reproduction phase error table 8.

On the other hand, the baseband signals I and Q band-limited by the roll-off filter 2 are supplied to the frame synchronization detection circuit 3, the frame synchronization pattern W1 is detected in the frame synchronization detection circuit 3, and the frame synchronization on the transmitting side is detected. When it is determined that the synchronization is achieved in agreement with the pattern W1, the signals A1 and A0 shown in FIGS. 3C and 3D generated from the TMCC information are the absolute phase calculation circuit 6 and the carrier reproduction phase. It is sent to the error table 8.

Here, when both the signals A1 and A0 have a low potential, the modulation method of the main signal is the 8PSK modulation method, and when the signal A1 has a low potential and the signal A0 has a high potential, the modulation method of the main signal. Is a QPSK modulation method, the signal A1 has a high potential and the signal A0 has a low potential, the main signal modulation method is a BPSK modulation method, and the signals A1 and A0 have a high potential, a burst signal. , And is supplied to the absolute phase calculation circuit 6 and the carrier reproduction phase error table 8 described later as a modulation method identification signal of the main signal.

In the absolute phase calculation circuit 6 which receives the signals A1 and A0, a phase difference signal is obtained based on the reception phase of the frame synchronization pattern W1 and output to the remapper circuit 7,
In the remapper circuit 7, the baseband signals I and Q are rotated by the angle based on the phase difference signal so as to have the same phase as the transmitting side.

The baseband signals I and Q matched with the phase on the transmission side in the remapper circuit 7 are supplied to the phase error table 8 for carrier reproduction. In the carrier reproduction phase error table 8, the phase error table corresponding to the modulation system identified based on the signals A1 and A0 is referred to,
A phase error voltage based on the phase error of the baseband signals I and Q is output from the phase error table 8 for carrier reproduction from the phase error table referred to based on the modulation method of the main signal.

The phase error voltage read from the carrier reproduction phase error table 8 is supplied to the AFC circuit 10 via a digital filter 9 forming a carrier reproduction loop filter composed of a low-pass filter, and its low-frequency component is supplied. The phase error voltage is taken out, and the phase error voltage through the digital filter 9 is sequentially accumulated and added in the AFC circuit 10.

The cumulative addition output from the AFC circuit 10 at each addition time point is supplied to the numerically controlled oscillator 11, and positive and negative sine wave data and positive and negative cosine wave data of the frequency based on the cumulative addition value are output. Here, the oscillation frequency of the numerically controlled oscillator 11 is changed by the output at the time of cumulative addition, and carrier reproduction is performed. Here, it is similar to AFC in the sense that the oscillation frequency of the numerically controlled oscillator 11 is changed, and is referred to as an AFC circuit 10.

In the arithmetic circuit 1, the numerically controlled oscillator 11
The positive sine wave data output from the baseband signal I
And the negative cosine wave data is multiplied by the baseband signal Q, and the multiplication results are added and output as the baseband signal Q. Similarly, the positive cosine wave data is multiplied by the baseband signal I, the negative sine wave data is multiplied by the baseband signal Q, and the multiplication results are added and output as the baseband signal I. In this way, the arithmetic circuit 1 demodulates.

On the other hand, in the frame synchronization detection circuit 3 which has received the band-limited baseband signals I and Q by the roll-off filter 2, the frame synchronization pattern W1 and the frame identification synchronization are supplied from the supplied baseband signals I and Q. The pattern W2 (W3) and TMCC information are detected. The detected TMCC information is sent to the TMCC decoder 4, decoded and held in the TMCC decoder.

When the TMCC decoder 4 detects that the site diversity execution instruction is given by the bit 4 in the extended area in the TMCC information, the site diversity control circuit 5 counts down the N value every time the superframe is detected and the N value is counted down. When the superframe becomes 0, an execution instruction signal is sent from the site diversity control circuit 5 to the frame synchronization detection circuit 3 and the digital filter 9.

In the frame synchronization detection circuit 3 which receives the execution instruction signal from the site diversity control circuit 5, N =
During the period of the frame synchronization pattern W1 of the frame following the final dummy data of the predetermined frame of the superframe which becomes 0, the absolute phase calculation circuit 6 and the carrier reproduction phase error table 8 are used for the modulation identification signal in the 8PSK modulation system. Send to. The digital filter 9, which has received the execution instruction signal from the site diversity control circuit 5, detects the frame synchronization pattern W1 of the frame following the final dummy data of the predetermined frame of the superframe with N = 0. The setting is changed from the setting for maintaining synchronization to a parameter for high-speed acquisition such as increasing the loop gain.

Next, the operation of the digital satellite broadcast receiver according to the embodiment of the present invention will be described with reference to the flowchart of FIG.

In the normal reception state, whether or not a bit is set in bit 4 of the extension area of the transmission / reception control information in the TMCC information is detected for each superframe to check whether or not a site switching instruction is detected. (Step S1). When it is determined that the site switching instruction is given, if the TMCC information is normally received, the TMCC information is held. At the time of normal reception, the TMCC information is held normally and the TMCC information is retained.

If it is determined in step S1 that a site switching instruction has been issued, the position of the frame in which site diversity is performed is detected (step S1).
2), it is counted down for each detected frame,
It repeats from step S2 until the N value reaches N = 0, and waits until N = 0 is reached (step S3).

The frame position where the site diversity is performed in step S3 is TMCC as described above.
Bit 3 to bit 1 in transmission / reception control information in the information
Information or the 3-bit information in the extension area in the extension information in the TMCC information, and counts down to N = 0 each time this frame position in the superframe is detected.

When it is determined that N = 0 in step S3, only carrier reproduction is set to the receiving method of the 8PSK modulated signal in the final slot of the frame when N = 0, and the frame synchronization state is reset. (Step S4).

Here, the reason why the 8PSK modulated signal reception system is set is as follows. When site diversity is performed, what is assumed for the modulated wave is a frequency shift and a phase shift. The frequency shift is determined by the performance of the transmission equipment and is known to be within about 1 kHz. On the other hand, the phase shift is indefinite. However,
As for the demodulation operation of the demodulation unit, considering the reproduction of the carrier within several tens of symbols, it is desired to minimize the phase shift and quickly eliminate the frequency shift. For this reason, the phase shift can be minimized by using the 8SK modulation signal reception method with many convergence points, rather than receiving the BPSK modulation section as the BPSK modulation signal reception method. Therefore, in step S4, 8P
The SK modulation signal reception system is set.

The frame synchronization detection circuit 3 resets the frame synchronization state. The frame synchronization detection circuit 3 checks the periodic frame synchronization pattern during frame synchronization, but detects the synchronization pattern after resetting the frame synchronization.

Following the reset of the frame synchronization state in step S4, the loop parameter for carrier reproduction in the digital filter 9 is set for high speed acquisition.
Normally, by increasing the gain of the digital filter 9, high-speed acquisition, that is, high-speed locking is achieved. Next, the process waits until the frame synchronization pattern W1 of the frame following the final dummy data of the frame detected in step S3 is detected (step S5).

In step S5, when the frame synchronization pattern W1 is detected, absolute phasing is performed in the section of the frame synchronization pattern W1 (step S6). When absolute phasing is performed, normal reception is subsequently resumed. .
That is, the remaining TMCC section is set to the data reception method of the BPSK modulation method, the loop gain setting in the digital filter 9 is set from the setting for high-speed acquisition to the normal reception, and the carrier reproduction is changed for each modulation method of the main signal. Change to receive.

After the carrier reproduction is changed to the reception of the main signal by the modulation method and the TMCC information is normally received, the normal reception state is established. That is, reception is performed for each modulation scheme based on TMCC information from when the gain of the carrier reproduction loop is set to the gain at the time of normal reception. In addition, it is determined whether the TMC information is normally received or not.
It is determined that the error correction by the Reed-Solomon error correction code as the outer code added to the C information is normally completed.

As described above, according to the digital satellite broadcasting receiver according to the embodiment of the present invention, the superframe information in which the site is switched from the TMCC information in the site diversity and the transmission / reception control in the TMCC information are performed. The frame information in the extension area in the information or the frame number (0 to 7) of which the site is switched is acquired from the frame information in the extension area in the extension information.

Since the frame synchronization pattern W1 always exists after the 48th slot, which is the last slot of the frame, upon receiving the frame information for switching the site, resynchronization can be performed in the frame synchronization pattern W1. it can. Therefore, only the last slot of the frame in which the site is switched cannot be normally received, and the disturbance of the image and the interruption of the sound can be minimized.

The dummy data is used for rate adjustment in a system in which the rate is fixed, such as digital satellite broadcasting, for the variation in the rate caused by digitizing and compressing the video signal, and at the receiver side. Even if it is not decoded correctly, it does not affect the decoding of broadcast contents.

[0056]

As described above, according to the digital satellite broadcast receiver of the present invention, synchronization is achieved by the frame synchronization pattern following the final dummy data in the predetermined frame in the superframe in which the site is switched. As a result, resynchronization can be performed in the shortest period of time, the image is not disturbed, and the sound is not interrupted.

Further, according to the digital satellite broadcast receiver of the present invention, the carrier reproduction is started as the receiving method of the 8PSK modulated signal in the frame synchronization pattern section immediately after the site switching, and the frame synchronization pattern is obtained. By determining the absolute phase in the section and performing carrier reproduction in the TMCC section immediately after that as a normal BPSK modulated signal reception method, a section with only 192 symbols of the frame synchronization pattern, TMCC information and frame identification synchronization pattern is detected. Carrier regeneration (convergence operation to the receiving point) can be performed at high speed and stably.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a demodulation unit of a digital satellite broadcast receiver according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the demodulation unit of the digital satellite broadcast receiver according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram of superframes and frames in digital satellite broadcasting.

FIG. 4 is an explanatory diagram showing allocation of transmission methods and slots in digital satellite broadcasting.

FIG. 5 is an explanatory diagram of operation of a TMCC information section for switching sites in digital satellite broadcasting.

FIG. 6 is a block diagram showing a configuration of a conventional digital satellite broadcast receiver.

[Explanation of symbols]

1 arithmetic circuit 2 roll-off filter 3 Frame sync detection circuit 4 TMCC decoder 5 Site diversity control circuit 6 Absolute phase calculation circuit 7 Remapper circuit 8 Carrier reproduction phase error table 9 Digital filter 10 AFC circuit 11 Numerically controlled oscillator

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-8-9190 (JP, A) JP-A-5-308253 (JP, A) JP-A-57-170633 (JP, A) JP-A-5- 336467 (JP, A) JP-A-9-331312 (JP, A) JP-A-11-163957 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04B 7/02 H04L 27 / 22 H04L 27/38

Claims (2)

(57) [Claims] 1. Immediately after detecting the dummy data in a frame in which the last slot is dummy data in the detected superframe, a predetermined number of superframes after the site diversity execution instruction are detected. The 8PSK modulation signal reception system is used for carrier reproduction in the frame synchronization pattern section of the frame, the absolute phase conversion is performed in the frame synchronization pattern section, and the loop gain of the carrier reproduction loop is set to the gain for high-speed acquisition. A digital satellite broadcast receiver characterized in that the loop gain of a carrier reproduction loop is set to the gain at the time of normal reception after performing carrier reproduction by using. 2. The digital satellite broadcasting receiver according to claim 1, wherein reception of a modulation signal based on TMCC information for each reception system is performed after the gain of the carrier reproduction loop is set to the gain at the time of normal reception. Characteristic digital satellite broadcasting receiver.