JP3515693B2 - Clock generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit for generating a clock having an arbitrary frequency. FIG. 2 is a schematic configuration diagram showing an example of a conventional clock generation circuit. This clock generation circuit
It has a phase comparator 1 that compares the phase of the input signal Si with the phase of the comparison signal S6a and outputs the output signal S1. On the output side of the phase comparison unit 1, a filter unit 2 that smoothes the output signal S1 and outputs an output signal S2 is connected. The output terminal of the filter unit 2 is connected to an input terminal of a 1-input / n-output switching unit 3 that receives the output signal S2 and outputs the output signal S2 to one of the n output terminals. .., S4-n having different frequencies based on the voltage of the output signal S2.
, 4-n are connected to each other. Oscillator 4-
, 4-n are provided with output signals S4-1, S4-1.
, S4-n, and an n-input / one-output switching unit 5 for outputting an output signal S5 by selecting one of them is connected. The output terminal of the switching unit 5 is connected to a frequency dividing unit 6 that divides the output signal S5 by an arbitrary value and outputs a comparison signal S6a and an output signal S6b. Next, the operation of the clock generation circuit shown in FIG. 2 will be described. In this clock generation circuit, the phase comparison unit 1 compares the phases of the input signal Si and the comparison signal S6a, and outputs an output signal S1 proportional to the phase difference. The output signal S1 is smoothed by the filter unit 2, and an output signal S2 is output. The output signal S2 is input to the switching unit 3, output from the selected output terminal, and
One of 1,..., 4-n (for example, oscillator 4-1)
Is input to The oscillator 4-1 outputs an output signal S4-1 having a frequency corresponding to the output signal S2. Output signal S4-
1 is input to the switching unit 5 and the output signal S5
Is output. The output signal S5 is frequency-divided by the frequency divider 6, and the frequency divider 6 outputs the comparison signal S6a and the output signal S6b. [0004] However, in the conventional clock generation circuit of FIG. 2, when the number of types of frequencies required for the output signal S6b increases, the oscillators 4-1 to.
Since it is necessary to increase the number of −n accordingly, there is a problem that the circuit scale and power consumption increase. According to the present invention, there is provided a clock generating circuit, wherein an input signal having a predetermined frequency is provided, and a pulse width of the input signal is set to a first value.
Pulse width conversion means for generating and outputting a reference signal by converting to a pulse width of one cycle of the clock, and clock frequency setting for setting the frequencies of the first clock, the enable signal, and the second clock Information is provided, and when the enable signal is in the active mode, the first clock is frequency-divided by a frequency division ratio based on the clock frequency setting signal to generate and output the comparison signal; Frequency dividing means for counting clocks and generating and outputting a count value in a range based on the clock frequency setting information;
The reference signal and the comparison signal are taken in synchronization with the first clock, the phases of the reference signal and the comparison signal are compared, and the phase difference between the reference signal and the comparison signal is determined by the first clock. Phase comparison means for generating and outputting a phase difference number signal represented by the number of one cycle of the above, and generating and outputting a phase difference direction signal representing a phase advance or delay of the phase of the comparison signal with respect to the reference signal; , The phase difference number signal, the phase difference direction signal, the count value, the first clock and the clock frequency setting information are given, based on the phase difference number signal and the phase difference direction signal,
Clock control means for generating a clock control signal for controlling the amount of delay or advance of the phase of the second clock in accordance with the clock frequency setting information, and outputting the clock control signal in synchronization with the first clock And the clock control signal, the first clock, and the clock frequency setting information.
, A third clock having a cycle longer than the cycle of the second clock and a fourth clock having a cycle shorter than the cycle of the second clock are generated, and the third and fourth clocks are generated. Clock generating means for generating and outputting the second clock and the active mode enable signal having a frequency corresponding to the clock frequency setting information in combination based on the clock control signal. By adopting such a configuration, the pulse width of the input signal is converted into a pulse width of one cycle of the first clock by the pulse width conversion means, and the reference signal is output. When the enable signal is in the active mode, the first clock is frequency-divided by the frequency dividing means at the frequency division ratio based on the clock frequency setting signal, and the comparison signal is output. Also, the first
Is counted by the frequency dividing means, and a count value in a range based on the clock frequency setting information is output. The reference signal and the comparison signal are taken into phase comparison means in synchronization with the first clock, and the phases are compared, and a phase difference number signal and a phase difference direction signal are output. In the clock control means,
A clock control signal is generated based on the count value, the phase difference number signal, and the phase difference direction signal in accordance with the clock frequency setting information, and is output in synchronization with the first clock.
The clock generation means combines the third clock and the fourth clock based on the clock control signal, and outputs a second clock having a frequency corresponding to the clock frequency setting information and an enable signal in the active mode. FIG. 1 is a configuration diagram of a clock generation circuit showing an embodiment of the present invention. This clock generation circuit has an oscillator 11 that outputs a first clock S11. On the output side of the oscillator 11, a pulse width conversion means (for example, a pulse width conversion unit) 12 and a frequency division means (for example, a frequency division unit) 13 are connected. Pulse width converter 1
A circuit 2 converts the pulse width of the input signal Si into a pulse width of one cycle of the clock S11 to generate and output the reference signal S12. The frequency divider 13 is provided with an enable signal S16
When a is in the active mode, the clock S11 is frequency-divided at a frequency division ratio based on the clock frequency setting signal rt to generate and output a comparison signal S13a.
This circuit counts 11 and generates and outputs a count value S13b in a range based on the clock frequency setting information rt. A phase comparison unit (for example, a phase comparison unit) 14 is connected to the output side of the pulse width conversion unit 12, the first output side of the frequency division unit 13, and the output side of the oscillator 11. The phase comparator 14 takes in the reference signal S12 and the comparison signal S13a in synchronization with the clock S11, compares the phases, and generates and outputs a phase difference number signal S14a and a phase difference direction signal S14b. It is. The phase difference number signal S14a is a signal representing the phase difference between the reference signal S12 and the comparison signal S13a by the number of one cycle of the clock S11.
The phase difference direction signal S14b is a signal indicating a phase advance or a phase delay of the comparison signal S13a with respect to the reference signal S12. Clock control means (for example, a clock control unit) 15 is connected to the output side of the phase comparison unit 14, the second output side of the frequency division unit 13, and the output side of the oscillator 11. The clock control unit 15 has a count value S13
b, phase difference number signal S14a and phase difference direction signal S14b
, A clock control signal S15 for controlling the amount of delay or advance of the phase of the second clock S16b is generated corresponding to the clock frequency setting information rt,
11 is a circuit that outputs the data in synchronization with 11. Clock control unit 1
Clock output means (for example, a clock generator) 16 is connected to the output side of the oscillator 5 and the output side of the oscillator 11. The clock generation unit 16 is a circuit that counts the clock S11 based on the clock control signal S15, and generates and outputs a clock S16b having a frequency corresponding to the clock frequency setting information rt and an active mode enable signal S16a. A first output side of the clock generation unit 16 is connected to the frequency division unit 13, and a second output side is connected to a transmission device (not shown) operating based on the clock S16b. FIG. 3 is a block diagram showing an example of the pulse width converter 12 in FIG. The pulse width conversion unit 12 receives the input signal Si in synchronization with the clock S11 and outputs an output signal S12a.
"D-FF") 12. D-FF12
Outputs the output signal S12b by synchronizing with the output signal S12a in synchronization with the clock S11.
3 are connected. The output side of the D-FF 13 is connected to an inverter 12c that inverts the output signal S12b and outputs an output signal S12c. An output signal S12 is provided on the output side of the inverter 12c and the output side of the D-FF12.
a and the output signal S12c to obtain the output signal S1
Each input terminal of a two-input AND circuit 12d that outputs 2d is connected to each other. The output side of the AND circuit 12d is connected to a D-FF 12e that takes in the output signal S12d in synchronization with the clock S11 and outputs the output signal S12. FIG. 4 is a block diagram showing an example of the frequency divider 13 in FIG. 1, and FIG. 5 is a diagram showing the truth values of the signals of the respective parts in the frequency divider 13 in FIG. The frequency divider 13 outputs the clear signal clr in the non-active mode and the enable signal S
When 16a is in the active mode, it has a counter 13a that divides the clock S11 by a division ratio based on the clock frequency setting signal rt to generate and output a comparison signal S13a. On the output side of the counter 13a, the comparison signal S
A decoder 13b that decodes 13a to generate and output a count value S13b is connected. FIG. 6 is a block diagram showing an example of the phase comparison section 14 in FIG. 1, and FIG. 7 is a view showing the truth values of signals of the respective sections in the RS-FF 14a in FIG. This phase comparison unit 14 is a set / reset type flip-flop (hereinafter, referred to as a flip-flop).
"RS-FF") 14a and the phase difference direction detection unit 1
4b. The RS-FF 14a outputs the reference signal S12 when the clear signal clr is in the non-active mode.
And a comparison signal S13a in synchronization with the clock S11 to compare the phases and output a phase difference number signal S14a. The phase difference direction detector 14b outputs the clear signal cl
When r is in the non-active mode, the circuit receives the reference signal S12, the comparison signal S13a, and the clock S11 to generate and output a phase difference direction signal S14b. FIG. 8 shows a phase difference direction detector 14b in FIG.
FIG. 3 is a configuration diagram illustrating an example of the configuration. 9 (a) and 9 (b) are diagrams showing the truth values of the signals of the respective parts in the phase difference direction detector 14b of FIG. 8, and FIG. 9 (a) shows the combination circuit 14b-
1B shows the truth value of the D-FF 14b-2, and FIG. 4B shows the truth value of the combination circuit 14b-3 and the D-FF 14b-4. The phase difference direction detector 14b outputs the reference signal S
12. Combination circuit 1 that receives comparison signal S13a and output signal S14b-2 and outputs output signal S14b-1
4b-1. The combination circuit 14b-1 includes a plurality of AND gates, OR gates, and the like. The clear signal clr is provided on the output side of the combination circuit 14b-1.
Is in the non-active mode, the output signal S14b-1
Is synchronized with the clock S11 and the output signal S14b
The D-FF 14b-2 that outputs -2 is connected.
The output side of the D-FF 14b-2 is connected to the combination circuit 14b-
1 and to the combination circuit 14b-3. The combination circuit 14b-3 outputs the output signal S
14b-2, a reference signal S12, a comparison signal S13a, and an output signal S14b-4. On the output side of the combination circuit 14b-3, when the clear signal clr is in the non-active mode, the D-FF1 which takes in the output signal S14b-3 in synchronization with the clock S11 and outputs the phase difference direction signal S14b.
4b-4 are connected. The output side of the D-FF 14b-4 is connected to the combination circuit 14b-3. FIG. 10 is a block diagram showing an example of the clock control unit 15 in FIG. 1, and FIG. 11 is a diagram showing the truth values of the signals of each unit in the clock control unit 15 in FIG. In FIG. 11, the frequency of the clock S16b is 1536 kHz.
An example in which the clock frequency setting information rt is set to be z is shown. The clock control unit 15 includes a combination circuit 15a that inputs the count value S13b, the phase difference number signal S14a, the phase difference direction signal S14b, and the clock frequency setting information rt and outputs an output signal S15a. The combination circuit 15a includes a plurality of AND gates, OR gates, and the like. The output side of the combination circuit 15a receives the output signal S15a in synchronization with the clock S11 and outputs a clock control signal S15.
F15b is connected. FIG. 12 is a block diagram showing an example of the clock generator 16 in FIG. This clock generation unit 16
It has a counting unit 16a and a D-FF 16b. The counting unit 16a counts the clock S11 based on the clock control signal S15 and the clock S16b, and outputs an output signal S16t having a frequency corresponding to the clock frequency setting information rt and an active mode enable signal S16.
This is a circuit that generates a and outputs it from the first and second output sides. On the first output side of the counting unit 16a,
A D-FF 16b that captures the output signal S16t in synchronization with the clock S11 and outputs the clock S16b is connected. The output side of the D-FF 16b is a counting unit 16a.
It is connected to the. FIG. 13 is a block diagram showing an example of the counting section 16a in FIG. The counting unit 16a has a counter 16a-1 that counts the clock S11 based on the clock control signal S15 and the clock S16b, and outputs an output signal S16a-1 having a frequency corresponding to the clock frequency setting information rt. Counter 16a-
The decoder 16a-2 that decodes the output signal S16a-1 and generates and outputs the output signal S16t and the enable signal S16a is connected to the output side of the decoder 1. FIG. 14 is a time chart for explaining the operation of the pulse width converter 12 in FIG. 3, FIG. 15 is a state transition diagram for explaining the operation of the frequency divider 13 in FIG. 4, and FIG.
FIG. 14 is a state transition diagram for explaining the operation of FIG. Hereinafter, the operations (a) to (e) of each unit in the clock generation circuit of FIG. 1 will be described with reference to these drawings. (A) Operation of Pulse Width Converter 12 As shown in FIG. 14, the pulse width of the input signal Si is converted by the pulse width converter 12 into a pulse width of one cycle of the clock S11, and the reference signal S12 is output. . Reference signal S1
2 is sent to the phase comparison unit 14. (B) Operation of frequency divider 13 As shown in FIG. 15, when the enable signal S16a is in the active mode, the clock S11 is frequency-divided by the frequency divider 13 at a frequency division ratio based on the clock frequency setting signal rt.
The comparison signal S13a is output and sent to the phase comparison unit 14. The clock S11 is counted by the frequency divider 13, and a count value S13b in a range based on the clock frequency setting information rt is output. The count value S13b is
It is sent to the clock control unit 15. (C) The operation reference signal S12 and the comparison signal S13a of the phase comparator 14 are the clock S1
1 and is taken into the phase comparator 14 to be compared in phase, and the phase difference number signal S14a and the phase difference direction signal S14b
Is output. (D) Operation of the Clock Control Unit 15 The clock control unit 15 uses the count value S13b, the phase difference number signal S14a, and the phase difference direction signal S14b based on:
The clock control signal S15 is the clock frequency setting information rt
And is output in synchronization with the clock S11. In this case, the clock control unit 15 outputs the reference signal S1
2 and a comparison signal S13a, and outputs a clock control signal S15 according to the phase difference in each cycle of phase comparison. (E) Operation of the clock generator 16 For example, the frequency of the clock S11 is 100 MHz, the frequency of the comparison signal S13a is 8 kHz, and the frequency of the clock S16 is
When the frequency of b is set to 1536 kHz, the clock S
16b is about 651 (ns), and the comparison signal S1
Since one cycle of 3a is 125 (μs), the comparison signal S13
There are 192 clocks S16b during one cycle of a. Since one cycle of the clock S11 is 10 (ns), the clock generation unit 16 generates 660 (ns) (= 1515) by continuing 66 clocks of 10 (ns).
A third clock ck1 having a cycle of (kHz) is generated, and 6 (10 (ns) clocks are continuously generated by 65 clocks).
A fourth clock ck2 having a period of 50 (ns) (= 1538 kHz) is generated. The reference signal S12 and the comparison signal S12 are obtained by the phase difference number signal S14a and the phase difference direction signal S14b.
13a, the clock generation unit 1
6, the clock S11 is counted based on the clock control signal S15, and an output signal S16t having a frequency corresponding to the clock frequency setting information rt and an active mode enable signal S16a are output, as shown in FIG. Is done. In this case, based on the clock control signal S15, 172 clocks ck1 and 20
Clocks ck2 and the comparison signal S13a
There are 192 clocks during one cycle of
An output signal S16t of kHz is generated. Output signal S1
6t is taken into the D-FF 16b in synchronization with the clock S11, and the clock S16b is output from the D-FF 16b. When the phase of the comparison signal S13a lags behind the reference signal S12, the counting unit 16a combines the 171 clocks ck1 and the 21 clocks ck2 based on the clock control signal S15, and generates the clock S1.
6b follows 1536 kHz. When the phase of the comparison signal S13a is ahead of the phase of the reference signal S12, the counting unit 16a outputs 1 based on the clock control signal S15.
73 clocks ck1 and 19 clocks ck2 are combined, and clock S16b follows 1536 kHz. As described above, in the present embodiment, the clock control unit 15 generates the clock control signal S15 according to the phase difference between the reference signal S12 and the comparison signal S13a, and the clock generation unit 16 generates the clock control signal S15. Based on the combination of the clock ck1 and the clock ck28 based on the clock S
Since the clock generation circuit 16b is generated, a clock generation circuit that generates the clock S16b having a frequency corresponding to the clock frequency setting information rt can be realized with a small-scale and low-power-consumption circuit configuration. The present invention is not limited to the above embodiment,
Various modifications are possible. For example, there are the following modifications. (A) The present invention can be applied to all devices that are used by switching a plurality of types of frequencies, such as a microcomputer system and a measuring device. (B) In the embodiment, the frequency of the clock S16b is set to 1
Although the example in which the frequency is set to 536 kHz has been described, a frequency of another value may be set. As described in detail above, according to the present invention, the clock control means generates a clock control signal corresponding to the phase difference between the reference signal and the comparison signal, and the clock generation means generates the clock control signal. Since the third clock and the fourth clock are combined to generate the second clock based on the clock control signal, the clock generation for generating the second clock having the frequency corresponding to the clock frequency setting information is performed. Circuit
It can be realized with a small-scale and low power consumption circuit configuration.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of a clock generation circuit according to an embodiment of the present invention. FIG. 2 is a configuration diagram of a conventional clock generation circuit. FIG. 3 is a configuration diagram of a pulse width conversion unit 12 in FIG. 1; FIG. 4 is a configuration diagram of a frequency divider 13 in FIG. FIG. 5 is a diagram showing truth values in a frequency divider 13 of FIG. 4; 6 is a configuration diagram of a phase comparison unit 14 in FIG. 7 is a diagram showing truth values in the RS-FF 14a in FIG. 8 is a configuration diagram of a phase difference direction detection unit 14b in FIG. 9 is a diagram showing truth values in the phase difference direction detection unit 14b in FIG. FIG. 10 is a configuration diagram of a clock control unit 15 in FIG. 1; 11 is a diagram showing truth values in the clock control unit 15 of FIG. FIG. 12 is a configuration diagram of a clock generation unit 16 in FIG. 1; 13 is a configuration diagram of a counting unit 16a in FIG. FIG. 14 is a time chart of FIG. 3; FIG. 15 is a state transition diagram of FIG. FIG. 16 is a state transition diagram of FIG. [Description of Signs] 12 Pulse width converter 13 Frequency divider 14 Phase comparator 15 Clock controller 16 Clock generator

──────────────────────────────────────────────────続 き Continuation of the front page (56) References Japanese Utility Model Showa 62-100723 (JP, U) Japanese Utility Model Showa 60-167438 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03L 7/06 G06F 1/04 H03K 5/135 H03B 28/00

Claims (1)

(57) [Claim 1] An input signal of a predetermined frequency is provided, and a pulse width of the input signal is converted into a pulse width of one cycle of the first clock to generate a reference signal. And a clock frequency setting information for setting a frequency of the first clock, the enable signal, and a frequency of the second clock. When the enable signal is in the active mode, Is divided by a frequency division ratio based on the clock frequency setting signal to generate and output a comparison signal, and the first clock is counted to count a value in a range based on the clock frequency setting information. Frequency dividing means for generating and outputting the reference signal and the comparison signal in synchronization with the first clock, comparing the phases of the reference signal and the comparison signal, and comparing the reference signal with the comparison signal. signal And outputs a phase difference number signal representing the phase difference by the number of one cycle of the first clock, and outputs a phase difference direction signal indicating a leading phase or a lagging phase of the comparison signal with respect to the reference signal. A phase comparing means for generating and outputting the phase difference number signal, the phase difference direction signal, the count value,
Clock and clock frequency setting information, and based on the phase difference number signal and the phase difference direction signal, a clock control signal for controlling the amount of delay or advance of the phase of the second clock. A clock control means for generating in response to the frequency setting information and outputting in synchronization with the first clock; and inputting the clock control signal, the first clock and the clock frequency setting information, and The second
Generating a third clock having a period longer than the period of the second clock and a fourth clock having a period shorter than the period of the second clock, and generating the third and fourth clocks based on the clock control signal. Clock generating means for generating and outputting the second clock having a frequency corresponding to the clock frequency setting information and the enable signal in the active mode.